1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _MACTX_USER_DESC_COMMON_H_ 19 #define _MACTX_USER_DESC_COMMON_H_ 20 21 #include "unallocated_ru_160_info.h" 22 #include "ru_allocation_160_info.h" 23 #define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 24 25 struct mactx_user_desc_common { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t num_users : 6, 28 reserved_0b : 5, 29 ltf_size : 2, 30 reserved_0c : 3, 31 he_stf_long : 1, 32 reserved_0d : 7, 33 num_users_he_sigb_band0 : 8; 34 uint32_t num_ltf_symbols : 3, 35 reserved_1a : 5, 36 num_users_he_sigb_band1 : 8, 37 reserved_1b : 16; 38 uint32_t packet_extension_a_factor : 2, 39 packet_extension_pe_disambiguity : 1, 40 packet_extension : 3, 41 reserved : 2, 42 he_sigb_dcm : 1, 43 reserved_2b : 7, 44 he_sigb_compression : 1, 45 reserved_2c : 15; 46 uint32_t he_sigb_0_mcs : 3, 47 reserved_3a : 13, 48 num_he_sigb_sym : 5, 49 center_ru_0 : 1, 50 center_ru_1 : 1, 51 reserved_3b : 1, 52 ftm_en : 1, 53 pe_nss : 3, 54 pe_ltf_size : 2, 55 pe_content : 1, 56 pe_chain_csd_en : 1; 57 struct ru_allocation_160_info ru_allocation_0123_details; 58 struct ru_allocation_160_info ru_allocation_4567_details; 59 struct unallocated_ru_160_info ru_allocation_160_0_details; 60 struct unallocated_ru_160_info ru_allocation_160_1_details; 61 uint32_t num_data_symbols : 16, 62 ndp_ru_tone_set_index : 7, 63 ndp_feedback_status : 1, 64 doppler_indication : 1, 65 reserved_14a : 7; 66 uint32_t spatial_reuse : 16, 67 reserved_15a : 16; 68 #else 69 uint32_t num_users_he_sigb_band0 : 8, 70 reserved_0d : 7, 71 he_stf_long : 1, 72 reserved_0c : 3, 73 ltf_size : 2, 74 reserved_0b : 5, 75 num_users : 6; 76 uint32_t reserved_1b : 16, 77 num_users_he_sigb_band1 : 8, 78 reserved_1a : 5, 79 num_ltf_symbols : 3; 80 uint32_t reserved_2c : 15, 81 he_sigb_compression : 1, 82 reserved_2b : 7, 83 he_sigb_dcm : 1, 84 reserved : 2, 85 packet_extension : 3, 86 packet_extension_pe_disambiguity : 1, 87 packet_extension_a_factor : 2; 88 uint32_t pe_chain_csd_en : 1, 89 pe_content : 1, 90 pe_ltf_size : 2, 91 pe_nss : 3, 92 ftm_en : 1, 93 reserved_3b : 1, 94 center_ru_1 : 1, 95 center_ru_0 : 1, 96 num_he_sigb_sym : 5, 97 reserved_3a : 13, 98 he_sigb_0_mcs : 3; 99 struct ru_allocation_160_info ru_allocation_0123_details; 100 struct ru_allocation_160_info ru_allocation_4567_details; 101 struct unallocated_ru_160_info ru_allocation_160_0_details; 102 struct unallocated_ru_160_info ru_allocation_160_1_details; 103 uint32_t reserved_14a : 7, 104 doppler_indication : 1, 105 ndp_feedback_status : 1, 106 ndp_ru_tone_set_index : 7, 107 num_data_symbols : 16; 108 uint32_t reserved_15a : 16, 109 spatial_reuse : 16; 110 #endif 111 }; 112 113 #define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000 114 #define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 115 #define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 116 #define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f 117 118 #define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000 119 #define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 120 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 121 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0 122 123 #define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000 124 #define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 125 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 126 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800 127 128 #define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000 129 #define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 130 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 131 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000 132 133 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000 134 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 135 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 136 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000 137 138 #define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000 139 #define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 140 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 141 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000 142 143 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000 144 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 145 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 146 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000 147 148 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004 149 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0 150 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2 151 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007 152 153 #define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004 154 #define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3 155 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7 156 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8 157 158 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004 159 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8 160 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15 161 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00 162 163 #define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004 164 #define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16 165 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31 166 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000 167 168 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008 169 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 170 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 171 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 172 173 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008 174 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 175 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 176 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 177 178 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008 179 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 180 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 181 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038 182 183 #define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008 184 #define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 185 #define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 186 #define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0 187 188 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008 189 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 190 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 191 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100 192 193 #define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008 194 #define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 195 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 196 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00 197 198 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008 199 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 200 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 201 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000 202 203 #define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008 204 #define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 205 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 206 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000 207 208 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c 209 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0 210 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2 211 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007 212 213 #define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c 214 #define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3 215 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15 216 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8 217 218 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c 219 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16 220 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20 221 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000 222 223 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c 224 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21 225 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21 226 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000 227 228 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c 229 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22 230 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22 231 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000 232 233 #define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c 234 #define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23 235 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23 236 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000 237 238 #define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c 239 #define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24 240 #define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24 241 #define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000 242 243 #define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c 244 #define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25 245 #define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27 246 #define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000 247 248 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c 249 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28 250 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29 251 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000 252 253 #define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c 254 #define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30 255 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30 256 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000 257 258 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c 259 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31 260 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31 261 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000 262 263 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010 264 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 265 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 266 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff 267 268 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010 269 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 270 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 271 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 272 273 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010 274 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 275 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 276 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000 277 278 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010 279 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 280 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 281 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 282 283 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010 284 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 285 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 286 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 287 288 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014 289 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 290 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 291 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff 292 293 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014 294 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 295 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 296 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 297 298 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014 299 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18 300 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31 301 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000 302 303 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018 304 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 305 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 306 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff 307 308 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018 309 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 310 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 311 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 312 313 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018 314 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 315 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 316 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000 317 318 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c 319 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 320 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 321 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff 322 323 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c 324 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 325 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 326 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 327 328 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c 329 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18 330 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31 331 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000 332 333 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020 334 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 335 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 336 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff 337 338 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020 339 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 340 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 341 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 342 343 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020 344 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 345 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 346 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000 347 348 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020 349 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 350 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 351 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 352 353 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020 354 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 355 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 356 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 357 358 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024 359 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 360 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 361 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff 362 363 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024 364 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 365 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 366 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 367 368 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024 369 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18 370 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31 371 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000 372 373 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028 374 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 375 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 376 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff 377 378 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028 379 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 380 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 381 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 382 383 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028 384 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 385 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 386 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000 387 388 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c 389 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 390 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 391 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff 392 393 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c 394 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 395 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 396 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 397 398 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c 399 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18 400 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31 401 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000 402 403 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030 404 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 405 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 406 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff 407 408 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030 409 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 410 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 411 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 412 413 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030 414 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 415 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 416 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 417 418 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030 419 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 420 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 421 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 422 423 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034 424 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0 425 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7 426 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff 427 428 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034 429 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8 430 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15 431 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 432 433 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034 434 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16 435 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23 436 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 437 438 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034 439 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24 440 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31 441 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 442 443 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038 444 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 445 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 446 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff 447 448 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038 449 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 450 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 451 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000 452 453 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038 454 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 455 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 456 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000 457 458 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038 459 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 460 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 461 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000 462 463 #define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038 464 #define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 465 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 466 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000 467 468 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c 469 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0 470 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15 471 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff 472 473 #define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c 474 #define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16 475 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31 476 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000 477 478 #endif 479