1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _MON_BUFFER_ADDR_H_ 19 #define _MON_BUFFER_ADDR_H_ 20 21 #define NUM_OF_DWORDS_MON_BUFFER_ADDR 3 22 23 struct mon_buffer_addr { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t buffer_virt_addr_31_0 : 32; 26 uint32_t buffer_virt_addr_63_32 : 32; 27 uint32_t dma_length : 12, 28 reserved_2a : 4, 29 msdu_continuation : 1, 30 truncated : 1, 31 reserved_2b : 14; 32 #else 33 uint32_t buffer_virt_addr_31_0 : 32; 34 uint32_t buffer_virt_addr_63_32 : 32; 35 uint32_t reserved_2b : 14, 36 truncated : 1, 37 msdu_continuation : 1, 38 reserved_2a : 4, 39 dma_length : 12; 40 #endif 41 }; 42 43 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 44 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 45 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 46 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 47 48 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 49 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0 50 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31 51 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 52 53 #define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008 54 #define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 55 #define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 56 #define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff 57 58 #define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008 59 #define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 60 #define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 61 #define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000 62 63 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008 64 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 65 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 66 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000 67 68 #define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008 69 #define MON_BUFFER_ADDR_TRUNCATED_LSB 17 70 #define MON_BUFFER_ADDR_TRUNCATED_MSB 17 71 #define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000 72 73 #define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008 74 #define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 75 #define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 76 #define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000 77 78 #endif 79