1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _MON_INGRESS_RING_H_ 19 #define _MON_INGRESS_RING_H_ 20 21 #include "buffer_addr_info.h" 22 #define NUM_OF_DWORDS_MON_INGRESS_RING 4 23 24 struct mon_ingress_ring { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct buffer_addr_info buffer_addr_info_details; 27 uint32_t buffer_virt_addr_31_0 : 32; 28 uint32_t buffer_virt_addr_63_32 : 32; 29 #else 30 struct buffer_addr_info buffer_addr_info_details; 31 uint32_t buffer_virt_addr_31_0 : 32; 32 uint32_t buffer_virt_addr_63_32 : 32; 33 #endif 34 }; 35 36 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 37 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 38 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 39 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 40 41 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 42 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 43 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 44 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 45 46 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 47 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 48 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 49 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 50 51 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 52 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 53 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 54 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 55 56 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 57 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 58 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 59 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 60 61 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 62 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 63 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 64 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 65 66 #endif 67