1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _PDG_RESPONSE_H_ 19 #define _PDG_RESPONSE_H_ 20 21 #include "pdg_response_rate_setting.h" 22 #define NUM_OF_DWORDS_PDG_RESPONSE 12 23 24 struct pdg_response { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct pdg_response_rate_setting hw_response_rate_info; 27 uint32_t hw_response_tx_duration : 16, 28 rx_duration_field : 16; 29 uint32_t punctured_response_transmission : 1, 30 cca_subband_channel_bonding_mask : 16, 31 scrambler_seed_override : 2, 32 response_density_valid : 1, 33 response_density : 5, 34 more_data : 1, 35 duration_indication : 1, 36 relayed_frame : 1, 37 address_indicator : 1, 38 bandwidth : 3; 39 uint32_t ack_id : 16, 40 block_ack_bitmap : 16; 41 uint32_t response_frame_type : 4, 42 ack_id_ext : 10, 43 ftm_en : 1, 44 group_id : 6, 45 sta_partial_aid : 11; 46 uint32_t ndp_ba_start_seq_ctrl : 12, 47 active_channel : 3, 48 txop_duration_all_ones : 1, 49 frame_length : 16; 50 #else 51 struct pdg_response_rate_setting hw_response_rate_info; 52 uint32_t rx_duration_field : 16, 53 hw_response_tx_duration : 16; 54 uint32_t bandwidth : 3, 55 address_indicator : 1, 56 relayed_frame : 1, 57 duration_indication : 1, 58 more_data : 1, 59 response_density : 5, 60 response_density_valid : 1, 61 scrambler_seed_override : 2, 62 cca_subband_channel_bonding_mask : 16, 63 punctured_response_transmission : 1; 64 uint32_t block_ack_bitmap : 16, 65 ack_id : 16; 66 uint32_t sta_partial_aid : 11, 67 group_id : 6, 68 ftm_en : 1, 69 ack_id_ext : 10, 70 response_frame_type : 4; 71 uint32_t frame_length : 16, 72 txop_duration_all_ones : 1, 73 active_channel : 3, 74 ndp_ba_start_seq_ctrl : 12; 75 #endif 76 }; 77 78 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000 79 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 80 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 81 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001 82 83 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 84 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 85 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 86 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe 87 88 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000 89 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 90 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 91 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000 92 93 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000 94 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 95 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 96 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000 97 98 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000 99 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 100 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 101 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000 102 103 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000 104 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 105 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 106 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000 107 108 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004 109 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0 110 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7 111 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff 112 113 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004 114 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8 115 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15 116 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00 117 118 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004 119 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16 120 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18 121 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000 122 123 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 124 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19 125 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26 126 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000 127 128 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004 129 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27 130 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29 131 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000 132 133 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004 134 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30 135 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30 136 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000 137 138 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 139 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31 140 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31 141 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000 142 143 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008 144 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 145 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 146 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f 147 148 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008 149 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 150 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 151 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070 152 153 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008 154 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 155 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 156 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080 157 158 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008 159 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 160 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 161 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00 162 163 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008 164 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 165 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 166 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000 167 168 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008 169 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 170 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 171 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000 172 173 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c 174 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0 175 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7 176 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff 177 178 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c 179 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8 180 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9 181 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300 182 183 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c 184 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10 185 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13 186 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00 187 188 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c 189 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14 190 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15 191 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000 192 193 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c 194 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16 195 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23 196 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000 197 198 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c 199 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24 200 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31 201 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000 202 203 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010 204 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 205 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 206 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001 207 208 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 209 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 210 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 211 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e 212 213 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 214 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 215 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 216 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 217 218 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 219 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 220 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 221 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 222 223 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010 224 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 225 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 226 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000 227 228 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 229 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 230 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 231 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 232 233 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 234 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 235 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 236 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000 237 238 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 239 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 240 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 241 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 242 243 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010 244 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 245 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 246 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000 247 248 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010 249 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 250 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 251 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000 252 253 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 254 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 255 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 256 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 257 258 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 259 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 260 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 261 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 262 263 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 264 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 265 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 266 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 267 268 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 269 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 270 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 271 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000 272 273 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010 274 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 275 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 276 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000 277 278 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 279 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0 280 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3 281 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f 282 283 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 284 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4 285 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7 286 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 287 288 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014 289 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8 290 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9 291 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300 292 293 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014 294 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10 295 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10 296 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400 297 298 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014 299 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11 300 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13 301 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800 302 303 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014 304 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14 305 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18 306 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000 307 308 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 309 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 310 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 311 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 312 313 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014 314 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20 315 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25 316 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000 317 318 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 319 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 320 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 321 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 322 323 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 324 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 325 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 326 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff 327 328 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 329 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 330 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 331 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 332 333 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 334 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 335 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 336 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 337 338 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 339 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 340 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 341 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 342 343 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 344 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 345 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 346 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 347 348 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 349 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 350 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 351 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 352 353 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 354 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 355 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 356 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 357 358 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c 359 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0 360 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15 361 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff 362 363 #define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c 364 #define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16 365 #define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31 366 #define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000 367 368 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020 369 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 370 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 371 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001 372 373 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020 374 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 375 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 376 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe 377 378 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020 379 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 380 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 381 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000 382 383 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020 384 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 385 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 386 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000 387 388 #define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020 389 #define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 390 #define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 391 #define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000 392 393 #define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020 394 #define PDG_RESPONSE_MORE_DATA_LSB 25 395 #define PDG_RESPONSE_MORE_DATA_MSB 25 396 #define PDG_RESPONSE_MORE_DATA_MASK 0x02000000 397 398 #define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020 399 #define PDG_RESPONSE_DURATION_INDICATION_LSB 26 400 #define PDG_RESPONSE_DURATION_INDICATION_MSB 26 401 #define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000 402 403 #define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020 404 #define PDG_RESPONSE_RELAYED_FRAME_LSB 27 405 #define PDG_RESPONSE_RELAYED_FRAME_MSB 27 406 #define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000 407 408 #define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020 409 #define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 410 #define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 411 #define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000 412 413 #define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020 414 #define PDG_RESPONSE_BANDWIDTH_LSB 29 415 #define PDG_RESPONSE_BANDWIDTH_MSB 31 416 #define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000 417 418 #define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024 419 #define PDG_RESPONSE_ACK_ID_LSB 0 420 #define PDG_RESPONSE_ACK_ID_MSB 15 421 #define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff 422 423 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024 424 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16 425 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31 426 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000 427 428 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028 429 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 430 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 431 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f 432 433 #define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028 434 #define PDG_RESPONSE_ACK_ID_EXT_LSB 4 435 #define PDG_RESPONSE_ACK_ID_EXT_MSB 13 436 #define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0 437 438 #define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028 439 #define PDG_RESPONSE_FTM_EN_LSB 14 440 #define PDG_RESPONSE_FTM_EN_MSB 14 441 #define PDG_RESPONSE_FTM_EN_MASK 0x00004000 442 443 #define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028 444 #define PDG_RESPONSE_GROUP_ID_LSB 15 445 #define PDG_RESPONSE_GROUP_ID_MSB 20 446 #define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000 447 448 #define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028 449 #define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 450 #define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 451 #define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000 452 453 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c 454 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0 455 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11 456 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff 457 458 #define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c 459 #define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12 460 #define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14 461 #define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000 462 463 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c 464 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15 465 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15 466 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000 467 468 #define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c 469 #define PDG_RESPONSE_FRAME_LENGTH_LSB 16 470 #define PDG_RESPONSE_FRAME_LENGTH_MSB 31 471 #define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000 472 473 #endif 474