1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RECEIVE_PKT_START_INFO_H_ 19 #define _RECEIVE_PKT_START_INFO_H_ 20 21 #define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 22 23 struct receive_pkt_start_info { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t reception_type : 4, 26 rx_chain_mask_type : 1, 27 receive_bandwidth : 3, 28 rx_chain_mask : 8, 29 phy_ppdu_id : 16; 30 uint32_t ppdu_start_timestamp_31_0 : 32; 31 uint32_t ppdu_start_timestamp_63_32 : 32; 32 uint32_t preamble_time_to_rxframe : 8, 33 standalone_sniffer_mode : 1, 34 reserved_3a : 23; 35 #else 36 uint32_t phy_ppdu_id : 16, 37 rx_chain_mask : 8, 38 receive_bandwidth : 3, 39 rx_chain_mask_type : 1, 40 reception_type : 4; 41 uint32_t ppdu_start_timestamp_31_0 : 32; 42 uint32_t ppdu_start_timestamp_63_32 : 32; 43 uint32_t reserved_3a : 23, 44 standalone_sniffer_mode : 1, 45 preamble_time_to_rxframe : 8; 46 #endif 47 }; 48 49 #define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 50 #define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 51 #define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 52 #define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f 53 54 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 55 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 56 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 57 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 58 59 #define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 60 #define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 61 #define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 62 #define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 63 64 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 65 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 66 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 67 #define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 68 69 #define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 70 #define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 71 #define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 72 #define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 73 74 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 75 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 76 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 77 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff 78 79 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 80 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 81 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 82 #define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff 83 84 #define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c 85 #define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 86 #define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 87 #define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff 88 89 #define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c 90 #define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 91 #define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 92 #define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 93 94 #define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c 95 #define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 96 #define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 97 #define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 98 99 #endif 100