xref: /wlan-driver/fw-api/hw/peach/v2/receive_user_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _RECEIVE_USER_INFO_H_
19 #define _RECEIVE_USER_INFO_H_
20 
21 #define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
22 
23 struct receive_user_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t phy_ppdu_id                                             : 16,
26                       user_rssi                                               :  8,
27                       pkt_type                                                :  4,
28                       stbc                                                    :  1,
29                       reception_type                                          :  3;
30              uint32_t rate_mcs                                                :  4,
31                       sgi                                                     :  2,
32                       __reserved_g_0004                                          :  1,
33                       reserved_1a                                             :  1,
34                       mimo_ss_bitmap                                          :  8,
35                       receive_bandwidth                                       :  3,
36                       reserved_1b                                             :  5,
37                       dl_ofdma_user_index                                     :  8;
38              uint32_t dl_ofdma_content_channel                                :  1,
39                       reserved_2a                                             :  7,
40                       nss                                                     :  3,
41                       stream_offset                                           :  3,
42                       sta_dcm                                                 :  1,
43                       ldpc                                                    :  1,
44                       ru_type_80_0                                            :  4,
45                       ru_type_80_1                                            :  4,
46                       ru_type_80_2                                            :  4,
47                       ru_type_80_3                                            :  4;
48              uint32_t ru_start_index_80_0                                     :  6,
49                       reserved_3a                                             :  2,
50                       ru_start_index_80_1                                     :  6,
51                       reserved_3b                                             :  2,
52                       ru_start_index_80_2                                     :  6,
53                       reserved_3c                                             :  2,
54                       ru_start_index_80_3                                     :  6,
55                       reserved_3d                                             :  2;
56              uint32_t user_fd_rssi_seg0                                       : 32;
57              uint32_t user_fd_rssi_seg1                                       : 32;
58              uint32_t user_fd_rssi_seg2                                       : 32;
59              uint32_t user_fd_rssi_seg3                                       : 32;
60 #else
61              uint32_t reception_type                                          :  3,
62                       stbc                                                    :  1,
63                       pkt_type                                                :  4,
64                       user_rssi                                               :  8,
65                       phy_ppdu_id                                             : 16;
66              uint32_t dl_ofdma_user_index                                     :  8,
67                       reserved_1b                                             :  5,
68                       receive_bandwidth                                       :  3,
69                       mimo_ss_bitmap                                          :  8,
70                       reserved_1a                                             :  1,
71                       __reserved_g_0004                                          :  1,
72                       sgi                                                     :  2,
73                       rate_mcs                                                :  4;
74              uint32_t ru_type_80_3                                            :  4,
75                       ru_type_80_2                                            :  4,
76                       ru_type_80_1                                            :  4,
77                       ru_type_80_0                                            :  4,
78                       ldpc                                                    :  1,
79                       sta_dcm                                                 :  1,
80                       stream_offset                                           :  3,
81                       nss                                                     :  3,
82                       reserved_2a                                             :  7,
83                       dl_ofdma_content_channel                                :  1;
84              uint32_t reserved_3d                                             :  2,
85                       ru_start_index_80_3                                     :  6,
86                       reserved_3c                                             :  2,
87                       ru_start_index_80_2                                     :  6,
88                       reserved_3b                                             :  2,
89                       ru_start_index_80_1                                     :  6,
90                       reserved_3a                                             :  2,
91                       ru_start_index_80_0                                     :  6;
92              uint32_t user_fd_rssi_seg0                                       : 32;
93              uint32_t user_fd_rssi_seg1                                       : 32;
94              uint32_t user_fd_rssi_seg2                                       : 32;
95              uint32_t user_fd_rssi_seg3                                       : 32;
96 #endif
97 };
98 
99 #define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
100 #define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
101 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
102 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
103 
104 #define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
105 #define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
106 #define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
107 #define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
108 
109 #define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
110 #define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
111 #define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
112 #define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
113 
114 #define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
115 #define RECEIVE_USER_INFO_STBC_LSB                                                  28
116 #define RECEIVE_USER_INFO_STBC_MSB                                                  28
117 #define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
118 
119 #define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
120 #define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
121 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
122 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
123 
124 #define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
125 #define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
126 #define RECEIVE_USER_INFO_RATE_MCS_MSB                                              3
127 #define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000000f
128 
129 #define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
130 #define RECEIVE_USER_INFO_SGI_LSB                                                   4
131 #define RECEIVE_USER_INFO_SGI_MSB                                                   5
132 #define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000030
133 
134 #define RECEIVE_USER_INFO_RESERVED_1A_OFFSET                                        0x00000004
135 #define RECEIVE_USER_INFO_RESERVED_1A_LSB                                           7
136 #define RECEIVE_USER_INFO_RESERVED_1A_MSB                                           7
137 #define RECEIVE_USER_INFO_RESERVED_1A_MASK                                          0x00000080
138 
139 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
140 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
141 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
142 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
143 
144 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
145 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
146 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
147 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
148 
149 #define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
150 #define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
151 #define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
152 #define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
153 
154 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
155 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
156 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
157 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
158 
159 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
160 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
161 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
162 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
163 
164 #define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
165 #define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
166 #define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           7
167 #define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x000000fe
168 
169 #define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
170 #define RECEIVE_USER_INFO_NSS_LSB                                                   8
171 #define RECEIVE_USER_INFO_NSS_MSB                                                   10
172 #define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
173 
174 #define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
175 #define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
176 #define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
177 #define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
178 
179 #define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
180 #define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
181 #define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
182 #define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
183 
184 #define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
185 #define RECEIVE_USER_INFO_LDPC_LSB                                                  15
186 #define RECEIVE_USER_INFO_LDPC_MSB                                                  15
187 #define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
188 
189 #define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
190 #define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
191 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
192 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
193 
194 #define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
195 #define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
196 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
197 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
198 
199 #define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
200 #define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
201 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
202 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
203 
204 #define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
205 #define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
206 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
207 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
208 
209 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
210 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
211 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
212 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
213 
214 #define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
215 #define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
216 #define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
217 #define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
218 
219 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
220 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
221 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
222 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
223 
224 #define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
225 #define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
226 #define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
227 #define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
228 
229 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
230 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
231 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
232 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
233 
234 #define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
235 #define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
236 #define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
237 #define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
238 
239 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
240 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
241 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
242 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
243 
244 #define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
245 #define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
246 #define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
247 #define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
248 
249 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
250 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
251 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
252 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
253 
254 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
255 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
256 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
257 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
258 
259 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
260 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
261 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
262 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
263 
264 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
265 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
266 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
267 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
268 
269 #endif
270