1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _REO_FLUSH_QUEUE_H_ 19 #define _REO_FLUSH_QUEUE_H_ 20 21 #include "uniform_reo_cmd_header.h" 22 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 23 24 struct reo_flush_queue { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct uniform_reo_cmd_header cmd_header; 27 uint32_t flush_desc_addr_31_0 : 32; 28 uint32_t flush_desc_addr_39_32 : 8, 29 block_desc_addr_usage_after_flush : 1, 30 block_resource_index : 2, 31 reserved_2a : 21; 32 uint32_t reserved_3a : 32; 33 uint32_t reserved_4a : 32; 34 uint32_t reserved_5a : 32; 35 uint32_t reserved_6a : 32; 36 uint32_t reserved_7a : 32; 37 uint32_t reserved_8a : 32; 38 #else 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t flush_desc_addr_31_0 : 32; 41 uint32_t reserved_2a : 21, 42 block_resource_index : 2, 43 block_desc_addr_usage_after_flush : 1, 44 flush_desc_addr_39_32 : 8; 45 uint32_t reserved_3a : 32; 46 uint32_t reserved_4a : 32; 47 uint32_t reserved_5a : 32; 48 uint32_t reserved_6a : 32; 49 uint32_t reserved_7a : 32; 50 uint32_t reserved_8a : 32; 51 #endif 52 }; 53 54 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 55 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 56 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 57 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 58 59 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 60 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 61 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 62 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 63 64 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 65 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 66 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 67 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 68 69 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 70 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0 71 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31 72 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 73 74 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 75 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 76 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 77 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 78 79 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 80 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 81 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 82 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 83 84 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 85 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 86 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 87 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600 88 89 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008 90 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 91 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 92 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800 93 94 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c 95 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0 96 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31 97 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff 98 99 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010 100 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 101 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 102 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff 103 104 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014 105 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0 106 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31 107 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff 108 109 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018 110 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 111 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 112 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff 113 114 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c 115 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0 116 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31 117 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff 118 119 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020 120 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 121 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 122 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff 123 124 #endif 125