1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_MSDU_DETAILS_H_ 19 #define _RX_MSDU_DETAILS_H_ 20 21 #include "rx_msdu_desc_info.h" 22 #include "rx_msdu_ext_desc_info.h" 23 #include "buffer_addr_info.h" 24 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 25 26 struct rx_msdu_details { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct buffer_addr_info buffer_addr_info_details; 29 struct rx_msdu_desc_info rx_msdu_desc_info_details; 30 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 31 #else 32 struct buffer_addr_info buffer_addr_info_details; 33 struct rx_msdu_desc_info rx_msdu_desc_info_details; 34 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 35 #endif 36 }; 37 38 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 39 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 40 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 41 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 42 43 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 44 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 45 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 46 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 47 48 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 49 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 50 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 51 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 52 53 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 54 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 55 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 56 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 57 58 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 59 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 60 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 61 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 62 63 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 64 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 65 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 66 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 67 68 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 69 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 70 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 71 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 72 73 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 74 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 75 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 76 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 77 78 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 79 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 80 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 81 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 82 83 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 84 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 85 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 86 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 87 88 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 89 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 90 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 91 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 92 93 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 94 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 95 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 96 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 97 98 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 99 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 100 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 101 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 102 103 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 104 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 105 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 106 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 107 108 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 109 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 110 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 111 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 112 113 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 114 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 115 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 116 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 117 118 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 119 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 120 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 121 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 122 123 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 124 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 125 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 126 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 127 128 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 129 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 130 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 131 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 132 133 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 134 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 135 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 136 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 137 138 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 139 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 140 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 141 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 142 143 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c 144 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 145 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 146 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 147 148 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c 149 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 150 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 151 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 152 153 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c 154 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 155 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 156 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 157 158 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c 159 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 160 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 161 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 162 163 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c 164 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 165 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 166 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 167 168 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c 169 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 170 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 171 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 172 173 #endif 174