1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_MSDU_END_H_ 19 #define _RX_MSDU_END_H_ 20 21 #define NUM_OF_DWORDS_RX_MSDU_END 32 22 23 struct rx_msdu_end { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t rxpcu_mpdu_filter_in_category : 2, 26 sw_frame_group_id : 7, 27 reserved_0 : 7, 28 phy_ppdu_id : 16; 29 uint32_t ip_hdr_chksum : 16, 30 reported_mpdu_length : 14, 31 reserved_1a : 2; 32 uint32_t reserved_2a : 8, 33 cce_super_rule : 6, 34 cce_classify_not_done_truncate : 1, 35 cce_classify_not_done_cce_dis : 1, 36 cumulative_l3_checksum : 16; 37 uint32_t rule_indication_31_0 : 32; 38 uint32_t ipv6_options_crc : 32; 39 uint32_t da_offset : 6, 40 sa_offset : 6, 41 da_offset_valid : 1, 42 sa_offset_valid : 1, 43 reserved_5a : 2, 44 l3_type : 16; 45 uint32_t rule_indication_63_32 : 32; 46 uint32_t tcp_seq_number : 32; 47 uint32_t tcp_ack_number : 32; 48 uint32_t tcp_flag : 9, 49 lro_eligible : 1, 50 reserved_9a : 6, 51 window_size : 16; 52 uint32_t sa_sw_peer_id : 16, 53 sa_idx_timeout : 1, 54 da_idx_timeout : 1, 55 to_ds : 1, 56 tid : 4, 57 sa_is_valid : 1, 58 da_is_valid : 1, 59 da_is_mcbc : 1, 60 l3_header_padding : 2, 61 first_msdu : 1, 62 last_msdu : 1, 63 fr_ds : 1, 64 ip_chksum_fail_copy : 1; 65 uint32_t sa_idx : 16, 66 da_idx_or_sw_peer_id : 16; 67 uint32_t msdu_drop : 1, 68 reo_destination_indication : 5, 69 flow_idx : 20, 70 use_ppe : 1, 71 __reserved_g_0003 : 2, 72 vlan_ctag_stripped : 1, 73 vlan_stag_stripped : 1, 74 fragment_flag : 1; 75 uint32_t fse_metadata : 32; 76 uint32_t cce_metadata : 16, 77 tcp_udp_chksum : 16; 78 uint32_t aggregation_count : 8, 79 flow_aggregation_continuation : 1, 80 fisa_timeout : 1, 81 tcp_udp_chksum_fail_copy : 1, 82 msdu_limit_error : 1, 83 flow_idx_timeout : 1, 84 flow_idx_invalid : 1, 85 cce_match : 1, 86 amsdu_parser_error : 1, 87 cumulative_ip_length : 16; 88 uint32_t key_id_octet : 8, 89 reserved_16a : 24; 90 uint32_t reserved_17a : 6, 91 service_code : 9, 92 priority_valid : 1, 93 intra_bss : 1, 94 dest_chip_id : 2, 95 multicast_echo : 1, 96 wds_learning_event : 1, 97 wds_roaming_event : 1, 98 wds_keep_alive_event : 1, 99 __reserved_g_0015 : 1, 100 reserved_17b : 8; 101 uint32_t msdu_length : 14, 102 stbc : 1, 103 ipsec_esp : 1, 104 l3_offset : 7, 105 ipsec_ah : 1, 106 l4_offset : 8; 107 uint32_t msdu_number : 8, 108 decap_format : 2, 109 ipv4_proto : 1, 110 ipv6_proto : 1, 111 tcp_proto : 1, 112 udp_proto : 1, 113 ip_frag : 1, 114 tcp_only_ack : 1, 115 da_is_bcast_mcast : 1, 116 toeplitz_hash_sel : 2, 117 ip_fixed_header_valid : 1, 118 ip_extn_header_valid : 1, 119 tcp_udp_header_valid : 1, 120 mesh_control_present : 1, 121 ldpc : 1, 122 ip4_protocol_ip6_next_header : 8; 123 uint32_t vlan_ctag_ci : 16, 124 vlan_stag_ci : 16; 125 uint32_t peer_meta_data : 32; 126 uint32_t user_rssi : 8, 127 pkt_type : 4, 128 sgi : 2, 129 rate_mcs : 4, 130 receive_bandwidth : 3, 131 reception_type : 3, 132 mimo_ss_bitmap : 7, 133 msdu_done_copy : 1; 134 uint32_t flow_id_toeplitz : 32; 135 uint32_t ppdu_start_timestamp_63_32 : 32; 136 uint32_t sw_phy_meta_data : 32; 137 uint32_t ppdu_start_timestamp_31_0 : 32; 138 uint32_t toeplitz_hash_2_or_4 : 32; 139 uint32_t reserved_28a : 16, 140 sa_15_0 : 16; 141 uint32_t sa_47_16 : 32; 142 uint32_t first_mpdu : 1, 143 reserved_30a : 1, 144 mcast_bcast : 1, 145 ast_index_not_found : 1, 146 ast_index_timeout : 1, 147 power_mgmt : 1, 148 non_qos : 1, 149 null_data : 1, 150 mgmt_type : 1, 151 ctrl_type : 1, 152 more_data : 1, 153 eosp : 1, 154 a_msdu_error : 1, 155 reserved_30b : 1, 156 order : 1, 157 wifi_parser_error : 1, 158 overflow_err : 1, 159 msdu_length_err : 1, 160 tcp_udp_chksum_fail : 1, 161 ip_chksum_fail : 1, 162 sa_idx_invalid : 1, 163 da_idx_invalid : 1, 164 amsdu_addr_mismatch : 1, 165 rx_in_tx_decrypt_byp : 1, 166 encrypt_required : 1, 167 directed : 1, 168 buffer_fragment : 1, 169 mpdu_length_err : 1, 170 tkip_mic_err : 1, 171 decrypt_err : 1, 172 unencrypted_frame_err : 1, 173 fcs_err : 1; 174 uint32_t reserved_31a : 10, 175 decrypt_status_code : 3, 176 rx_bitmap_not_updated : 1, 177 reserved_31b : 17, 178 msdu_done : 1; 179 #else 180 uint32_t phy_ppdu_id : 16, 181 reserved_0 : 7, 182 sw_frame_group_id : 7, 183 rxpcu_mpdu_filter_in_category : 2; 184 uint32_t reserved_1a : 2, 185 reported_mpdu_length : 14, 186 ip_hdr_chksum : 16; 187 uint32_t cumulative_l3_checksum : 16, 188 cce_classify_not_done_cce_dis : 1, 189 cce_classify_not_done_truncate : 1, 190 cce_super_rule : 6, 191 reserved_2a : 8; 192 uint32_t rule_indication_31_0 : 32; 193 uint32_t ipv6_options_crc : 32; 194 uint32_t l3_type : 16, 195 reserved_5a : 2, 196 sa_offset_valid : 1, 197 da_offset_valid : 1, 198 sa_offset : 6, 199 da_offset : 6; 200 uint32_t rule_indication_63_32 : 32; 201 uint32_t tcp_seq_number : 32; 202 uint32_t tcp_ack_number : 32; 203 uint32_t window_size : 16, 204 reserved_9a : 6, 205 lro_eligible : 1, 206 tcp_flag : 9; 207 uint32_t ip_chksum_fail_copy : 1, 208 fr_ds : 1, 209 last_msdu : 1, 210 first_msdu : 1, 211 l3_header_padding : 2, 212 da_is_mcbc : 1, 213 da_is_valid : 1, 214 sa_is_valid : 1, 215 tid : 4, 216 to_ds : 1, 217 da_idx_timeout : 1, 218 sa_idx_timeout : 1, 219 sa_sw_peer_id : 16; 220 uint32_t da_idx_or_sw_peer_id : 16, 221 sa_idx : 16; 222 uint32_t fragment_flag : 1, 223 vlan_stag_stripped : 1, 224 vlan_ctag_stripped : 1, 225 __reserved_g_0003 : 2, 226 use_ppe : 1, 227 flow_idx : 20, 228 reo_destination_indication : 5, 229 msdu_drop : 1; 230 uint32_t fse_metadata : 32; 231 uint32_t tcp_udp_chksum : 16, 232 cce_metadata : 16; 233 uint32_t cumulative_ip_length : 16, 234 amsdu_parser_error : 1, 235 cce_match : 1, 236 flow_idx_invalid : 1, 237 flow_idx_timeout : 1, 238 msdu_limit_error : 1, 239 tcp_udp_chksum_fail_copy : 1, 240 fisa_timeout : 1, 241 flow_aggregation_continuation : 1, 242 aggregation_count : 8; 243 uint32_t reserved_16a : 24, 244 key_id_octet : 8; 245 uint32_t reserved_17b : 8, 246 __reserved_g_0015 : 1, 247 wds_keep_alive_event : 1, 248 wds_roaming_event : 1, 249 wds_learning_event : 1, 250 multicast_echo : 1, 251 dest_chip_id : 2, 252 intra_bss : 1, 253 priority_valid : 1, 254 service_code : 9, 255 reserved_17a : 6; 256 uint32_t l4_offset : 8, 257 ipsec_ah : 1, 258 l3_offset : 7, 259 ipsec_esp : 1, 260 stbc : 1, 261 msdu_length : 14; 262 uint32_t ip4_protocol_ip6_next_header : 8, 263 ldpc : 1, 264 mesh_control_present : 1, 265 tcp_udp_header_valid : 1, 266 ip_extn_header_valid : 1, 267 ip_fixed_header_valid : 1, 268 toeplitz_hash_sel : 2, 269 da_is_bcast_mcast : 1, 270 tcp_only_ack : 1, 271 ip_frag : 1, 272 udp_proto : 1, 273 tcp_proto : 1, 274 ipv6_proto : 1, 275 ipv4_proto : 1, 276 decap_format : 2, 277 msdu_number : 8; 278 uint32_t vlan_stag_ci : 16, 279 vlan_ctag_ci : 16; 280 uint32_t peer_meta_data : 32; 281 uint32_t msdu_done_copy : 1, 282 mimo_ss_bitmap : 7, 283 reception_type : 3, 284 receive_bandwidth : 3, 285 rate_mcs : 4, 286 sgi : 2, 287 pkt_type : 4, 288 user_rssi : 8; 289 uint32_t flow_id_toeplitz : 32; 290 uint32_t ppdu_start_timestamp_63_32 : 32; 291 uint32_t sw_phy_meta_data : 32; 292 uint32_t ppdu_start_timestamp_31_0 : 32; 293 uint32_t toeplitz_hash_2_or_4 : 32; 294 uint32_t sa_15_0 : 16, 295 reserved_28a : 16; 296 uint32_t sa_47_16 : 32; 297 uint32_t fcs_err : 1, 298 unencrypted_frame_err : 1, 299 decrypt_err : 1, 300 tkip_mic_err : 1, 301 mpdu_length_err : 1, 302 buffer_fragment : 1, 303 directed : 1, 304 encrypt_required : 1, 305 rx_in_tx_decrypt_byp : 1, 306 amsdu_addr_mismatch : 1, 307 da_idx_invalid : 1, 308 sa_idx_invalid : 1, 309 ip_chksum_fail : 1, 310 tcp_udp_chksum_fail : 1, 311 msdu_length_err : 1, 312 overflow_err : 1, 313 wifi_parser_error : 1, 314 order : 1, 315 reserved_30b : 1, 316 a_msdu_error : 1, 317 eosp : 1, 318 more_data : 1, 319 ctrl_type : 1, 320 mgmt_type : 1, 321 null_data : 1, 322 non_qos : 1, 323 power_mgmt : 1, 324 ast_index_timeout : 1, 325 ast_index_not_found : 1, 326 mcast_bcast : 1, 327 reserved_30a : 1, 328 first_mpdu : 1; 329 uint32_t msdu_done : 1, 330 reserved_31b : 17, 331 rx_bitmap_not_updated : 1, 332 decrypt_status_code : 3, 333 reserved_31a : 10; 334 #endif 335 }; 336 337 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 338 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 339 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 340 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 341 342 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 343 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 344 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 345 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc 346 347 #define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000 348 #define RX_MSDU_END_RESERVED_0_LSB 9 349 #define RX_MSDU_END_RESERVED_0_MSB 15 350 #define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00 351 352 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000 353 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 354 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 355 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000 356 357 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004 358 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0 359 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15 360 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff 361 362 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 363 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16 364 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29 365 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 366 367 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004 368 #define RX_MSDU_END_RESERVED_1A_LSB 30 369 #define RX_MSDU_END_RESERVED_1A_MSB 31 370 #define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000 371 372 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008 373 #define RX_MSDU_END_RESERVED_2A_LSB 0 374 #define RX_MSDU_END_RESERVED_2A_MSB 7 375 #define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff 376 377 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008 378 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 379 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 380 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00 381 382 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 383 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 384 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 385 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 386 387 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 388 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 389 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 390 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 391 392 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 393 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 394 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 395 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 396 397 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c 398 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0 399 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31 400 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff 401 402 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010 403 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 404 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 405 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff 406 407 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014 408 #define RX_MSDU_END_DA_OFFSET_LSB 0 409 #define RX_MSDU_END_DA_OFFSET_MSB 5 410 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f 411 412 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014 413 #define RX_MSDU_END_SA_OFFSET_LSB 6 414 #define RX_MSDU_END_SA_OFFSET_MSB 11 415 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0 416 417 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014 418 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 12 419 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 12 420 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000 421 422 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014 423 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 13 424 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 13 425 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000 426 427 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014 428 #define RX_MSDU_END_RESERVED_5A_LSB 14 429 #define RX_MSDU_END_RESERVED_5A_MSB 15 430 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000 431 432 #define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014 433 #define RX_MSDU_END_L3_TYPE_LSB 16 434 #define RX_MSDU_END_L3_TYPE_MSB 31 435 #define RX_MSDU_END_L3_TYPE_MASK 0xffff0000 436 437 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018 438 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 439 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 440 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff 441 442 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c 443 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0 444 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31 445 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff 446 447 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020 448 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 449 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 450 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff 451 452 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024 453 #define RX_MSDU_END_TCP_FLAG_LSB 0 454 #define RX_MSDU_END_TCP_FLAG_MSB 8 455 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff 456 457 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024 458 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 9 459 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 9 460 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200 461 462 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024 463 #define RX_MSDU_END_RESERVED_9A_LSB 10 464 #define RX_MSDU_END_RESERVED_9A_MSB 15 465 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00 466 467 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024 468 #define RX_MSDU_END_WINDOW_SIZE_LSB 16 469 #define RX_MSDU_END_WINDOW_SIZE_MSB 31 470 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000 471 472 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028 473 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 474 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 475 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff 476 477 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028 478 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 479 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 480 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000 481 482 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028 483 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 484 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 485 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000 486 487 #define RX_MSDU_END_TO_DS_OFFSET 0x00000028 488 #define RX_MSDU_END_TO_DS_LSB 18 489 #define RX_MSDU_END_TO_DS_MSB 18 490 #define RX_MSDU_END_TO_DS_MASK 0x00040000 491 492 #define RX_MSDU_END_TID_OFFSET 0x00000028 493 #define RX_MSDU_END_TID_LSB 19 494 #define RX_MSDU_END_TID_MSB 22 495 #define RX_MSDU_END_TID_MASK 0x00780000 496 497 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028 498 #define RX_MSDU_END_SA_IS_VALID_LSB 23 499 #define RX_MSDU_END_SA_IS_VALID_MSB 23 500 #define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000 501 502 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028 503 #define RX_MSDU_END_DA_IS_VALID_LSB 24 504 #define RX_MSDU_END_DA_IS_VALID_MSB 24 505 #define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000 506 507 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028 508 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 509 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 510 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000 511 512 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028 513 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 514 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 515 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000 516 517 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028 518 #define RX_MSDU_END_FIRST_MSDU_LSB 28 519 #define RX_MSDU_END_FIRST_MSDU_MSB 28 520 #define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000 521 522 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028 523 #define RX_MSDU_END_LAST_MSDU_LSB 29 524 #define RX_MSDU_END_LAST_MSDU_MSB 29 525 #define RX_MSDU_END_LAST_MSDU_MASK 0x20000000 526 527 #define RX_MSDU_END_FR_DS_OFFSET 0x00000028 528 #define RX_MSDU_END_FR_DS_LSB 30 529 #define RX_MSDU_END_FR_DS_MSB 30 530 #define RX_MSDU_END_FR_DS_MASK 0x40000000 531 532 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028 533 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 534 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 535 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000 536 537 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c 538 #define RX_MSDU_END_SA_IDX_LSB 0 539 #define RX_MSDU_END_SA_IDX_MSB 15 540 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff 541 542 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 543 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16 544 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31 545 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 546 547 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030 548 #define RX_MSDU_END_MSDU_DROP_LSB 0 549 #define RX_MSDU_END_MSDU_DROP_MSB 0 550 #define RX_MSDU_END_MSDU_DROP_MASK 0x00000001 551 552 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030 553 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 554 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 555 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e 556 557 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030 558 #define RX_MSDU_END_FLOW_IDX_LSB 6 559 #define RX_MSDU_END_FLOW_IDX_MSB 25 560 #define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0 561 562 #define RX_MSDU_END_USE_PPE_OFFSET 0x00000030 563 #define RX_MSDU_END_USE_PPE_LSB 26 564 #define RX_MSDU_END_USE_PPE_MSB 26 565 #define RX_MSDU_END_USE_PPE_MASK 0x04000000 566 567 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030 568 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 569 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 570 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000 571 572 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030 573 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 574 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 575 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000 576 577 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030 578 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 579 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 580 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000 581 582 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034 583 #define RX_MSDU_END_FSE_METADATA_LSB 0 584 #define RX_MSDU_END_FSE_METADATA_MSB 31 585 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff 586 587 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038 588 #define RX_MSDU_END_CCE_METADATA_LSB 0 589 #define RX_MSDU_END_CCE_METADATA_MSB 15 590 #define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff 591 592 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038 593 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 594 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 595 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000 596 597 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c 598 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 0 599 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 7 600 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff 601 602 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c 603 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8 604 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8 605 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 606 607 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c 608 #define RX_MSDU_END_FISA_TIMEOUT_LSB 9 609 #define RX_MSDU_END_FISA_TIMEOUT_MSB 9 610 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200 611 612 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c 613 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10 614 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10 615 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400 616 617 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c 618 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11 619 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11 620 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800 621 622 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c 623 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12 624 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12 625 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000 626 627 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c 628 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13 629 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13 630 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000 631 632 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c 633 #define RX_MSDU_END_CCE_MATCH_LSB 14 634 #define RX_MSDU_END_CCE_MATCH_MSB 14 635 #define RX_MSDU_END_CCE_MATCH_MASK 0x00004000 636 637 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c 638 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15 639 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15 640 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000 641 642 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c 643 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16 644 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31 645 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 646 647 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040 648 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 649 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 650 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff 651 652 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040 653 #define RX_MSDU_END_RESERVED_16A_LSB 8 654 #define RX_MSDU_END_RESERVED_16A_MSB 31 655 #define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00 656 657 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044 658 #define RX_MSDU_END_RESERVED_17A_LSB 0 659 #define RX_MSDU_END_RESERVED_17A_MSB 5 660 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f 661 662 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044 663 #define RX_MSDU_END_SERVICE_CODE_LSB 6 664 #define RX_MSDU_END_SERVICE_CODE_MSB 14 665 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0 666 667 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044 668 #define RX_MSDU_END_PRIORITY_VALID_LSB 15 669 #define RX_MSDU_END_PRIORITY_VALID_MSB 15 670 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000 671 672 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044 673 #define RX_MSDU_END_INTRA_BSS_LSB 16 674 #define RX_MSDU_END_INTRA_BSS_MSB 16 675 #define RX_MSDU_END_INTRA_BSS_MASK 0x00010000 676 677 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044 678 #define RX_MSDU_END_DEST_CHIP_ID_LSB 17 679 #define RX_MSDU_END_DEST_CHIP_ID_MSB 18 680 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000 681 682 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044 683 #define RX_MSDU_END_MULTICAST_ECHO_LSB 19 684 #define RX_MSDU_END_MULTICAST_ECHO_MSB 19 685 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000 686 687 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044 688 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20 689 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20 690 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000 691 692 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044 693 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21 694 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21 695 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000 696 697 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044 698 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22 699 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22 700 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000 701 702 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044 703 #define RX_MSDU_END_RESERVED_17B_LSB 24 704 #define RX_MSDU_END_RESERVED_17B_MSB 31 705 #define RX_MSDU_END_RESERVED_17B_MASK 0xff000000 706 707 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048 708 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 709 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 710 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff 711 712 #define RX_MSDU_END_STBC_OFFSET 0x00000048 713 #define RX_MSDU_END_STBC_LSB 14 714 #define RX_MSDU_END_STBC_MSB 14 715 #define RX_MSDU_END_STBC_MASK 0x00004000 716 717 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048 718 #define RX_MSDU_END_IPSEC_ESP_LSB 15 719 #define RX_MSDU_END_IPSEC_ESP_MSB 15 720 #define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000 721 722 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048 723 #define RX_MSDU_END_L3_OFFSET_LSB 16 724 #define RX_MSDU_END_L3_OFFSET_MSB 22 725 #define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000 726 727 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048 728 #define RX_MSDU_END_IPSEC_AH_LSB 23 729 #define RX_MSDU_END_IPSEC_AH_MSB 23 730 #define RX_MSDU_END_IPSEC_AH_MASK 0x00800000 731 732 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048 733 #define RX_MSDU_END_L4_OFFSET_LSB 24 734 #define RX_MSDU_END_L4_OFFSET_MSB 31 735 #define RX_MSDU_END_L4_OFFSET_MASK 0xff000000 736 737 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c 738 #define RX_MSDU_END_MSDU_NUMBER_LSB 0 739 #define RX_MSDU_END_MSDU_NUMBER_MSB 7 740 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff 741 742 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c 743 #define RX_MSDU_END_DECAP_FORMAT_LSB 8 744 #define RX_MSDU_END_DECAP_FORMAT_MSB 9 745 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300 746 747 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c 748 #define RX_MSDU_END_IPV4_PROTO_LSB 10 749 #define RX_MSDU_END_IPV4_PROTO_MSB 10 750 #define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400 751 752 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c 753 #define RX_MSDU_END_IPV6_PROTO_LSB 11 754 #define RX_MSDU_END_IPV6_PROTO_MSB 11 755 #define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800 756 757 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c 758 #define RX_MSDU_END_TCP_PROTO_LSB 12 759 #define RX_MSDU_END_TCP_PROTO_MSB 12 760 #define RX_MSDU_END_TCP_PROTO_MASK 0x00001000 761 762 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c 763 #define RX_MSDU_END_UDP_PROTO_LSB 13 764 #define RX_MSDU_END_UDP_PROTO_MSB 13 765 #define RX_MSDU_END_UDP_PROTO_MASK 0x00002000 766 767 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c 768 #define RX_MSDU_END_IP_FRAG_LSB 14 769 #define RX_MSDU_END_IP_FRAG_MSB 14 770 #define RX_MSDU_END_IP_FRAG_MASK 0x00004000 771 772 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c 773 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 15 774 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 15 775 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000 776 777 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c 778 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16 779 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16 780 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000 781 782 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c 783 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17 784 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18 785 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000 786 787 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c 788 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19 789 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19 790 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000 791 792 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c 793 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20 794 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20 795 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000 796 797 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c 798 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21 799 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21 800 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000 801 802 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c 803 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22 804 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22 805 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000 806 807 #define RX_MSDU_END_LDPC_OFFSET 0x0000004c 808 #define RX_MSDU_END_LDPC_LSB 23 809 #define RX_MSDU_END_LDPC_MSB 23 810 #define RX_MSDU_END_LDPC_MASK 0x00800000 811 812 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c 813 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 814 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 815 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 816 817 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050 818 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 819 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 820 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff 821 822 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050 823 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 824 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 825 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000 826 827 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054 828 #define RX_MSDU_END_PEER_META_DATA_LSB 0 829 #define RX_MSDU_END_PEER_META_DATA_MSB 31 830 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff 831 832 #define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058 833 #define RX_MSDU_END_USER_RSSI_LSB 0 834 #define RX_MSDU_END_USER_RSSI_MSB 7 835 #define RX_MSDU_END_USER_RSSI_MASK 0x000000ff 836 837 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058 838 #define RX_MSDU_END_PKT_TYPE_LSB 8 839 #define RX_MSDU_END_PKT_TYPE_MSB 11 840 #define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00 841 842 #define RX_MSDU_END_SGI_OFFSET 0x00000058 843 #define RX_MSDU_END_SGI_LSB 12 844 #define RX_MSDU_END_SGI_MSB 13 845 #define RX_MSDU_END_SGI_MASK 0x00003000 846 847 #define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058 848 #define RX_MSDU_END_RATE_MCS_LSB 14 849 #define RX_MSDU_END_RATE_MCS_MSB 17 850 #define RX_MSDU_END_RATE_MCS_MASK 0x0003c000 851 852 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058 853 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 854 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 855 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000 856 857 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058 858 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 859 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 860 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000 861 862 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058 863 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 864 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 865 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000 866 867 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058 868 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 869 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 870 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000 871 872 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c 873 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0 874 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31 875 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff 876 877 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060 878 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 879 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 880 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff 881 882 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064 883 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 0 884 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 31 885 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff 886 887 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068 888 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 889 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 890 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff 891 892 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c 893 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0 894 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31 895 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff 896 897 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070 898 #define RX_MSDU_END_RESERVED_28A_LSB 0 899 #define RX_MSDU_END_RESERVED_28A_MSB 15 900 #define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff 901 902 #define RX_MSDU_END_SA_15_0_OFFSET 0x00000070 903 #define RX_MSDU_END_SA_15_0_LSB 16 904 #define RX_MSDU_END_SA_15_0_MSB 31 905 #define RX_MSDU_END_SA_15_0_MASK 0xffff0000 906 907 #define RX_MSDU_END_SA_47_16_OFFSET 0x00000074 908 #define RX_MSDU_END_SA_47_16_LSB 0 909 #define RX_MSDU_END_SA_47_16_MSB 31 910 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff 911 912 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078 913 #define RX_MSDU_END_FIRST_MPDU_LSB 0 914 #define RX_MSDU_END_FIRST_MPDU_MSB 0 915 #define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001 916 917 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078 918 #define RX_MSDU_END_RESERVED_30A_LSB 1 919 #define RX_MSDU_END_RESERVED_30A_MSB 1 920 #define RX_MSDU_END_RESERVED_30A_MASK 0x00000002 921 922 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078 923 #define RX_MSDU_END_MCAST_BCAST_LSB 2 924 #define RX_MSDU_END_MCAST_BCAST_MSB 2 925 #define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004 926 927 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078 928 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 929 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 930 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008 931 932 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078 933 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 934 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 935 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010 936 937 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078 938 #define RX_MSDU_END_POWER_MGMT_LSB 5 939 #define RX_MSDU_END_POWER_MGMT_MSB 5 940 #define RX_MSDU_END_POWER_MGMT_MASK 0x00000020 941 942 #define RX_MSDU_END_NON_QOS_OFFSET 0x00000078 943 #define RX_MSDU_END_NON_QOS_LSB 6 944 #define RX_MSDU_END_NON_QOS_MSB 6 945 #define RX_MSDU_END_NON_QOS_MASK 0x00000040 946 947 #define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078 948 #define RX_MSDU_END_NULL_DATA_LSB 7 949 #define RX_MSDU_END_NULL_DATA_MSB 7 950 #define RX_MSDU_END_NULL_DATA_MASK 0x00000080 951 952 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078 953 #define RX_MSDU_END_MGMT_TYPE_LSB 8 954 #define RX_MSDU_END_MGMT_TYPE_MSB 8 955 #define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100 956 957 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078 958 #define RX_MSDU_END_CTRL_TYPE_LSB 9 959 #define RX_MSDU_END_CTRL_TYPE_MSB 9 960 #define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200 961 962 #define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078 963 #define RX_MSDU_END_MORE_DATA_LSB 10 964 #define RX_MSDU_END_MORE_DATA_MSB 10 965 #define RX_MSDU_END_MORE_DATA_MASK 0x00000400 966 967 #define RX_MSDU_END_EOSP_OFFSET 0x00000078 968 #define RX_MSDU_END_EOSP_LSB 11 969 #define RX_MSDU_END_EOSP_MSB 11 970 #define RX_MSDU_END_EOSP_MASK 0x00000800 971 972 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078 973 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 974 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 975 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000 976 977 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078 978 #define RX_MSDU_END_RESERVED_30B_LSB 13 979 #define RX_MSDU_END_RESERVED_30B_MSB 13 980 #define RX_MSDU_END_RESERVED_30B_MASK 0x00002000 981 982 #define RX_MSDU_END_ORDER_OFFSET 0x00000078 983 #define RX_MSDU_END_ORDER_LSB 14 984 #define RX_MSDU_END_ORDER_MSB 14 985 #define RX_MSDU_END_ORDER_MASK 0x00004000 986 987 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078 988 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 989 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 990 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000 991 992 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078 993 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 994 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 995 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000 996 997 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078 998 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 999 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 1000 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000 1001 1002 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 1003 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 1004 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 1005 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 1006 1007 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078 1008 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 1009 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 1010 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000 1011 1012 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078 1013 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 1014 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 1015 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000 1016 1017 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078 1018 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 1019 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 1020 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000 1021 1022 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078 1023 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 1024 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 1025 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000 1026 1027 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078 1028 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 1029 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 1030 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 1031 1032 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078 1033 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 1034 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 1035 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000 1036 1037 #define RX_MSDU_END_DIRECTED_OFFSET 0x00000078 1038 #define RX_MSDU_END_DIRECTED_LSB 25 1039 #define RX_MSDU_END_DIRECTED_MSB 25 1040 #define RX_MSDU_END_DIRECTED_MASK 0x02000000 1041 1042 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078 1043 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 1044 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 1045 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000 1046 1047 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078 1048 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 1049 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 1050 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000 1051 1052 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078 1053 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 1054 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 1055 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000 1056 1057 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078 1058 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 1059 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 1060 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000 1061 1062 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078 1063 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 1064 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 1065 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 1066 1067 #define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078 1068 #define RX_MSDU_END_FCS_ERR_LSB 31 1069 #define RX_MSDU_END_FCS_ERR_MSB 31 1070 #define RX_MSDU_END_FCS_ERR_MASK 0x80000000 1071 1072 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c 1073 #define RX_MSDU_END_RESERVED_31A_LSB 0 1074 #define RX_MSDU_END_RESERVED_31A_MSB 9 1075 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff 1076 1077 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c 1078 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10 1079 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12 1080 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00 1081 1082 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c 1083 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13 1084 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13 1085 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 1086 1087 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c 1088 #define RX_MSDU_END_RESERVED_31B_LSB 14 1089 #define RX_MSDU_END_RESERVED_31B_MSB 30 1090 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000 1091 1092 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c 1093 #define RX_MSDU_END_MSDU_DONE_LSB 31 1094 #define RX_MSDU_END_MSDU_DONE_MSB 31 1095 #define RX_MSDU_END_MSDU_DONE_MASK 0x80000000 1096 1097 #endif 1098