xref: /wlan-driver/fw-api/hw/peach/v2/rx_timing_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _RX_TIMING_INFO_H_
19 #define _RX_TIMING_INFO_H_
20 
21 #define NUM_OF_DWORDS_RX_TIMING_INFO 5
22 
23 struct rx_timing_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t phy_timestamp_1_lower_32                                : 32;
26              uint32_t phy_timestamp_1_upper_32                                : 32;
27              uint32_t phy_timestamp_2_lower_32                                : 32;
28              uint32_t phy_timestamp_2_upper_32                                : 32;
29              uint32_t residual_phase_offset                                   : 12,
30                       reserved                                                : 20;
31 #else
32              uint32_t phy_timestamp_1_lower_32                                : 32;
33              uint32_t phy_timestamp_1_upper_32                                : 32;
34              uint32_t phy_timestamp_2_lower_32                                : 32;
35              uint32_t phy_timestamp_2_upper_32                                : 32;
36              uint32_t reserved                                                : 20,
37                       residual_phase_offset                                   : 12;
38 #endif
39 };
40 
41 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET                              0x00000000
42 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB                                 0
43 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB                                 31
44 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK                                0xffffffff
45 
46 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET                              0x00000004
47 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB                                 0
48 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB                                 31
49 #define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK                                0xffffffff
50 
51 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET                              0x00000008
52 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB                                 0
53 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB                                 31
54 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK                                0xffffffff
55 
56 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET                              0x0000000c
57 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB                                 0
58 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB                                 31
59 #define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK                                0xffffffff
60 
61 #define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                                 0x00000010
62 #define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB                                    0
63 #define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB                                    11
64 #define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK                                   0x00000fff
65 
66 #define RX_TIMING_INFO_RESERVED_OFFSET                                              0x00000010
67 #define RX_TIMING_INFO_RESERVED_LSB                                                 12
68 #define RX_TIMING_INFO_RESERVED_MSB                                                 31
69 #define RX_TIMING_INFO_RESERVED_MASK                                                0xfffff000
70 
71 #endif
72