xref: /wlan-driver/fw-api/hw/peach/v2/soc_ce_seq_hwioreg.h (revision 5113495b16420b49004c444715d2daae2066e7dc)

/*
 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
#ifndef __SOC_CE_SEQ_HWIOREG_H__
#define __SOC_CE_SEQ_HWIOREG_H__

#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00000000)
#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00000000)
#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00000000

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00001000)
#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00001000)
#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00001000

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00002000)
#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00002000)
#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00002000

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00003000)
#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00003000)
#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00003000

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00004000)
#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00004000)
#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00004000

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00005000)
#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00005000)
#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00005000

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00006000)
#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00006000)
#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00006000

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00007000)
#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00007000)
#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00007000

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00008000)
#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00008000)
#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00008000

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00009000)
#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00009000)
#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00009000

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x0000a000)
#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000a000)
#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x0000a000

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x0000b000)
#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000b000)
#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x0000b000

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x0000c000)
#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000c000)
#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x0000c000

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x0000d000)
#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000d000)
#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x0000d000

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x0000e000)
#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000e000)
#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x0000e000

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x0000f000)
#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000f000)
#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x0000f000

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00010000)
#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00010000)
#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00010000

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00011000)
#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00011000)
#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00011000

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00012000)
#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS                                                              (SOC_WFSS_CE_REG_BASE_PHYS + 0x00012000)
#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS                                                              0x00012000

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00013000)
#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS                                                                 (SOC_WFSS_CE_REG_BASE_PHYS + 0x00013000)
#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS                                                                 0x00013000

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE                                                                  (SOC_WFSS_CE_REG_BASE      + 0x00014000)
#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS                                                             (SOC_WFSS_CE_REG_BASE_PHYS + 0x00014000)
#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS                                                             0x00014000

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE                                                                     (SOC_WFSS_CE_REG_BASE      + 0x00015000)
#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS                                                                (SOC_WFSS_CE_REG_BASE_PHYS + 0x00015000)
#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS                                                                0x00015000

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE                                                                  (SOC_WFSS_CE_REG_BASE      + 0x00016000)
#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS                                                             (SOC_WFSS_CE_REG_BASE_PHYS + 0x00016000)
#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS                                                             0x00016000

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS                                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                                                               0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR                                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS                                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS                                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR                                                       (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS                                                       (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS                                                       (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK                                                         0x3fffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS                                                (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK                                     0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK           0xffff0000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                 0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                       0x8000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                          0xf
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                 0x7fff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                    0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK                                         0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                           0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                              0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                     0x8000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                        0xf
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS                                     (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK                                          0x3ff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                       0x3ff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                         0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR                                    (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS                                    (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS                                    (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK                                           0x7
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                      0x7
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                      0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS                                   (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK                                     0xffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                      0xff0000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                          0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                     0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                        0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR                                                  (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS                                                  (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS                                                  (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR                                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS                                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS                                                            (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                                                                  0x1f
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK                                                        0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                                                         0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK                                                     0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT                                                     0x3
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK                                                          0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                                                          0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK                                                       0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT                                                       0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK                                             0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT                                             0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR                                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS                                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS                                                        (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                                                              0x1f
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK                                                      0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT                                                       0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK                                              0x8
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT                                              0x3
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK                                                0x4
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT                                                0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK                                                    0x2
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT                                                    0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK                                                       0x1
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT                                                       0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                                                         0xffffffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK                                                  0xffff0000
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                                                        0x10
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK                                                       0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                                                          0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS                                                         (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN)
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE                                                                     (SOC_WFSS_CE_REG_BASE      + 0x00017000)
#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS                                                                (SOC_WFSS_CE_REG_BASE_PHYS + 0x00017000)
#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS                                                                0x00017000

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                                                                 0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK                                                      0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT                                                       0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK                                                       0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                       0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                             0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK                                           0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT                                              0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK                                                           0x3fffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK                                             0x3fc000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT                                                  0xe
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK                                              0x3000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT                                                 0xc
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK                                               0xf00
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT                                                 0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK                                                  0x80
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT                                                   0x7
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK                                                   0x40
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT                                                    0x6
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                             0x20
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                              0x5
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                              0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                               0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK                                                   0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT                                                   0x3
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK                                                   0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT                                                   0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK                                                0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT                                                0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK                                                0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT                                                0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                             0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                    0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK                                                        0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                   0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                    0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK                                       0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK             0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                   0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                         0x8000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                            0xf
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                   0x7fff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                      0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK                                           0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR                                          (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS                                          (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS                                          (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK                                          0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK            0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                       0x8000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                          0xf
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                 0x7fff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK                                            0x3ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK                                             0x7
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                        0x7
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                        0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK                                       0xffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                        0xff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                            0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                       0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                          0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK                                           0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK                                                     0x1ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                         0x100
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                           0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK                                                 0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT                                                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR                                                    (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS                                                    (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS                                                    (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK                                                    0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK                                              0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT                                                     0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK                                                  0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                               0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS                                                   (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK                                                     0xffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                      0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                       0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK                                                             0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK                                                     0xff00
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT                                                        0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK                                                    0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT                                                     0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS                                                     (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                     0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                           0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK                                         0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT                                            0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK                                                        0x3ffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK                                               0x3c00000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT                                                    0x16
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK                                           0x3fc000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT                                                0xe
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK                                            0x3000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT                                               0xc
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK                                             0xf00
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT                                               0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK                                                0x80
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT                                                 0x7
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK                                                 0x40
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT                                                  0x6
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                           0x20
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                            0x5
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                            0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                             0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK                                                 0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                                                 0x3
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK                                                 0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT                                                 0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK                                              0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT                                              0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK                                              0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT                                              0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK                                                0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                           0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS                                                (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK                                                      0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                 0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK                                         0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                     0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                              0xf
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                        0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR                                        (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS                                        (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS                                        (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK                                        0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                     0xf
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                  0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS                                      (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK                                           0x3ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                         0x3ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                           0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK                                              0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK                                         0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK                                                   0x1ff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                       0x100
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                         0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK                                               0xff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                                                0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS                                                  (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK                                                  0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK                                            0xffffffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT                                                   0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR                                            (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS                                            (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS                                            (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK                                                0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                             0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR                                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS                                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS                                                              (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                                                                 0x1ffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK                                           0x10000
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT                                              0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK                                                  0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT                                                     0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                                                                 0x3f
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK                                                         0x20
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT                                                          0x5
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK                                                 0x10
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT                                                  0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK                                                   0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT                                                   0x3
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK                                                       0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT                                                       0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK                                                       0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT                                                       0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK                                                          0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT                                                          0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS                                                       (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK                                                              0xf
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK                                               0x8
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT                                               0x3
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK                                                0x4
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT                                                0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK                                                0x2
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT                                                0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK                                                     0x1
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT                                                     0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                                                               0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS                                                           (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                                                               0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK                                                      0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT                                                         0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK                                                             0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT                                                       0x0

#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS                                                         (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK                                                             0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN          \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v)      \
        out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN)
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0

#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE                                                                    (SOC_WFSS_CE_REG_BASE      + 0x00018000)
#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS                                                               (SOC_WFSS_CE_REG_BASE_PHYS + 0x00018000)
#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS                                                               0x00018000

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000000)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000000)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK                                                   0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK                                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT                                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000004)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000004)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK                                                         0xff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK                                                   0xff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT                                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000008)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000008)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK                                                       0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK                                      0xe00
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                                        0x9
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK                                      0x1f0
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                                        0x4
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK                                        0xf
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                                        0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000000c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000000c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK                                                      0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK                               0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT                               0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000010)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000010)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK                                              0x80000fff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK                            0x80000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT                                  0x1f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK                                             0x800
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT                                               0xb
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK                                          0x400
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT                                            0xa
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK                                           0x200
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT                                             0x9
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK                                      0x100
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT                                        0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK                                       0x80
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT                                        0x7
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK                                         0x40
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT                                          0x6
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK                                    0x20
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT                                     0x5
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK                                    0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT                                     0x4
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK                                         0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT                                         0x3
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK                                         0x4
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT                                         0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK                                              0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT                                              0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK                                                0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT                                                0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000014)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000014)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000014)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK                                                     0x1010101
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK                                 0x1000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT                                      0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK                                    0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT                                       0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK                                      0x100
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                                        0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK                                         0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                                         0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000018)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000018)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS                                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000018)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK                                                     0x3f3f3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK                                0x3f0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT                                    0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK                                       0x3f00
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                                          0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK                                         0x3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                                          0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000001c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000001c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK                                             0xffff3f3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK           0xff000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT                 0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK            0xff0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT                0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK                   0x3f00
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT                      0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK                    0x3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT                     0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000020)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000020)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK                                             0xffff3f3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK           0xff000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT                 0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK            0xff0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT                0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK                   0x3f00
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT                      0x8
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK                    0x3f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT                     0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000024)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000024)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000024)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK                                                 0xfffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK                            0x8000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT                                 0x1b
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK                            0x4000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT                                 0x1a
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK                           0x2000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT                                0x19
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK                       0x1000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT                            0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK                        0x800000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT                            0x17
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK                             0x700000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT                                 0x14
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK                               0xe0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT                                  0x11
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK                          0x1fe00
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT                              0x9
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK                        0x1fe
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT                          0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK                                       0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT                                       0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000028)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000028)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000028)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK                                                0xffff0001
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK                                 0xffff0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT                                       0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK                                      0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000002c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000002c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000002c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK                                                     0xffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK                                     0xffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                                        0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000030)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000030)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK                                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK                             0xffff0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT                                   0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK                                0xffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT                                   0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000034)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000034)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK                                                0xfffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK                              0xe0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT                                 0x11
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK                                 0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT                                    0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                 0xffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000038)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000038)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS                                             (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK                                                0xfffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK                              0xe0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT                                 0x11
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK                                 0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT                                    0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                 0xffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000003c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000003c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK                                   0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000040)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000040)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK                                   0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000044)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000044)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK                                   0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000048)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000048)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS                                   (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK                                   0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000004c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000004c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK                                                        0x1ffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK                                                0x1000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT                                                     0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK                                             0xfff000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT                                                  0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK                                                0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT                                                  0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000050)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000050)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK                                                            0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK                                                0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT                                                  0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000054)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000054)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK                                                          0xffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK                                                     0xfff000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT                                                          0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK                                                         0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT                                                           0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000058)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000058)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK                                                      0x1ffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK                                              0x1000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT                                                   0x18
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK                                           0xfff000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT                                                0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK                                              0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT                                                0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000005c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000005c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK                                                          0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK                                              0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT                                                0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000060)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000060)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK                                            0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000064)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000064)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK                                            0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000068)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000068)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK                                                   0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK                                            0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000006c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000006c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK                                                 0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK                                          0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT                                                 0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000070)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000070)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK                                                 0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK                                          0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT                                                 0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000074)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000074)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000074)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK                                                        0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK                                                 0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT                                                 0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000078)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000078)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000078)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK                                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT                                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000007c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000007c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK                                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT                                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000080)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000080)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK                                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT                                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000084)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000084)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK                                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT                                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000088)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000088)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000088)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK                                                  0xfffdffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK                                       0x80000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT                                             0x1f
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK                                  0x40000000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT                                        0x1e
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK                                      0x3ffc0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT                                            0x12
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK                                              0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT                                                 0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK                                              0xf000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT                                                 0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK                                          0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000008c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000008c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000008c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK                                                    0xffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK                                       0xfff000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT                                            0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK                                          0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000090)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000090)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000090)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK                                                      0x1fff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK                                               0x1000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT                                                  0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK                                          0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT                                            0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000094)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000094)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000094)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK                                                          0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK                                                 0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT                                                   0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000098)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000098)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS                                            (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000098)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK                                            0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK                                      0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT                                             0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000009c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000009c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS                                                 (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000009c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK                                                 0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK                                             0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT                                                    0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000a0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK                                                        0xf00ff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK                                           0xf0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT                                              0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK                              0xc0
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT                               0x6
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK                              0x30
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT                               0x4
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK                               0xc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT                               0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK                               0x3
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT                               0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000a4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS                                               (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK                                                  0x10fff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK                   0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT                      0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK                                 0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT                                   0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000a8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK                                                        0x10fff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK                                               0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT                                                  0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK                                              0xfff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT                                                0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000ac)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000ac)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS                                              (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK                                                 0x300ff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_BMSK                    0x20000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_SHFT                       0x11
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK                       0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT                          0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK                               0xe0
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT                                0x5
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK                               0x1c
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT                                0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK                              0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT                              0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK                                     0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT                                     0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000b0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000b4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000b8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000bc)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000bc)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000bc)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000c0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS                                                (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c0)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK                               0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT                                      0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x000000c4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS                                                    (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c4)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK                                                           0x3
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK                                            0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT                                            0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK                                                0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT                                                0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000400)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000400)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000400)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK                                                          0x100ff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                     0x10000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                        0x10
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK                                          0xff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT                                           0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000404)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000404)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000404)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT                                                       0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000408)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000408)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS                                                     (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000408)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK                                                     0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK                                                0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT                                                       0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000040c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000040c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS                                                        (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000040c)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK                                                        0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK                                                    0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT                                                           0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000410)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000410)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS                                                       (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000410)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK                                                             0xff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK                                                         0xff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT                                                          0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR                                          (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000414)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS                                          (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000414)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS                                          (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000414)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK                                          0xffffffff
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK                        0xfffe0000
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT                              0x11
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK                         0x1fffc
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT                             0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK                      0x2
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT                      0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK                       0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT                       0x0

#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000418)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000418)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS                                                  (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000418)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK                                                         0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN          \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(m)      \
        in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, m)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(v)      \
        out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,v)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN)
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK                                  0x1
#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT                                  0x0

#endif