1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef __SOC_CE_SEQ_HWIOREG_H__ 17 #define __SOC_CE_SEQ_HWIOREG_H__ 18 19 #define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) 20 #define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00000000) 21 #define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000 22 23 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 24 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 25 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 26 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 27 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 28 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 29 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 30 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 31 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 32 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 33 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 34 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 35 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 36 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 37 38 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 39 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 40 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 41 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 42 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 43 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 44 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 45 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 46 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 47 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 48 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 49 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 50 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 51 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 52 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 53 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 54 55 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 56 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 57 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 58 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 59 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 60 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 61 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 62 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 63 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 64 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 65 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 66 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 67 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 68 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 69 70 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 71 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 72 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 73 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 74 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 75 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 76 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 77 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 78 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 79 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 80 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 81 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 82 83 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 84 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 85 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 86 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 87 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 88 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 89 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 90 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 91 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 92 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 93 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 94 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 95 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 96 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 97 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 98 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 99 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 100 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 101 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 102 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 103 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 104 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 105 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 106 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 107 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 108 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 109 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 110 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 111 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 112 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 113 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 114 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 115 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 116 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 117 118 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 119 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 120 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 121 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 122 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 123 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 124 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 125 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 126 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 127 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 128 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 129 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 130 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 131 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 132 133 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 134 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 135 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 136 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 137 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 138 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 139 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 140 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 141 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 142 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 143 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 144 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 145 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 146 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 147 148 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 149 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 150 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 151 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 152 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 153 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 154 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 155 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 156 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 157 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 158 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 159 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 160 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 161 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 162 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 163 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 164 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 165 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 166 167 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 168 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 169 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 170 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 171 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 172 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 173 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 174 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 175 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 176 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 177 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 178 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 179 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 180 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 181 182 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 183 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 184 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 185 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 186 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 187 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 188 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 189 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 190 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 191 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 192 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 193 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 194 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 195 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 196 197 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 198 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 199 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 200 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 201 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 202 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 203 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 204 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 205 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 206 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 207 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 208 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 209 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 210 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 211 212 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 213 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 214 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 215 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 216 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 217 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 218 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 219 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 220 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 221 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 222 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 223 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 224 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 225 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 226 227 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 228 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 229 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 230 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 231 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 232 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 233 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 234 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 235 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 236 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 237 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 238 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 239 240 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 241 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 242 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 243 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 244 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 245 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 246 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 247 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 248 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 249 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 250 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 251 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 252 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 253 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 254 255 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 256 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 257 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 258 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 259 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 260 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 261 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 262 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 263 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 264 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 265 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 266 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 267 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 268 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 269 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 270 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 271 272 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 273 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 274 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 275 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 276 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 277 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 278 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 279 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 280 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 281 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 282 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 283 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 284 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 285 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 286 287 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 288 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 289 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 290 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 291 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 292 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 293 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 294 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 295 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 296 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 297 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 298 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 299 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 300 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 301 302 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 303 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 304 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 305 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 306 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 307 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 308 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 309 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 310 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 311 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 312 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 313 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 314 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 315 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 316 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 317 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 318 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 319 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 320 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 321 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 322 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 323 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 324 325 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 326 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 327 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 328 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 329 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 330 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 331 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 332 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 333 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 334 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 335 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 336 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 337 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 338 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 339 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 340 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 341 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 342 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 343 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 344 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 345 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 346 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 347 348 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 349 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 350 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 351 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 352 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 353 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 354 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 355 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 356 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 357 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 358 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 359 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 360 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 361 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 362 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 363 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 364 365 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 366 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 367 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 368 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 369 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 370 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 371 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 372 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 373 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 374 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 375 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 376 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 377 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 378 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 379 380 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 381 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 382 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 383 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 384 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 385 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 386 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 387 in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 388 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 389 out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 390 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 391 out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 392 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 393 #define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 394 395 #define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) 396 #define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00001000) 397 #define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000 398 399 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) 400 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 401 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 402 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 403 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 404 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 405 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 406 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 407 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 408 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 409 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 410 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 411 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 412 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 413 414 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) 415 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 416 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 417 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 418 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 419 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 420 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 421 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 422 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 423 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 424 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 425 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 426 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 427 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 428 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 429 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 430 431 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000008) 432 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 433 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 434 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 435 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 436 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 437 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 438 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 439 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 440 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 441 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 442 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 443 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 444 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 445 446 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 447 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 448 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 449 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 450 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 451 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 452 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 453 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 454 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 455 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 456 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 457 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 458 459 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000010) 460 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 461 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 462 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 463 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 464 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 465 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 466 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 467 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 468 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 469 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 470 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 471 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 472 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 473 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 474 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 475 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 476 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 477 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 478 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 479 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 480 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 481 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 482 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 483 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 484 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 485 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 486 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 487 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 488 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 489 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 490 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 491 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 492 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 493 494 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 495 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 496 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 497 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 498 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 499 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 500 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 501 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 502 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 503 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 504 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 505 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 506 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 507 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 508 509 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000020) 510 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 511 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 512 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 513 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 514 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 515 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 516 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 517 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 518 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 519 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 520 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 521 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 522 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 523 524 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000030) 525 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 526 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 527 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 528 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 529 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 530 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 531 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 532 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 533 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 534 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 535 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 536 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 537 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 538 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 539 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 540 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 541 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 542 543 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000034) 544 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 545 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 546 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 547 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 548 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 549 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 550 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 551 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 552 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 553 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 554 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 555 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 556 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 557 558 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000038) 559 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 560 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 561 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 562 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 563 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 564 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 565 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 566 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 567 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 568 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 569 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 570 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 571 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 572 573 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 574 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 575 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 576 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 577 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 578 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 579 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 580 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 581 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 582 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 583 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 584 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 585 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 586 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 587 588 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000040) 589 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 590 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 591 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 592 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 593 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 594 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 595 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 596 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 597 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 598 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 599 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 600 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 601 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 602 603 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000044) 604 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 605 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 606 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 607 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 608 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 609 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 610 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 611 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 612 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 613 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 614 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 615 616 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000048) 617 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 618 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 619 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 620 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 621 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 622 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 623 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 624 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 625 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 626 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 627 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 628 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 629 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 630 631 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 632 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 633 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 634 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 635 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 636 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 637 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 638 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 639 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 640 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 641 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 642 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 643 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 644 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 645 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 646 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 647 648 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000050) 649 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 650 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 651 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 652 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 653 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 654 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 655 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 656 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 657 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 658 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 659 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 660 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 661 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 662 663 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000054) 664 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 665 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 666 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 667 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 668 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 669 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 670 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 671 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 672 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 673 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 674 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 675 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 676 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 677 678 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) 679 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 680 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 681 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 682 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 683 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 684 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 685 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 686 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 687 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 688 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 689 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 690 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 691 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 692 693 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 694 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 695 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 696 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 697 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 698 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 699 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 700 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 701 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 702 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 703 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 704 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 705 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 706 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 707 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 708 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 709 710 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000060) 711 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 712 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 713 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 714 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 715 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 716 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 717 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 718 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 719 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 720 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 721 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 722 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 723 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 724 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 725 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 726 727 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000064) 728 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 729 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 730 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 731 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 732 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 733 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 734 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 735 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 736 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 737 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 738 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 739 740 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000068) 741 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 742 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 743 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 744 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 745 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 746 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 747 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 748 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 749 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 750 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 751 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 752 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 753 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 754 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 755 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 756 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 757 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 758 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 759 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 760 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 761 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 762 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 763 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 764 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 765 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 766 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 767 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 768 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 769 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 770 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 771 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 772 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 773 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 774 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 775 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 776 777 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 778 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 779 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 780 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 781 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 782 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 783 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 784 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 785 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 786 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 787 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 788 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 789 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 790 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 791 792 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000070) 793 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 794 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 795 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 796 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 797 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 798 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 799 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 800 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 801 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 802 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 803 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 804 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 805 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 806 807 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 808 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 809 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 810 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 811 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 812 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 813 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 814 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 815 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 816 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 817 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 818 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 819 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 820 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 821 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 822 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 823 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 824 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 825 826 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000080) 827 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 828 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 829 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 830 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 831 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 832 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 833 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 834 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 835 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 836 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 837 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 838 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 839 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 840 841 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000084) 842 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 843 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 844 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 845 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 846 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 847 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 848 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 849 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 850 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 851 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 852 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 853 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 854 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 855 856 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 857 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 858 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 859 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 860 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 861 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 862 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 863 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 864 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 865 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 866 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 867 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 868 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 869 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 870 871 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 872 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 873 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 874 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 875 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 876 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 877 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 878 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 879 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 880 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 881 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 882 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 883 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 884 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 885 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 886 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 887 888 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 889 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 890 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 891 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 892 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 893 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 894 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 895 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 896 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 897 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 898 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 899 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 900 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 901 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 902 903 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 904 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 905 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 906 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 907 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 908 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 909 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 910 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 911 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 912 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 913 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 914 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 915 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 916 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 917 918 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 919 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 920 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 921 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 922 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 923 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 924 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 925 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 926 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 927 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 928 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 929 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 930 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 931 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 932 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 933 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 934 935 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 936 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 937 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 938 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 939 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 940 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 941 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 942 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 943 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 944 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 945 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 946 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 947 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 948 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 949 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 950 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 951 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 952 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 953 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 954 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 955 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 956 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 957 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 958 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 959 960 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 961 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 962 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 963 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 964 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 965 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 966 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 967 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 968 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 969 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 970 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 971 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 972 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 973 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 974 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 975 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 976 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 977 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 978 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 979 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 980 981 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) 982 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 983 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 984 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 985 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 986 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 987 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 988 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 989 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 990 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 991 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 992 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 993 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 994 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 995 996 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000404) 997 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 998 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 999 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 1000 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 1001 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 1002 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 1003 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 1004 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 1005 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 1006 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 1007 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 1008 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 1009 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 1010 1011 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) 1012 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 1013 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 1014 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 1015 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 1016 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 1017 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 1018 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 1019 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 1020 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 1021 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 1022 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 1023 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 1024 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 1025 1026 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 1027 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 1028 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 1029 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 1030 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 1031 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 1032 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 1033 in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 1034 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 1035 out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 1036 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 1037 out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 1038 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 1039 #define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 1040 1041 #define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) 1042 #define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00002000) 1043 #define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000 1044 1045 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 1046 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 1047 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 1048 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 1049 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 1050 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 1051 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 1052 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 1053 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 1054 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 1055 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 1056 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 1057 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1058 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1059 1060 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 1061 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 1062 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 1063 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 1064 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 1065 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 1066 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 1067 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 1068 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 1069 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 1070 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 1071 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 1072 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 1073 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1074 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 1075 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1076 1077 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 1078 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 1079 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 1080 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 1081 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 1082 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 1083 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 1084 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 1085 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 1086 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 1087 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 1088 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 1089 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 1090 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 1091 1092 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 1093 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 1094 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 1095 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 1096 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 1097 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 1098 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 1099 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 1100 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1101 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1102 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 1103 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1104 1105 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 1106 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 1107 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 1108 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 1109 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 1110 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 1111 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 1112 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 1113 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 1114 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 1115 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 1116 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 1117 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 1118 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 1119 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 1120 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1121 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 1122 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1123 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 1124 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1125 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 1126 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 1127 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 1128 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1129 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 1130 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1131 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 1132 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1133 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 1134 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 1135 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 1136 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1137 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 1138 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1139 1140 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 1141 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 1142 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 1143 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 1144 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 1145 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 1146 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 1147 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 1148 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 1149 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 1150 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 1151 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 1152 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1153 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1154 1155 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 1156 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 1157 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 1158 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 1159 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 1160 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 1161 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 1162 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 1163 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 1164 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 1165 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 1166 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 1167 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 1168 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1169 1170 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 1171 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 1172 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 1173 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1174 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 1175 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1176 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 1177 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 1178 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 1179 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 1180 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 1181 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 1182 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1183 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1184 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 1185 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1186 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 1187 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1188 1189 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 1190 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 1191 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 1192 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 1193 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 1194 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1195 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 1196 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 1197 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 1198 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 1199 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 1200 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 1201 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 1202 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1203 1204 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 1205 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 1206 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 1207 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1208 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 1209 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 1210 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 1211 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 1212 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1213 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1214 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 1215 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1216 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 1217 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1218 1219 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 1220 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 1221 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 1222 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 1223 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 1224 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1225 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 1226 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 1227 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 1228 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 1229 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 1230 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 1231 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 1232 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1233 1234 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 1235 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 1236 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 1237 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 1238 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 1239 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1240 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 1241 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 1242 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 1243 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 1244 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 1245 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 1246 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 1247 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1248 1249 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 1250 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 1251 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 1252 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 1253 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 1254 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1255 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 1256 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 1257 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 1258 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1259 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 1260 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1261 1262 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 1263 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 1264 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 1265 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1266 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 1267 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 1268 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 1269 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 1270 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 1271 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 1272 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 1273 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 1274 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1275 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1276 1277 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 1278 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 1279 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 1280 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 1281 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 1282 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 1283 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 1284 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 1285 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 1286 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 1287 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 1288 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 1289 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 1290 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1291 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 1292 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1293 1294 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 1295 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 1296 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 1297 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 1298 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 1299 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 1300 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 1301 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 1302 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 1303 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 1304 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 1305 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 1306 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1307 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 1308 1309 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 1310 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 1311 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 1312 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 1313 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 1314 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 1315 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 1316 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 1317 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 1318 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 1319 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 1320 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 1321 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 1322 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1323 1324 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 1325 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 1326 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 1327 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 1328 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 1329 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 1330 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 1331 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 1332 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 1333 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 1334 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 1335 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 1336 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 1337 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 1338 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 1339 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 1340 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 1341 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 1342 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 1343 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 1344 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 1345 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 1346 1347 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 1348 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 1349 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 1350 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 1351 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 1352 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 1353 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 1354 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 1355 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 1356 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 1357 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 1358 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 1359 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 1360 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 1361 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 1362 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 1363 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 1364 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 1365 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 1366 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 1367 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 1368 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 1369 1370 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 1371 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 1372 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 1373 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 1374 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 1375 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 1376 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 1377 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 1378 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 1379 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 1380 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 1381 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 1382 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 1383 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 1384 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 1385 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 1386 1387 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 1388 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 1389 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 1390 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 1391 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 1392 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 1393 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 1394 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 1395 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 1396 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 1397 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 1398 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 1399 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 1400 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 1401 1402 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 1403 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 1404 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 1405 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 1406 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 1407 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 1408 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 1409 in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 1410 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 1411 out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 1412 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 1413 out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 1414 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 1415 #define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 1416 1417 #define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) 1418 #define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00003000) 1419 #define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000 1420 1421 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) 1422 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 1423 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 1424 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 1425 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 1426 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 1427 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 1428 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 1429 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 1430 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 1431 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 1432 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 1433 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1434 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1435 1436 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) 1437 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 1438 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 1439 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 1440 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 1441 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 1442 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 1443 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 1444 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 1445 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 1446 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 1447 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 1448 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 1449 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1450 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 1451 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1452 1453 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000008) 1454 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 1455 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 1456 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 1457 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 1458 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 1459 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 1460 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 1461 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 1462 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 1463 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 1464 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 1465 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 1466 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 1467 1468 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 1469 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 1470 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 1471 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 1472 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 1473 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 1474 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 1475 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 1476 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1477 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1478 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 1479 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1480 1481 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000010) 1482 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 1483 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 1484 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 1485 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 1486 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 1487 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 1488 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 1489 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 1490 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 1491 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 1492 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 1493 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 1494 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 1495 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 1496 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1497 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 1498 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1499 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 1500 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1501 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 1502 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 1503 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 1504 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1505 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 1506 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1507 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 1508 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1509 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 1510 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 1511 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 1512 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1513 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 1514 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1515 1516 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 1517 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 1518 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 1519 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 1520 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 1521 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 1522 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 1523 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 1524 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 1525 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 1526 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 1527 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 1528 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1529 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1530 1531 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000020) 1532 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 1533 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 1534 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 1535 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 1536 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 1537 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 1538 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 1539 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 1540 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 1541 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 1542 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 1543 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 1544 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1545 1546 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000030) 1547 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 1548 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 1549 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1550 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 1551 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1552 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 1553 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 1554 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 1555 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 1556 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 1557 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 1558 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1559 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1560 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 1561 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1562 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 1563 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1564 1565 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000034) 1566 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 1567 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 1568 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 1569 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 1570 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1571 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 1572 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 1573 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 1574 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 1575 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 1576 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 1577 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 1578 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1579 1580 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000038) 1581 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 1582 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 1583 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1584 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 1585 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 1586 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 1587 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 1588 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1589 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1590 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 1591 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1592 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 1593 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1594 1595 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 1596 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 1597 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 1598 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 1599 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 1600 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1601 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 1602 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 1603 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 1604 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 1605 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 1606 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 1607 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 1608 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1609 1610 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000040) 1611 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 1612 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 1613 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 1614 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 1615 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1616 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 1617 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 1618 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 1619 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 1620 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 1621 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 1622 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 1623 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1624 1625 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000044) 1626 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 1627 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 1628 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 1629 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 1630 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1631 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 1632 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 1633 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 1634 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1635 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 1636 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1637 1638 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000048) 1639 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 1640 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 1641 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1642 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 1643 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 1644 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 1645 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 1646 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 1647 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 1648 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 1649 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 1650 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1651 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1652 1653 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 1654 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 1655 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 1656 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 1657 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 1658 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 1659 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 1660 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 1661 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 1662 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 1663 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 1664 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 1665 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 1666 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1667 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 1668 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1669 1670 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000050) 1671 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 1672 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 1673 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 1674 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 1675 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 1676 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 1677 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 1678 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 1679 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 1680 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 1681 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 1682 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1683 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 1684 1685 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000054) 1686 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 1687 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 1688 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 1689 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 1690 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 1691 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 1692 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 1693 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 1694 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 1695 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 1696 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 1697 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 1698 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1699 1700 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000058) 1701 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 1702 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 1703 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 1704 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 1705 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 1706 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 1707 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 1708 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 1709 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 1710 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 1711 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 1712 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1713 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1714 1715 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 1716 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 1717 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 1718 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 1719 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 1720 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 1721 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 1722 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 1723 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 1724 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 1725 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 1726 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 1727 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 1728 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1729 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 1730 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1731 1732 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000060) 1733 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 1734 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 1735 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 1736 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 1737 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 1738 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 1739 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 1740 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 1741 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 1742 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 1743 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 1744 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 1745 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 1746 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 1747 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 1748 1749 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000064) 1750 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 1751 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 1752 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 1753 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 1754 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 1755 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 1756 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 1757 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1758 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1759 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 1760 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1761 1762 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000068) 1763 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 1764 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 1765 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 1766 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 1767 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 1768 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 1769 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 1770 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 1771 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 1772 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 1773 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 1774 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 1775 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 1776 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 1777 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 1778 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 1779 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1780 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 1781 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1782 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 1783 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1784 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 1785 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 1786 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 1787 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1788 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 1789 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1790 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 1791 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1792 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 1793 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 1794 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 1795 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1796 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 1797 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1798 1799 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 1800 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 1801 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 1802 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 1803 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 1804 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 1805 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 1806 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 1807 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 1808 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 1809 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 1810 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 1811 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 1812 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 1813 1814 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000070) 1815 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 1816 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 1817 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 1818 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 1819 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 1820 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 1821 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 1822 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 1823 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 1824 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 1825 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 1826 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 1827 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 1828 1829 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 1830 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 1831 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 1832 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 1833 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 1834 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 1835 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 1836 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 1837 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 1838 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 1839 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 1840 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 1841 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1842 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1843 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 1844 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 1845 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 1846 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1847 1848 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000080) 1849 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 1850 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 1851 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 1852 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 1853 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 1854 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 1855 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 1856 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1857 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1858 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 1859 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 1860 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 1861 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1862 1863 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000084) 1864 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 1865 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 1866 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 1867 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 1868 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 1869 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 1870 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 1871 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 1872 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 1873 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 1874 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 1875 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 1876 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 1877 1878 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 1879 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 1880 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 1881 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1882 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 1883 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 1884 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 1885 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 1886 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 1887 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 1888 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 1889 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 1890 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1891 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1892 1893 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 1894 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 1895 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 1896 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 1897 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 1898 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 1899 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 1900 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 1901 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 1902 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 1903 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 1904 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 1905 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 1906 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1907 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 1908 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1909 1910 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 1911 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 1912 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 1913 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 1914 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 1915 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 1916 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 1917 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 1918 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 1919 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 1920 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 1921 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 1922 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1923 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 1924 1925 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 1926 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 1927 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 1928 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 1929 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 1930 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 1931 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 1932 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 1933 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 1934 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 1935 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 1936 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 1937 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 1938 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1939 1940 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 1941 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 1942 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 1943 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 1944 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 1945 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 1946 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 1947 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 1948 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 1949 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 1950 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 1951 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 1952 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 1953 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 1954 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 1955 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 1956 1957 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 1958 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 1959 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 1960 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 1961 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 1962 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 1963 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 1964 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 1965 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 1966 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 1967 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 1968 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 1969 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 1970 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 1971 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 1972 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 1973 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 1974 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 1975 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 1976 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 1977 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 1978 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 1979 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 1980 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 1981 1982 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 1983 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 1984 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 1985 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 1986 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 1987 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 1988 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 1989 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 1990 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 1991 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 1992 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 1993 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 1994 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 1995 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 1996 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 1997 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 1998 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 1999 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 2000 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 2001 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 2002 2003 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000400) 2004 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 2005 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 2006 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 2007 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 2008 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 2009 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 2010 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 2011 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 2012 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 2013 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 2014 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 2015 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 2016 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 2017 2018 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000404) 2019 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 2020 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 2021 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 2022 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 2023 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 2024 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 2025 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 2026 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 2027 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 2028 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 2029 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 2030 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 2031 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 2032 2033 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000408) 2034 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 2035 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 2036 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 2037 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 2038 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 2039 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 2040 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 2041 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 2042 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 2043 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 2044 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 2045 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 2046 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 2047 2048 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 2049 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 2050 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 2051 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 2052 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 2053 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 2054 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 2055 in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 2056 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 2057 out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 2058 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 2059 out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 2060 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 2061 #define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 2062 2063 #define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00004000) 2064 #define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00004000) 2065 #define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000 2066 2067 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 2068 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 2069 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 2070 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 2071 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 2072 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 2073 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 2074 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 2075 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 2076 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 2077 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 2078 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 2079 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2080 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2081 2082 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 2083 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 2084 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 2085 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 2086 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 2087 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 2088 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 2089 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 2090 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 2091 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 2092 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 2093 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 2094 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 2095 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2096 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 2097 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2098 2099 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 2100 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 2101 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 2102 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 2103 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 2104 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 2105 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 2106 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 2107 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 2108 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 2109 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 2110 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 2111 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 2112 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 2113 2114 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 2115 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 2116 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 2117 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 2118 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 2119 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 2120 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 2121 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 2122 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2123 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2124 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 2125 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2126 2127 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 2128 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 2129 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 2130 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 2131 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 2132 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 2133 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 2134 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 2135 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 2136 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 2137 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 2138 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 2139 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 2140 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 2141 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 2142 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2143 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 2144 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2145 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 2146 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2147 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 2148 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 2149 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 2150 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2151 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 2152 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2153 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 2154 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2155 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 2156 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 2157 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 2158 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2159 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 2160 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2161 2162 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 2163 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 2164 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 2165 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 2166 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 2167 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 2168 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 2169 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 2170 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 2171 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 2172 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 2173 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 2174 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2175 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2176 2177 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 2178 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 2179 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 2180 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 2181 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 2182 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 2183 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 2184 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 2185 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 2186 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 2187 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 2188 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 2189 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 2190 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2191 2192 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 2193 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 2194 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 2195 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2196 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 2197 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2198 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 2199 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 2200 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 2201 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 2202 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 2203 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 2204 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2205 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2206 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 2207 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2208 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 2209 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2210 2211 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 2212 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 2213 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 2214 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 2215 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 2216 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2217 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 2218 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 2219 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 2220 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 2221 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 2222 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 2223 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 2224 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2225 2226 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 2227 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 2228 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 2229 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2230 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 2231 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 2232 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 2233 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 2234 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2235 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2236 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 2237 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2238 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 2239 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2240 2241 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 2242 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 2243 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 2244 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 2245 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 2246 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2247 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 2248 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 2249 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 2250 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 2251 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 2252 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 2253 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 2254 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2255 2256 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 2257 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 2258 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 2259 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 2260 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 2261 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2262 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 2263 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 2264 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 2265 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 2266 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 2267 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 2268 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 2269 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2270 2271 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 2272 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 2273 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 2274 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 2275 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 2276 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2277 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 2278 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 2279 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 2280 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2281 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 2282 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2283 2284 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 2285 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 2286 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 2287 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2288 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 2289 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 2290 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 2291 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 2292 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 2293 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 2294 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 2295 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 2296 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2297 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2298 2299 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 2300 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 2301 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 2302 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 2303 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 2304 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 2305 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 2306 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 2307 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 2308 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 2309 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 2310 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 2311 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 2312 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2313 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 2314 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2315 2316 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 2317 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 2318 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 2319 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 2320 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 2321 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 2322 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 2323 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 2324 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 2325 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 2326 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 2327 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 2328 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2329 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 2330 2331 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 2332 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 2333 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 2334 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 2335 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 2336 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 2337 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 2338 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 2339 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 2340 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 2341 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 2342 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 2343 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 2344 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2345 2346 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 2347 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 2348 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 2349 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 2350 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 2351 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 2352 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 2353 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 2354 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 2355 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 2356 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 2357 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 2358 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 2359 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 2360 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 2361 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 2362 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 2363 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 2364 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 2365 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 2366 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 2367 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 2368 2369 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 2370 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 2371 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 2372 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 2373 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 2374 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 2375 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 2376 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 2377 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 2378 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 2379 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 2380 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 2381 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 2382 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 2383 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 2384 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 2385 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 2386 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 2387 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 2388 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 2389 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 2390 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 2391 2392 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 2393 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 2394 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 2395 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 2396 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 2397 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 2398 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 2399 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 2400 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 2401 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 2402 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 2403 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 2404 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 2405 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 2406 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 2407 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 2408 2409 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 2410 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 2411 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 2412 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 2413 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 2414 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 2415 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 2416 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 2417 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 2418 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 2419 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 2420 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 2421 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 2422 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 2423 2424 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 2425 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 2426 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 2427 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 2428 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 2429 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 2430 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 2431 in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 2432 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 2433 out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 2434 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 2435 out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 2436 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 2437 #define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 2438 2439 #define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00005000) 2440 #define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00005000) 2441 #define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000 2442 2443 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000000) 2444 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 2445 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 2446 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 2447 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 2448 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 2449 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 2450 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 2451 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 2452 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 2453 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 2454 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 2455 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2456 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2457 2458 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000004) 2459 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 2460 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 2461 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 2462 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 2463 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 2464 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 2465 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 2466 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 2467 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 2468 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 2469 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 2470 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 2471 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2472 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 2473 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2474 2475 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000008) 2476 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 2477 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 2478 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 2479 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 2480 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 2481 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 2482 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 2483 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 2484 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 2485 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 2486 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 2487 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 2488 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 2489 2490 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 2491 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 2492 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 2493 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 2494 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 2495 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 2496 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 2497 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 2498 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2499 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2500 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 2501 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2502 2503 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000010) 2504 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 2505 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 2506 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 2507 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 2508 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 2509 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 2510 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 2511 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 2512 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 2513 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 2514 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 2515 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 2516 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 2517 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 2518 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2519 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 2520 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2521 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 2522 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2523 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 2524 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 2525 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 2526 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2527 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 2528 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2529 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 2530 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2531 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 2532 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 2533 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 2534 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2535 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 2536 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2537 2538 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 2539 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 2540 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 2541 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 2542 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 2543 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 2544 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 2545 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 2546 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 2547 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 2548 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 2549 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 2550 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2551 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2552 2553 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000020) 2554 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 2555 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 2556 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 2557 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 2558 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 2559 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 2560 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 2561 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 2562 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 2563 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 2564 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 2565 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 2566 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2567 2568 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000030) 2569 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 2570 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 2571 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2572 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 2573 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2574 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 2575 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 2576 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 2577 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 2578 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 2579 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 2580 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2581 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2582 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 2583 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2584 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 2585 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2586 2587 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000034) 2588 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 2589 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 2590 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 2591 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 2592 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2593 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 2594 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 2595 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 2596 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 2597 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 2598 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 2599 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 2600 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2601 2602 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000038) 2603 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 2604 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 2605 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2606 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 2607 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 2608 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 2609 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 2610 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2611 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2612 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 2613 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2614 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 2615 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2616 2617 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 2618 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 2619 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 2620 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 2621 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 2622 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2623 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 2624 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 2625 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 2626 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 2627 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 2628 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 2629 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 2630 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2631 2632 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000040) 2633 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 2634 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 2635 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 2636 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 2637 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2638 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 2639 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 2640 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 2641 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 2642 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 2643 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 2644 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 2645 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2646 2647 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000044) 2648 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 2649 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 2650 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 2651 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 2652 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2653 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 2654 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 2655 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 2656 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2657 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 2658 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2659 2660 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000048) 2661 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 2662 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 2663 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2664 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 2665 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 2666 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 2667 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 2668 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 2669 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 2670 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 2671 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 2672 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2673 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2674 2675 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 2676 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 2677 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 2678 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 2679 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 2680 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 2681 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 2682 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 2683 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 2684 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 2685 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 2686 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 2687 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 2688 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2689 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 2690 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2691 2692 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000050) 2693 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 2694 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 2695 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 2696 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 2697 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 2698 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 2699 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 2700 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 2701 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 2702 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 2703 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 2704 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2705 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 2706 2707 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000054) 2708 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 2709 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 2710 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 2711 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 2712 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 2713 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 2714 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 2715 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 2716 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 2717 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 2718 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 2719 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 2720 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2721 2722 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000058) 2723 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 2724 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 2725 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 2726 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 2727 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 2728 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 2729 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 2730 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 2731 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 2732 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 2733 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 2734 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2735 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2736 2737 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 2738 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 2739 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 2740 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 2741 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 2742 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 2743 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 2744 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 2745 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 2746 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 2747 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 2748 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 2749 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 2750 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2751 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 2752 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2753 2754 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000060) 2755 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 2756 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 2757 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 2758 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 2759 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 2760 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 2761 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 2762 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 2763 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 2764 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 2765 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 2766 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 2767 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 2768 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 2769 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 2770 2771 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000064) 2772 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 2773 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 2774 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 2775 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 2776 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 2777 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 2778 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 2779 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2780 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2781 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 2782 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2783 2784 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000068) 2785 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 2786 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 2787 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 2788 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 2789 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 2790 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 2791 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 2792 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 2793 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 2794 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 2795 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 2796 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 2797 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 2798 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 2799 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 2800 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 2801 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2802 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 2803 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2804 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 2805 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2806 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 2807 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 2808 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 2809 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2810 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 2811 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2812 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 2813 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2814 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 2815 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 2816 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 2817 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2818 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 2819 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2820 2821 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 2822 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 2823 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 2824 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 2825 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 2826 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 2827 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 2828 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 2829 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 2830 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 2831 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 2832 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 2833 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 2834 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 2835 2836 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000070) 2837 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 2838 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 2839 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 2840 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 2841 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 2842 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 2843 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 2844 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 2845 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 2846 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 2847 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 2848 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 2849 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 2850 2851 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 2852 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 2853 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 2854 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 2855 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 2856 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 2857 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 2858 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 2859 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 2860 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 2861 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 2862 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 2863 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2864 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2865 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 2866 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 2867 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 2868 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2869 2870 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000080) 2871 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 2872 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 2873 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 2874 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 2875 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 2876 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 2877 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 2878 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2879 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2880 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 2881 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 2882 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 2883 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2884 2885 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000084) 2886 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 2887 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 2888 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 2889 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 2890 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 2891 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 2892 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 2893 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 2894 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 2895 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 2896 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 2897 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 2898 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 2899 2900 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 2901 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 2902 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 2903 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2904 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 2905 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 2906 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 2907 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 2908 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 2909 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 2910 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 2911 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 2912 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2913 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2914 2915 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 2916 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 2917 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 2918 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 2919 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 2920 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 2921 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 2922 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 2923 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 2924 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 2925 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 2926 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 2927 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 2928 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2929 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 2930 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2931 2932 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 2933 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 2934 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 2935 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 2936 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 2937 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 2938 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 2939 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 2940 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 2941 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 2942 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 2943 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 2944 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2945 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 2946 2947 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 2948 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 2949 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 2950 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 2951 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 2952 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 2953 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 2954 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 2955 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 2956 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 2957 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 2958 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 2959 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 2960 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2961 2962 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 2963 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 2964 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 2965 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 2966 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 2967 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 2968 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 2969 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 2970 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 2971 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 2972 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 2973 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 2974 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 2975 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 2976 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 2977 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 2978 2979 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 2980 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 2981 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 2982 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 2983 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 2984 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 2985 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 2986 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 2987 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 2988 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 2989 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 2990 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 2991 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 2992 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 2993 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 2994 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 2995 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 2996 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 2997 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 2998 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 2999 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 3000 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 3001 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 3002 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 3003 3004 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 3005 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 3006 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 3007 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 3008 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 3009 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 3010 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 3011 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 3012 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 3013 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 3014 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 3015 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 3016 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 3017 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 3018 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 3019 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 3020 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 3021 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 3022 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 3023 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 3024 3025 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000400) 3026 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 3027 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 3028 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 3029 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 3030 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 3031 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 3032 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 3033 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 3034 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 3035 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 3036 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 3037 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 3038 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 3039 3040 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000404) 3041 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 3042 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 3043 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 3044 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 3045 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 3046 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 3047 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 3048 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 3049 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 3050 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 3051 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 3052 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 3053 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 3054 3055 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000408) 3056 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 3057 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 3058 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 3059 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 3060 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 3061 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 3062 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 3063 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 3064 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 3065 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 3066 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 3067 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 3068 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 3069 3070 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 3071 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 3072 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 3073 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 3074 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 3075 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 3076 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 3077 in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 3078 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 3079 out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 3080 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 3081 out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 3082 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 3083 #define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 3084 3085 #define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00006000) 3086 #define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00006000) 3087 #define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000 3088 3089 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 3090 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 3091 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 3092 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 3093 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 3094 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 3095 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 3096 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 3097 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 3098 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 3099 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 3100 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 3101 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3102 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3103 3104 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 3105 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 3106 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 3107 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 3108 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 3109 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 3110 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 3111 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 3112 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 3113 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 3114 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 3115 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 3116 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 3117 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3118 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 3119 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3120 3121 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 3122 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 3123 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 3124 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 3125 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 3126 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 3127 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 3128 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 3129 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 3130 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 3131 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 3132 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 3133 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 3134 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 3135 3136 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 3137 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 3138 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 3139 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 3140 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 3141 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 3142 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 3143 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 3144 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3145 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3146 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 3147 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3148 3149 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 3150 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 3151 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 3152 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 3153 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 3154 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 3155 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 3156 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 3157 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 3158 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 3159 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 3160 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 3161 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 3162 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 3163 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 3164 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3165 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 3166 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3167 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 3168 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3169 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 3170 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 3171 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 3172 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3173 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 3174 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3175 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 3176 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3177 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 3178 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 3179 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 3180 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3181 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 3182 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3183 3184 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 3185 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 3186 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 3187 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 3188 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 3189 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 3190 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 3191 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 3192 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 3193 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 3194 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 3195 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 3196 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3197 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3198 3199 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 3200 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 3201 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 3202 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 3203 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 3204 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 3205 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 3206 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 3207 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 3208 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 3209 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 3210 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 3211 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 3212 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3213 3214 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 3215 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 3216 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 3217 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3218 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 3219 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3220 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 3221 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 3222 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 3223 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 3224 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 3225 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 3226 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3227 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3228 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 3229 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3230 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 3231 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3232 3233 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 3234 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 3235 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 3236 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 3237 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 3238 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3239 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 3240 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 3241 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 3242 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 3243 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 3244 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 3245 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 3246 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3247 3248 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 3249 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 3250 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 3251 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3252 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 3253 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 3254 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 3255 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 3256 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3257 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3258 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 3259 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3260 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 3261 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3262 3263 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 3264 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 3265 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 3266 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 3267 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 3268 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3269 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 3270 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 3271 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 3272 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 3273 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 3274 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 3275 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 3276 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3277 3278 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 3279 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 3280 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 3281 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 3282 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 3283 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3284 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 3285 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 3286 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 3287 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 3288 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 3289 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 3290 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 3291 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3292 3293 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 3294 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 3295 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 3296 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 3297 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 3298 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3299 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 3300 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 3301 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 3302 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3303 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 3304 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3305 3306 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 3307 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 3308 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 3309 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3310 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 3311 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 3312 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 3313 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 3314 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 3315 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 3316 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 3317 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 3318 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3319 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3320 3321 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 3322 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 3323 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 3324 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 3325 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 3326 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 3327 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 3328 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 3329 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 3330 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 3331 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 3332 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 3333 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 3334 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3335 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 3336 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3337 3338 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 3339 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 3340 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 3341 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 3342 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 3343 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 3344 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 3345 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 3346 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 3347 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 3348 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 3349 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 3350 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3351 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 3352 3353 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 3354 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 3355 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 3356 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 3357 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 3358 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 3359 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 3360 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 3361 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 3362 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 3363 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 3364 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 3365 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 3366 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3367 3368 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 3369 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 3370 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 3371 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 3372 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 3373 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 3374 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 3375 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 3376 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 3377 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 3378 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 3379 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 3380 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 3381 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 3382 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 3383 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 3384 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 3385 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 3386 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 3387 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 3388 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 3389 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 3390 3391 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 3392 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 3393 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 3394 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 3395 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 3396 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 3397 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 3398 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 3399 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 3400 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 3401 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 3402 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 3403 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 3404 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 3405 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 3406 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 3407 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 3408 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 3409 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 3410 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 3411 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 3412 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 3413 3414 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 3415 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 3416 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 3417 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 3418 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 3419 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 3420 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 3421 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 3422 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 3423 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 3424 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 3425 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 3426 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 3427 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 3428 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 3429 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 3430 3431 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 3432 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 3433 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 3434 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 3435 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 3436 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 3437 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 3438 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 3439 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 3440 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 3441 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 3442 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 3443 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 3444 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 3445 3446 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 3447 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 3448 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 3449 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 3450 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 3451 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 3452 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 3453 in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 3454 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 3455 out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 3456 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 3457 out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 3458 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 3459 #define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 3460 3461 #define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00007000) 3462 #define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00007000) 3463 #define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000 3464 3465 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000000) 3466 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 3467 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 3468 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 3469 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 3470 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 3471 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 3472 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 3473 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 3474 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 3475 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 3476 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 3477 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3478 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3479 3480 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000004) 3481 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 3482 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 3483 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 3484 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 3485 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 3486 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 3487 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 3488 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 3489 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 3490 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 3491 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 3492 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 3493 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3494 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 3495 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3496 3497 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000008) 3498 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 3499 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 3500 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 3501 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 3502 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 3503 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 3504 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 3505 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 3506 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 3507 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 3508 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 3509 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 3510 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 3511 3512 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 3513 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 3514 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 3515 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 3516 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 3517 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 3518 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 3519 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 3520 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3521 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3522 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 3523 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3524 3525 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000010) 3526 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 3527 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 3528 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 3529 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 3530 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 3531 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 3532 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 3533 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 3534 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 3535 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 3536 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 3537 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 3538 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 3539 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 3540 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3541 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 3542 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3543 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 3544 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3545 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 3546 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 3547 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 3548 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3549 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 3550 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3551 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 3552 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3553 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 3554 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 3555 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 3556 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3557 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 3558 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3559 3560 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 3561 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 3562 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 3563 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 3564 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 3565 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 3566 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 3567 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 3568 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 3569 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 3570 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 3571 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 3572 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3573 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3574 3575 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000020) 3576 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 3577 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 3578 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 3579 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 3580 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 3581 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 3582 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 3583 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 3584 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 3585 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 3586 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 3587 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 3588 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3589 3590 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000030) 3591 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 3592 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 3593 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3594 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 3595 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3596 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 3597 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 3598 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 3599 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 3600 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 3601 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 3602 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3603 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3604 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 3605 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3606 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 3607 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3608 3609 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000034) 3610 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 3611 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 3612 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 3613 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 3614 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3615 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 3616 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 3617 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 3618 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 3619 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 3620 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 3621 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 3622 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3623 3624 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000038) 3625 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 3626 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 3627 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3628 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 3629 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 3630 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 3631 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 3632 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3633 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3634 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 3635 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3636 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 3637 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3638 3639 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 3640 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 3641 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 3642 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 3643 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 3644 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3645 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 3646 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 3647 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 3648 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 3649 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 3650 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 3651 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 3652 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3653 3654 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000040) 3655 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 3656 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 3657 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 3658 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 3659 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3660 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 3661 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 3662 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 3663 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 3664 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 3665 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 3666 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 3667 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3668 3669 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000044) 3670 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 3671 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 3672 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 3673 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 3674 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3675 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 3676 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 3677 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 3678 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3679 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 3680 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3681 3682 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000048) 3683 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 3684 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 3685 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3686 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 3687 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 3688 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 3689 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 3690 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 3691 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 3692 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 3693 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 3694 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3695 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3696 3697 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 3698 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 3699 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 3700 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 3701 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 3702 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 3703 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 3704 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 3705 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 3706 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 3707 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 3708 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 3709 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 3710 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3711 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 3712 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3713 3714 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000050) 3715 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 3716 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 3717 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 3718 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 3719 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 3720 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 3721 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 3722 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 3723 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 3724 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 3725 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 3726 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3727 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 3728 3729 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000054) 3730 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 3731 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 3732 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 3733 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 3734 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 3735 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 3736 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 3737 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 3738 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 3739 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 3740 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 3741 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 3742 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3743 3744 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000058) 3745 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 3746 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 3747 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 3748 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 3749 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 3750 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 3751 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 3752 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 3753 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 3754 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 3755 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 3756 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3757 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3758 3759 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 3760 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 3761 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 3762 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 3763 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 3764 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 3765 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 3766 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 3767 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 3768 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 3769 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 3770 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 3771 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 3772 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3773 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 3774 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3775 3776 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000060) 3777 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 3778 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 3779 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 3780 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 3781 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 3782 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 3783 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 3784 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 3785 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 3786 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 3787 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 3788 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 3789 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 3790 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 3791 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 3792 3793 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000064) 3794 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 3795 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 3796 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 3797 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 3798 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 3799 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 3800 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 3801 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3802 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3803 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 3804 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3805 3806 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000068) 3807 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 3808 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 3809 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 3810 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 3811 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 3812 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 3813 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 3814 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 3815 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 3816 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 3817 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 3818 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 3819 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 3820 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 3821 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 3822 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 3823 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3824 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 3825 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3826 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 3827 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3828 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 3829 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 3830 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 3831 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3832 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 3833 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3834 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 3835 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3836 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 3837 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 3838 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 3839 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3840 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 3841 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3842 3843 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 3844 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 3845 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 3846 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 3847 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 3848 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 3849 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 3850 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 3851 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 3852 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 3853 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 3854 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 3855 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3856 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3857 3858 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000070) 3859 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 3860 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 3861 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 3862 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 3863 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 3864 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 3865 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 3866 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 3867 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 3868 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 3869 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 3870 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 3871 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3872 3873 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 3874 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 3875 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 3876 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3877 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 3878 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 3879 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 3880 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 3881 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 3882 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 3883 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 3884 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 3885 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3886 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3887 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 3888 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3889 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 3890 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3891 3892 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000080) 3893 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 3894 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 3895 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3896 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 3897 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 3898 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 3899 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 3900 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3901 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3902 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 3903 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3904 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 3905 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3906 3907 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000084) 3908 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 3909 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 3910 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 3911 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 3912 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 3913 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 3914 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 3915 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 3916 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 3917 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 3918 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 3919 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 3920 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3921 3922 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 3923 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 3924 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 3925 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3926 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 3927 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 3928 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 3929 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 3930 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 3931 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 3932 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 3933 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 3934 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3935 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3936 3937 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 3938 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 3939 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 3940 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 3941 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 3942 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 3943 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 3944 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 3945 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 3946 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 3947 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 3948 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 3949 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 3950 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3951 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 3952 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3953 3954 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 3955 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 3956 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 3957 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 3958 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 3959 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 3960 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 3961 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 3962 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 3963 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 3964 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 3965 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 3966 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3967 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 3968 3969 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 3970 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 3971 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 3972 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 3973 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 3974 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 3975 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 3976 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 3977 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 3978 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 3979 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 3980 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 3981 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 3982 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3983 3984 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 3985 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 3986 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 3987 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 3988 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 3989 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 3990 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 3991 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 3992 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 3993 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 3994 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 3995 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 3996 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 3997 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 3998 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 3999 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 4000 4001 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 4002 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 4003 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 4004 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 4005 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 4006 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 4007 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 4008 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 4009 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 4010 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 4011 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 4012 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 4013 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 4014 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 4015 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 4016 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 4017 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 4018 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 4019 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 4020 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 4021 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 4022 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 4023 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 4024 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 4025 4026 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 4027 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 4028 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 4029 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 4030 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 4031 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 4032 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 4033 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 4034 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 4035 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 4036 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 4037 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 4038 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 4039 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 4040 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 4041 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 4042 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 4043 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 4044 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 4045 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 4046 4047 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000400) 4048 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 4049 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 4050 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 4051 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 4052 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 4053 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 4054 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 4055 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 4056 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 4057 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 4058 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 4059 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 4060 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 4061 4062 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000404) 4063 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 4064 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 4065 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 4066 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 4067 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 4068 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 4069 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 4070 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 4071 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 4072 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 4073 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 4074 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 4075 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 4076 4077 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000408) 4078 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 4079 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 4080 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 4081 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 4082 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 4083 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 4084 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 4085 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 4086 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 4087 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 4088 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 4089 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 4090 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 4091 4092 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 4093 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 4094 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 4095 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 4096 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 4097 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 4098 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 4099 in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 4100 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 4101 out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 4102 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 4103 out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 4104 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 4105 #define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 4106 4107 #define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00008000) 4108 #define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00008000) 4109 #define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000 4110 4111 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 4112 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 4113 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 4114 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 4115 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 4116 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 4117 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 4118 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 4119 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 4120 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 4121 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 4122 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 4123 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4124 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4125 4126 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 4127 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 4128 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 4129 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 4130 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 4131 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 4132 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 4133 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 4134 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 4135 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 4136 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 4137 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 4138 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 4139 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4140 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 4141 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4142 4143 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 4144 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 4145 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 4146 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 4147 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 4148 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 4149 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 4150 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 4151 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 4152 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 4153 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 4154 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 4155 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 4156 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 4157 4158 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 4159 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 4160 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 4161 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 4162 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 4163 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 4164 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 4165 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 4166 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4167 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4168 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 4169 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4170 4171 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 4172 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 4173 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 4174 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 4175 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 4176 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 4177 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 4178 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 4179 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 4180 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 4181 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 4182 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 4183 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 4184 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 4185 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 4186 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4187 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 4188 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4189 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 4190 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4191 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 4192 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 4193 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 4194 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4195 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 4196 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4197 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 4198 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4199 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 4200 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 4201 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 4202 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4203 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 4204 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4205 4206 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 4207 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 4208 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 4209 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 4210 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 4211 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 4212 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 4213 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 4214 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 4215 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 4216 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 4217 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 4218 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 4219 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 4220 4221 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 4222 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 4223 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 4224 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 4225 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 4226 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 4227 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 4228 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 4229 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 4230 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 4231 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 4232 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 4233 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 4234 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 4235 4236 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 4237 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 4238 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 4239 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 4240 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 4241 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 4242 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 4243 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 4244 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 4245 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 4246 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 4247 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 4248 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4249 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4250 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 4251 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 4252 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 4253 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4254 4255 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 4256 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 4257 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 4258 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 4259 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 4260 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 4261 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 4262 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 4263 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 4264 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 4265 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 4266 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 4267 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 4268 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 4269 4270 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 4271 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 4272 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 4273 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 4274 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 4275 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 4276 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 4277 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 4278 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4279 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4280 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 4281 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 4282 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 4283 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4284 4285 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 4286 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 4287 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 4288 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 4289 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 4290 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 4291 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 4292 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 4293 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 4294 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 4295 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 4296 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 4297 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 4298 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 4299 4300 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 4301 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 4302 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 4303 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 4304 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 4305 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 4306 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 4307 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 4308 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 4309 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 4310 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 4311 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 4312 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 4313 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 4314 4315 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 4316 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 4317 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 4318 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 4319 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 4320 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 4321 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 4322 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 4323 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 4324 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 4325 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 4326 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 4327 4328 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 4329 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 4330 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 4331 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4332 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 4333 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 4334 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 4335 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 4336 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 4337 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 4338 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 4339 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 4340 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4341 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4342 4343 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 4344 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 4345 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 4346 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 4347 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 4348 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 4349 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 4350 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 4351 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 4352 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 4353 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 4354 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 4355 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 4356 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4357 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 4358 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4359 4360 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 4361 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 4362 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 4363 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 4364 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 4365 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 4366 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 4367 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 4368 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 4369 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 4370 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 4371 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 4372 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4373 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 4374 4375 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 4376 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 4377 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 4378 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 4379 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 4380 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 4381 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 4382 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 4383 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 4384 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 4385 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 4386 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 4387 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 4388 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4389 4390 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 4391 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 4392 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 4393 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 4394 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 4395 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 4396 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 4397 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 4398 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 4399 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 4400 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 4401 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 4402 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 4403 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 4404 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 4405 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 4406 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 4407 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 4408 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 4409 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 4410 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 4411 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 4412 4413 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 4414 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 4415 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 4416 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 4417 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 4418 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 4419 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 4420 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 4421 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 4422 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 4423 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 4424 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 4425 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 4426 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 4427 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 4428 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 4429 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 4430 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 4431 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 4432 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 4433 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 4434 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 4435 4436 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 4437 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 4438 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 4439 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 4440 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 4441 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 4442 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 4443 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 4444 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 4445 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 4446 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 4447 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 4448 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 4449 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 4450 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 4451 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 4452 4453 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 4454 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 4455 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 4456 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 4457 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 4458 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 4459 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 4460 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 4461 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 4462 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 4463 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 4464 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 4465 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 4466 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 4467 4468 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 4469 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 4470 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 4471 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 4472 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 4473 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 4474 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 4475 in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 4476 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 4477 out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 4478 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 4479 out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 4480 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 4481 #define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 4482 4483 #define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00009000) 4484 #define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00009000) 4485 #define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000 4486 4487 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000000) 4488 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 4489 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 4490 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 4491 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 4492 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 4493 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 4494 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 4495 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 4496 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 4497 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 4498 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 4499 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4500 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4501 4502 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000004) 4503 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 4504 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 4505 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 4506 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 4507 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 4508 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 4509 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 4510 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 4511 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 4512 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 4513 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 4514 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 4515 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4516 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 4517 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4518 4519 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000008) 4520 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 4521 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 4522 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 4523 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 4524 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 4525 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 4526 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 4527 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 4528 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 4529 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 4530 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 4531 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 4532 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 4533 4534 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 4535 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 4536 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 4537 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 4538 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 4539 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 4540 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 4541 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 4542 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4543 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4544 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 4545 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4546 4547 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000010) 4548 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 4549 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 4550 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 4551 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 4552 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 4553 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 4554 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 4555 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 4556 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 4557 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 4558 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 4559 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 4560 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 4561 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 4562 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4563 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 4564 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4565 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 4566 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4567 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 4568 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 4569 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 4570 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4571 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 4572 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4573 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 4574 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4575 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 4576 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 4577 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 4578 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4579 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 4580 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4581 4582 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 4583 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 4584 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 4585 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 4586 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 4587 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 4588 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 4589 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 4590 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 4591 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 4592 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 4593 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 4594 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 4595 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 4596 4597 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000020) 4598 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 4599 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 4600 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 4601 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 4602 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 4603 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 4604 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 4605 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 4606 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 4607 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 4608 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 4609 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 4610 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 4611 4612 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000030) 4613 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 4614 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 4615 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 4616 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 4617 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 4618 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 4619 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 4620 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 4621 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 4622 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 4623 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 4624 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4625 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4626 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 4627 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 4628 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 4629 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4630 4631 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000034) 4632 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 4633 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 4634 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 4635 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 4636 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 4637 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 4638 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 4639 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 4640 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 4641 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 4642 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 4643 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 4644 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 4645 4646 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000038) 4647 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 4648 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 4649 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 4650 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 4651 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 4652 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 4653 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 4654 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4655 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4656 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 4657 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 4658 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 4659 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4660 4661 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 4662 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 4663 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 4664 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 4665 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 4666 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 4667 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 4668 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 4669 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 4670 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 4671 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 4672 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 4673 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 4674 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 4675 4676 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000040) 4677 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 4678 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 4679 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 4680 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 4681 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 4682 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 4683 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 4684 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 4685 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 4686 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 4687 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 4688 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 4689 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 4690 4691 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000044) 4692 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 4693 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 4694 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 4695 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 4696 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 4697 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 4698 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 4699 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 4700 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 4701 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 4702 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 4703 4704 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000048) 4705 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 4706 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 4707 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4708 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 4709 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 4710 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 4711 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 4712 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 4713 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 4714 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 4715 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 4716 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4717 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4718 4719 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 4720 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 4721 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 4722 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 4723 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 4724 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 4725 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 4726 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 4727 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 4728 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 4729 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 4730 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 4731 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 4732 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4733 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 4734 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4735 4736 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000050) 4737 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 4738 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 4739 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 4740 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 4741 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 4742 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 4743 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 4744 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 4745 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 4746 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 4747 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 4748 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4749 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 4750 4751 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000054) 4752 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 4753 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 4754 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 4755 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 4756 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 4757 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 4758 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 4759 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 4760 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 4761 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 4762 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 4763 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 4764 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4765 4766 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000058) 4767 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 4768 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 4769 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 4770 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 4771 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 4772 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 4773 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 4774 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 4775 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 4776 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 4777 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 4778 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4779 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4780 4781 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 4782 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 4783 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 4784 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 4785 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 4786 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 4787 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 4788 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 4789 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 4790 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 4791 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 4792 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 4793 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 4794 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4795 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 4796 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4797 4798 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000060) 4799 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 4800 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 4801 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 4802 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 4803 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 4804 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 4805 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 4806 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 4807 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 4808 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 4809 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 4810 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 4811 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 4812 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 4813 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 4814 4815 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000064) 4816 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 4817 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 4818 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 4819 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 4820 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 4821 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 4822 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 4823 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4824 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4825 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 4826 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4827 4828 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000068) 4829 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 4830 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 4831 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 4832 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 4833 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 4834 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 4835 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 4836 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 4837 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 4838 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 4839 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 4840 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 4841 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 4842 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 4843 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 4844 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 4845 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4846 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 4847 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4848 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 4849 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4850 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 4851 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 4852 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 4853 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4854 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 4855 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4856 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 4857 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4858 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 4859 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 4860 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 4861 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4862 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 4863 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4864 4865 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 4866 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 4867 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 4868 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 4869 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 4870 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 4871 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 4872 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 4873 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 4874 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 4875 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 4876 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 4877 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4878 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4879 4880 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000070) 4881 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 4882 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 4883 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 4884 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 4885 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 4886 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 4887 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 4888 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 4889 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 4890 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 4891 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 4892 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 4893 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4894 4895 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 4896 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 4897 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 4898 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4899 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 4900 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 4901 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 4902 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 4903 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 4904 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 4905 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 4906 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 4907 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4908 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4909 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 4910 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4911 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 4912 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4913 4914 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000080) 4915 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 4916 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 4917 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4918 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 4919 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 4920 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 4921 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 4922 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4923 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4924 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 4925 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4926 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 4927 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4928 4929 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000084) 4930 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 4931 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 4932 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 4933 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 4934 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 4935 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 4936 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 4937 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 4938 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 4939 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 4940 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 4941 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 4942 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4943 4944 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 4945 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 4946 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 4947 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4948 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 4949 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 4950 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 4951 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 4952 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 4953 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 4954 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 4955 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 4956 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4957 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4958 4959 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 4960 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 4961 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 4962 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 4963 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 4964 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 4965 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 4966 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 4967 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 4968 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 4969 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 4970 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 4971 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 4972 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4973 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 4974 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4975 4976 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 4977 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 4978 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 4979 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 4980 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 4981 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 4982 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 4983 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 4984 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 4985 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 4986 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 4987 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 4988 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4989 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 4990 4991 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 4992 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 4993 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 4994 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 4995 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 4996 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 4997 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 4998 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 4999 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 5000 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 5001 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 5002 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 5003 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 5004 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5005 5006 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 5007 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 5008 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 5009 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 5010 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 5011 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 5012 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 5013 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 5014 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 5015 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 5016 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 5017 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 5018 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 5019 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 5020 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 5021 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 5022 5023 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 5024 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 5025 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 5026 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 5027 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 5028 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 5029 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 5030 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 5031 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 5032 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 5033 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 5034 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 5035 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 5036 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 5037 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 5038 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 5039 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 5040 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 5041 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 5042 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 5043 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 5044 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 5045 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 5046 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 5047 5048 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 5049 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 5050 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 5051 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 5052 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 5053 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 5054 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 5055 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 5056 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 5057 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 5058 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 5059 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 5060 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 5061 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 5062 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 5063 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 5064 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 5065 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 5066 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 5067 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 5068 5069 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000400) 5070 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 5071 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 5072 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 5073 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 5074 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 5075 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 5076 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 5077 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 5078 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 5079 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 5080 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 5081 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 5082 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 5083 5084 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000404) 5085 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 5086 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 5087 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 5088 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 5089 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 5090 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 5091 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 5092 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 5093 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 5094 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 5095 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 5096 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 5097 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 5098 5099 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000408) 5100 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 5101 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 5102 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 5103 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 5104 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 5105 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 5106 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 5107 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 5108 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 5109 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 5110 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 5111 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 5112 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 5113 5114 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 5115 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 5116 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 5117 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 5118 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 5119 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 5120 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 5121 in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 5122 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 5123 out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 5124 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 5125 out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 5126 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 5127 #define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 5128 5129 #define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000a000) 5130 #define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000a000) 5131 #define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000 5132 5133 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 5134 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 5135 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 5136 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 5137 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 5138 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 5139 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 5140 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 5141 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 5142 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 5143 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 5144 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 5145 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5146 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5147 5148 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 5149 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 5150 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 5151 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 5152 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 5153 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 5154 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 5155 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 5156 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 5157 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 5158 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 5159 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 5160 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 5161 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5162 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 5163 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5164 5165 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 5166 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 5167 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 5168 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 5169 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 5170 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 5171 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 5172 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 5173 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 5174 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 5175 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 5176 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 5177 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 5178 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 5179 5180 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 5181 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 5182 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 5183 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 5184 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 5185 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 5186 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 5187 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 5188 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5189 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5190 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 5191 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5192 5193 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 5194 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 5195 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 5196 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 5197 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 5198 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 5199 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 5200 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 5201 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 5202 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 5203 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 5204 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 5205 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 5206 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 5207 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 5208 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5209 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 5210 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5211 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 5212 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5213 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 5214 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 5215 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 5216 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5217 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 5218 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5219 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 5220 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5221 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 5222 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 5223 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 5224 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5225 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 5226 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5227 5228 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 5229 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 5230 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 5231 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 5232 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 5233 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 5234 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 5235 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 5236 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 5237 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 5238 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 5239 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 5240 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 5241 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 5242 5243 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 5244 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 5245 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 5246 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 5247 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 5248 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 5249 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 5250 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 5251 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 5252 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 5253 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 5254 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 5255 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 5256 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 5257 5258 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 5259 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 5260 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 5261 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 5262 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 5263 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 5264 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 5265 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 5266 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 5267 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 5268 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 5269 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 5270 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5271 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5272 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 5273 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 5274 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 5275 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5276 5277 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 5278 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 5279 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 5280 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 5281 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 5282 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 5283 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 5284 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 5285 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 5286 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 5287 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 5288 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 5289 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 5290 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 5291 5292 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 5293 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 5294 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 5295 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 5296 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 5297 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 5298 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 5299 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 5300 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5301 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5302 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 5303 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 5304 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 5305 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5306 5307 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 5308 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 5309 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 5310 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 5311 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 5312 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 5313 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 5314 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 5315 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 5316 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 5317 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 5318 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 5319 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 5320 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 5321 5322 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 5323 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 5324 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 5325 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 5326 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 5327 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 5328 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 5329 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 5330 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 5331 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 5332 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 5333 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 5334 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 5335 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 5336 5337 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 5338 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 5339 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 5340 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 5341 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 5342 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 5343 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 5344 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 5345 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 5346 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 5347 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 5348 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 5349 5350 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 5351 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 5352 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 5353 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5354 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 5355 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 5356 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 5357 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 5358 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 5359 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 5360 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 5361 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 5362 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5363 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5364 5365 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 5366 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 5367 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 5368 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 5369 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 5370 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 5371 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 5372 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 5373 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 5374 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 5375 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 5376 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 5377 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 5378 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5379 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 5380 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5381 5382 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 5383 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 5384 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 5385 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 5386 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 5387 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 5388 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 5389 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 5390 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 5391 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 5392 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 5393 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 5394 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5395 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 5396 5397 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 5398 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 5399 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 5400 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 5401 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 5402 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 5403 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 5404 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 5405 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 5406 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 5407 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 5408 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 5409 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 5410 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5411 5412 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 5413 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 5414 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 5415 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 5416 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 5417 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 5418 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 5419 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 5420 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 5421 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 5422 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 5423 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 5424 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 5425 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 5426 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 5427 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 5428 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 5429 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 5430 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 5431 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 5432 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 5433 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 5434 5435 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 5436 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 5437 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 5438 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 5439 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 5440 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 5441 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 5442 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 5443 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 5444 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 5445 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 5446 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 5447 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 5448 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 5449 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 5450 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 5451 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 5452 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 5453 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 5454 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 5455 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 5456 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 5457 5458 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 5459 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 5460 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 5461 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 5462 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 5463 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 5464 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 5465 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 5466 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 5467 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 5468 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 5469 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 5470 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 5471 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 5472 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 5473 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 5474 5475 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 5476 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 5477 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 5478 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 5479 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 5480 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 5481 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 5482 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 5483 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 5484 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 5485 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 5486 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 5487 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 5488 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 5489 5490 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 5491 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 5492 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 5493 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 5494 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 5495 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 5496 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 5497 in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 5498 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 5499 out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 5500 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 5501 out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 5502 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 5503 #define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 5504 5505 #define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000b000) 5506 #define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000b000) 5507 #define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000 5508 5509 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000000) 5510 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 5511 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 5512 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 5513 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 5514 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 5515 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 5516 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 5517 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 5518 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 5519 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 5520 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 5521 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5522 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5523 5524 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000004) 5525 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 5526 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 5527 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 5528 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 5529 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 5530 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 5531 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 5532 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 5533 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 5534 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 5535 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 5536 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 5537 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5538 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 5539 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5540 5541 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000008) 5542 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 5543 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 5544 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 5545 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 5546 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 5547 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 5548 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 5549 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 5550 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 5551 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 5552 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 5553 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 5554 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 5555 5556 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 5557 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 5558 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 5559 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 5560 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 5561 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 5562 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 5563 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 5564 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5565 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5566 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 5567 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5568 5569 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000010) 5570 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 5571 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 5572 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 5573 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 5574 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 5575 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 5576 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 5577 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 5578 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 5579 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 5580 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 5581 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 5582 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 5583 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 5584 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5585 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 5586 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5587 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 5588 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5589 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 5590 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 5591 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 5592 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5593 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 5594 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5595 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 5596 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5597 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 5598 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 5599 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 5600 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5601 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 5602 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5603 5604 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 5605 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 5606 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 5607 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 5608 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 5609 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 5610 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 5611 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 5612 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 5613 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 5614 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 5615 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 5616 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 5617 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 5618 5619 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000020) 5620 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 5621 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 5622 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 5623 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 5624 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 5625 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 5626 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 5627 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 5628 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 5629 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 5630 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 5631 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 5632 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 5633 5634 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000030) 5635 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 5636 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 5637 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 5638 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 5639 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 5640 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 5641 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 5642 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 5643 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 5644 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 5645 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 5646 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5647 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5648 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 5649 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 5650 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 5651 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5652 5653 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000034) 5654 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 5655 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 5656 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 5657 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 5658 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 5659 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 5660 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 5661 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 5662 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 5663 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 5664 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 5665 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 5666 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 5667 5668 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000038) 5669 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 5670 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 5671 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 5672 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 5673 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 5674 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 5675 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 5676 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5677 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5678 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 5679 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 5680 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 5681 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5682 5683 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 5684 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 5685 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 5686 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 5687 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 5688 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 5689 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 5690 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 5691 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 5692 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 5693 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 5694 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 5695 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 5696 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 5697 5698 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000040) 5699 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 5700 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 5701 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 5702 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 5703 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 5704 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 5705 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 5706 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 5707 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 5708 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 5709 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 5710 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 5711 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 5712 5713 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000044) 5714 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 5715 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 5716 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 5717 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 5718 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 5719 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 5720 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 5721 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 5722 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 5723 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 5724 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 5725 5726 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000048) 5727 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 5728 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 5729 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5730 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 5731 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 5732 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 5733 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 5734 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 5735 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 5736 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 5737 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 5738 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5739 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5740 5741 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 5742 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 5743 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 5744 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 5745 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 5746 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 5747 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 5748 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 5749 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 5750 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 5751 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 5752 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 5753 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 5754 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5755 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 5756 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5757 5758 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000050) 5759 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 5760 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 5761 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 5762 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 5763 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 5764 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 5765 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 5766 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 5767 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 5768 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 5769 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 5770 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5771 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 5772 5773 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000054) 5774 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 5775 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 5776 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 5777 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 5778 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 5779 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 5780 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 5781 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 5782 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 5783 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 5784 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 5785 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 5786 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5787 5788 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000058) 5789 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 5790 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 5791 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 5792 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 5793 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 5794 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 5795 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 5796 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 5797 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 5798 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 5799 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 5800 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5801 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5802 5803 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 5804 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 5805 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 5806 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 5807 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 5808 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 5809 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 5810 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 5811 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 5812 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 5813 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 5814 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 5815 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 5816 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5817 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 5818 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5819 5820 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000060) 5821 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 5822 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 5823 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 5824 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 5825 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 5826 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 5827 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 5828 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 5829 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 5830 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 5831 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 5832 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 5833 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 5834 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 5835 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 5836 5837 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000064) 5838 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 5839 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 5840 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 5841 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 5842 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 5843 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 5844 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 5845 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5846 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5847 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 5848 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5849 5850 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000068) 5851 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 5852 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 5853 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 5854 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 5855 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 5856 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 5857 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 5858 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 5859 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 5860 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 5861 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 5862 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 5863 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 5864 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 5865 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 5866 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 5867 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5868 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 5869 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5870 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 5871 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5872 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 5873 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 5874 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 5875 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5876 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 5877 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5878 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 5879 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5880 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 5881 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 5882 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 5883 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5884 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 5885 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5886 5887 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 5888 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 5889 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 5890 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 5891 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 5892 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 5893 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 5894 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 5895 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 5896 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 5897 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 5898 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 5899 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5900 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5901 5902 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000070) 5903 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 5904 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 5905 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 5906 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 5907 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 5908 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 5909 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 5910 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 5911 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 5912 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 5913 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 5914 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 5915 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5916 5917 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 5918 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 5919 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 5920 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5921 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 5922 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 5923 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 5924 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 5925 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 5926 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 5927 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 5928 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 5929 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5930 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5931 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 5932 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5933 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 5934 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5935 5936 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000080) 5937 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 5938 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 5939 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5940 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 5941 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 5942 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 5943 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 5944 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5945 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5946 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 5947 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5948 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 5949 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5950 5951 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000084) 5952 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 5953 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 5954 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 5955 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 5956 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 5957 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 5958 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 5959 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 5960 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 5961 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 5962 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 5963 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 5964 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5965 5966 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 5967 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 5968 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 5969 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5970 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 5971 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 5972 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 5973 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 5974 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 5975 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 5976 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 5977 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 5978 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5979 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5980 5981 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 5982 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 5983 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 5984 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 5985 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 5986 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 5987 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 5988 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 5989 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 5990 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 5991 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 5992 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 5993 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 5994 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5995 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 5996 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5997 5998 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 5999 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 6000 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 6001 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 6002 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 6003 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 6004 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 6005 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 6006 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 6007 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 6008 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 6009 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 6010 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6011 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 6012 6013 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 6014 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 6015 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 6016 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 6017 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 6018 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 6019 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 6020 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 6021 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 6022 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 6023 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 6024 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 6025 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 6026 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6027 6028 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 6029 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 6030 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 6031 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 6032 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 6033 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 6034 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 6035 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 6036 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 6037 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 6038 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 6039 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 6040 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 6041 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 6042 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 6043 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 6044 6045 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 6046 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 6047 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 6048 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 6049 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 6050 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 6051 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 6052 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 6053 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 6054 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 6055 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 6056 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 6057 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 6058 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 6059 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 6060 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 6061 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 6062 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 6063 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 6064 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 6065 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 6066 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 6067 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 6068 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 6069 6070 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 6071 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 6072 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 6073 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 6074 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 6075 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 6076 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 6077 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 6078 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 6079 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 6080 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 6081 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 6082 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 6083 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 6084 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 6085 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 6086 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 6087 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 6088 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 6089 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 6090 6091 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000400) 6092 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 6093 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 6094 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 6095 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 6096 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 6097 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 6098 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 6099 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 6100 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 6101 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 6102 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 6103 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 6104 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 6105 6106 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000404) 6107 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 6108 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 6109 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 6110 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 6111 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 6112 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 6113 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 6114 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 6115 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 6116 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 6117 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 6118 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 6119 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 6120 6121 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000408) 6122 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 6123 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 6124 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 6125 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 6126 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 6127 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 6128 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 6129 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 6130 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 6131 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 6132 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 6133 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 6134 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 6135 6136 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 6137 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 6138 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 6139 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 6140 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 6141 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 6142 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 6143 in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 6144 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 6145 out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 6146 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 6147 out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 6148 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 6149 #define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 6150 6151 #define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000c000) 6152 #define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000c000) 6153 #define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000 6154 6155 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 6156 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 6157 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 6158 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 6159 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 6160 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 6161 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 6162 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 6163 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 6164 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 6165 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 6166 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 6167 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 6168 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 6169 6170 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 6171 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 6172 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 6173 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 6174 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 6175 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 6176 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 6177 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 6178 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 6179 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 6180 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 6181 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 6182 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 6183 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 6184 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 6185 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 6186 6187 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 6188 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 6189 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 6190 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 6191 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 6192 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 6193 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 6194 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 6195 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 6196 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 6197 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 6198 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 6199 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 6200 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 6201 6202 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 6203 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 6204 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 6205 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 6206 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 6207 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 6208 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 6209 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 6210 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 6211 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 6212 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 6213 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 6214 6215 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 6216 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 6217 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 6218 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 6219 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 6220 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 6221 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 6222 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 6223 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 6224 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 6225 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 6226 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 6227 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 6228 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 6229 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 6230 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 6231 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 6232 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 6233 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 6234 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 6235 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 6236 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 6237 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 6238 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 6239 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 6240 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 6241 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 6242 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 6243 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 6244 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 6245 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 6246 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 6247 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 6248 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 6249 6250 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 6251 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 6252 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 6253 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 6254 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 6255 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 6256 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 6257 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 6258 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 6259 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 6260 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 6261 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 6262 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 6263 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 6264 6265 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 6266 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 6267 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 6268 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 6269 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 6270 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 6271 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 6272 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 6273 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 6274 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 6275 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 6276 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 6277 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 6278 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 6279 6280 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 6281 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 6282 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 6283 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 6284 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 6285 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 6286 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 6287 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 6288 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 6289 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 6290 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 6291 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 6292 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 6293 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 6294 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 6295 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 6296 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 6297 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 6298 6299 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 6300 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 6301 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 6302 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 6303 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 6304 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 6305 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 6306 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 6307 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 6308 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 6309 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 6310 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 6311 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 6312 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 6313 6314 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 6315 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 6316 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 6317 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 6318 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 6319 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 6320 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 6321 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 6322 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 6323 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 6324 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 6325 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 6326 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 6327 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 6328 6329 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 6330 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 6331 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 6332 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 6333 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 6334 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 6335 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 6336 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 6337 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 6338 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 6339 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 6340 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 6341 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 6342 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 6343 6344 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 6345 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 6346 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 6347 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 6348 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 6349 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 6350 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 6351 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 6352 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 6353 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 6354 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 6355 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 6356 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 6357 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 6358 6359 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 6360 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 6361 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 6362 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 6363 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 6364 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 6365 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 6366 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 6367 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 6368 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 6369 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 6370 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 6371 6372 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 6373 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 6374 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 6375 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 6376 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 6377 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 6378 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 6379 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 6380 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 6381 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 6382 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 6383 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 6384 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 6385 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 6386 6387 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 6388 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 6389 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 6390 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 6391 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 6392 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 6393 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 6394 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 6395 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 6396 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 6397 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 6398 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 6399 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 6400 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 6401 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 6402 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 6403 6404 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 6405 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 6406 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 6407 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 6408 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 6409 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 6410 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 6411 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 6412 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 6413 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 6414 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 6415 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 6416 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6417 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 6418 6419 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 6420 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 6421 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 6422 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 6423 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 6424 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 6425 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 6426 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 6427 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 6428 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 6429 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 6430 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 6431 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 6432 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6433 6434 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 6435 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 6436 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 6437 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 6438 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 6439 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 6440 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 6441 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 6442 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 6443 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 6444 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 6445 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 6446 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 6447 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 6448 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 6449 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 6450 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 6451 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 6452 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 6453 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 6454 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 6455 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 6456 6457 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 6458 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 6459 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 6460 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 6461 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 6462 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 6463 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 6464 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 6465 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 6466 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 6467 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 6468 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 6469 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 6470 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 6471 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 6472 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 6473 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 6474 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 6475 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 6476 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 6477 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 6478 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 6479 6480 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 6481 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 6482 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 6483 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 6484 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 6485 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 6486 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 6487 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 6488 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 6489 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 6490 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 6491 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 6492 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 6493 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 6494 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 6495 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 6496 6497 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 6498 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 6499 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 6500 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 6501 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 6502 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 6503 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 6504 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 6505 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 6506 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 6507 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 6508 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 6509 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 6510 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 6511 6512 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 6513 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 6514 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 6515 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 6516 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 6517 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 6518 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 6519 in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 6520 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 6521 out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 6522 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 6523 out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 6524 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 6525 #define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 6526 6527 #define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000d000) 6528 #define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000d000) 6529 #define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000 6530 6531 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000000) 6532 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 6533 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 6534 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 6535 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 6536 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 6537 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 6538 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 6539 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 6540 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 6541 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 6542 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 6543 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 6544 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 6545 6546 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000004) 6547 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 6548 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 6549 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 6550 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 6551 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 6552 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 6553 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 6554 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 6555 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 6556 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 6557 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 6558 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 6559 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 6560 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 6561 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 6562 6563 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000008) 6564 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 6565 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 6566 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 6567 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 6568 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 6569 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 6570 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 6571 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 6572 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 6573 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 6574 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 6575 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 6576 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 6577 6578 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 6579 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 6580 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 6581 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 6582 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 6583 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 6584 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 6585 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 6586 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 6587 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 6588 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 6589 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 6590 6591 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000010) 6592 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 6593 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 6594 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 6595 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 6596 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 6597 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 6598 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 6599 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 6600 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 6601 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 6602 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 6603 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 6604 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 6605 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 6606 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 6607 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 6608 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 6609 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 6610 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 6611 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 6612 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 6613 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 6614 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 6615 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 6616 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 6617 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 6618 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 6619 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 6620 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 6621 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 6622 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 6623 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 6624 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 6625 6626 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 6627 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 6628 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 6629 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 6630 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 6631 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 6632 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 6633 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 6634 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 6635 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 6636 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 6637 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 6638 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 6639 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 6640 6641 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000020) 6642 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 6643 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 6644 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 6645 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 6646 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 6647 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 6648 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 6649 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 6650 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 6651 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 6652 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 6653 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 6654 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 6655 6656 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000030) 6657 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 6658 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 6659 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 6660 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 6661 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 6662 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 6663 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 6664 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 6665 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 6666 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 6667 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 6668 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 6669 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 6670 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 6671 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 6672 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 6673 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 6674 6675 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000034) 6676 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 6677 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 6678 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 6679 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 6680 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 6681 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 6682 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 6683 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 6684 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 6685 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 6686 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 6687 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 6688 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 6689 6690 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000038) 6691 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 6692 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 6693 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 6694 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 6695 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 6696 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 6697 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 6698 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 6699 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 6700 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 6701 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 6702 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 6703 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 6704 6705 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 6706 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 6707 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 6708 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 6709 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 6710 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 6711 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 6712 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 6713 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 6714 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 6715 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 6716 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 6717 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 6718 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 6719 6720 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000040) 6721 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 6722 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 6723 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 6724 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 6725 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 6726 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 6727 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 6728 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 6729 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 6730 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 6731 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 6732 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 6733 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 6734 6735 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000044) 6736 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 6737 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 6738 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 6739 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 6740 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 6741 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 6742 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 6743 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 6744 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 6745 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 6746 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 6747 6748 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000048) 6749 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 6750 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 6751 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 6752 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 6753 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 6754 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 6755 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 6756 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 6757 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 6758 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 6759 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 6760 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 6761 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 6762 6763 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 6764 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 6765 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 6766 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 6767 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 6768 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 6769 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 6770 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 6771 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 6772 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 6773 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 6774 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 6775 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 6776 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 6777 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 6778 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 6779 6780 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000050) 6781 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 6782 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 6783 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 6784 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 6785 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 6786 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 6787 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 6788 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 6789 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 6790 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 6791 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 6792 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6793 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 6794 6795 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000054) 6796 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 6797 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 6798 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 6799 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 6800 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 6801 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 6802 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 6803 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 6804 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 6805 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 6806 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 6807 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 6808 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6809 6810 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000058) 6811 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 6812 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 6813 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 6814 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 6815 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 6816 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 6817 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 6818 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 6819 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 6820 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 6821 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 6822 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 6823 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 6824 6825 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 6826 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 6827 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 6828 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 6829 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 6830 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 6831 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 6832 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 6833 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 6834 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 6835 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 6836 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 6837 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 6838 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 6839 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 6840 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 6841 6842 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000060) 6843 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 6844 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 6845 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 6846 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 6847 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 6848 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 6849 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 6850 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 6851 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 6852 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 6853 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 6854 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 6855 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 6856 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 6857 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 6858 6859 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000064) 6860 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 6861 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 6862 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 6863 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 6864 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 6865 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 6866 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 6867 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 6868 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 6869 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 6870 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 6871 6872 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000068) 6873 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 6874 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 6875 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 6876 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 6877 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 6878 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 6879 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 6880 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 6881 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 6882 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 6883 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 6884 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 6885 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 6886 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 6887 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 6888 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 6889 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 6890 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 6891 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 6892 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 6893 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 6894 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 6895 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 6896 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 6897 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 6898 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 6899 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 6900 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 6901 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 6902 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 6903 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 6904 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 6905 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 6906 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 6907 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 6908 6909 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 6910 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 6911 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 6912 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 6913 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 6914 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 6915 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 6916 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 6917 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 6918 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 6919 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 6920 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 6921 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 6922 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 6923 6924 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000070) 6925 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 6926 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 6927 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 6928 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 6929 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 6930 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 6931 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 6932 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 6933 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 6934 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 6935 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 6936 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 6937 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 6938 6939 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 6940 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 6941 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 6942 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 6943 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 6944 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 6945 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 6946 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 6947 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 6948 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 6949 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 6950 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 6951 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 6952 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 6953 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 6954 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 6955 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 6956 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 6957 6958 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000080) 6959 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 6960 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 6961 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 6962 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 6963 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 6964 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 6965 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 6966 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 6967 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 6968 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 6969 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 6970 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 6971 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 6972 6973 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000084) 6974 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 6975 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 6976 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 6977 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 6978 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 6979 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 6980 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 6981 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 6982 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 6983 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 6984 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 6985 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 6986 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 6987 6988 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 6989 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 6990 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 6991 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 6992 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 6993 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 6994 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 6995 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 6996 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 6997 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 6998 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 6999 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 7000 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 7001 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 7002 7003 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 7004 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 7005 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 7006 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 7007 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 7008 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 7009 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 7010 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 7011 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 7012 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 7013 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 7014 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 7015 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 7016 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 7017 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 7018 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 7019 7020 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 7021 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 7022 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 7023 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 7024 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 7025 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 7026 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 7027 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 7028 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 7029 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 7030 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 7031 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 7032 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 7033 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 7034 7035 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 7036 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 7037 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 7038 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 7039 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 7040 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 7041 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 7042 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 7043 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 7044 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 7045 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 7046 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 7047 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 7048 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 7049 7050 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 7051 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 7052 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 7053 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 7054 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 7055 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 7056 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 7057 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 7058 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 7059 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 7060 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 7061 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 7062 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 7063 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 7064 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 7065 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 7066 7067 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 7068 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 7069 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 7070 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 7071 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 7072 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 7073 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 7074 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 7075 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 7076 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 7077 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 7078 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 7079 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 7080 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 7081 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 7082 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 7083 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 7084 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 7085 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 7086 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 7087 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 7088 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 7089 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 7090 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 7091 7092 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 7093 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 7094 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 7095 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 7096 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 7097 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 7098 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 7099 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 7100 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 7101 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 7102 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 7103 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 7104 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 7105 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 7106 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 7107 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 7108 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 7109 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 7110 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 7111 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 7112 7113 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000400) 7114 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 7115 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 7116 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 7117 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 7118 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 7119 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 7120 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 7121 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 7122 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 7123 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 7124 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 7125 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 7126 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 7127 7128 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000404) 7129 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 7130 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 7131 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 7132 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 7133 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 7134 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 7135 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 7136 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 7137 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 7138 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 7139 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 7140 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 7141 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 7142 7143 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000408) 7144 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 7145 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 7146 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 7147 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 7148 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 7149 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 7150 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 7151 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 7152 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 7153 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 7154 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 7155 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 7156 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 7157 7158 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 7159 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 7160 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 7161 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 7162 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 7163 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 7164 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 7165 in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 7166 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 7167 out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 7168 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 7169 out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 7170 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 7171 #define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 7172 7173 #define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000e000) 7174 #define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000e000) 7175 #define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000 7176 7177 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 7178 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 7179 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 7180 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 7181 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 7182 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 7183 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 7184 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 7185 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 7186 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 7187 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 7188 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 7189 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 7190 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 7191 7192 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 7193 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 7194 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 7195 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 7196 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 7197 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 7198 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 7199 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 7200 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 7201 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 7202 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 7203 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 7204 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 7205 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 7206 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 7207 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 7208 7209 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 7210 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 7211 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 7212 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 7213 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 7214 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 7215 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 7216 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 7217 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 7218 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 7219 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 7220 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 7221 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 7222 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 7223 7224 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 7225 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 7226 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 7227 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 7228 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 7229 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 7230 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 7231 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 7232 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 7233 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 7234 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 7235 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 7236 7237 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 7238 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 7239 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 7240 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 7241 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 7242 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 7243 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 7244 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 7245 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 7246 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 7247 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 7248 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 7249 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 7250 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 7251 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 7252 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 7253 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 7254 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 7255 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 7256 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 7257 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 7258 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 7259 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 7260 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 7261 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 7262 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 7263 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 7264 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 7265 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 7266 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 7267 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 7268 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 7269 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 7270 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 7271 7272 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 7273 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 7274 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 7275 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 7276 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 7277 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 7278 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 7279 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 7280 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 7281 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 7282 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 7283 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 7284 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 7285 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 7286 7287 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 7288 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 7289 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 7290 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 7291 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 7292 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 7293 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 7294 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 7295 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 7296 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 7297 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 7298 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 7299 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 7300 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 7301 7302 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 7303 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 7304 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 7305 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 7306 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 7307 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 7308 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 7309 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 7310 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 7311 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 7312 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 7313 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 7314 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 7315 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 7316 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 7317 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 7318 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 7319 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 7320 7321 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 7322 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 7323 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 7324 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 7325 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 7326 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 7327 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 7328 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 7329 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 7330 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 7331 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 7332 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 7333 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 7334 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 7335 7336 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 7337 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 7338 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 7339 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 7340 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 7341 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 7342 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 7343 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 7344 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 7345 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 7346 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 7347 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 7348 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 7349 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 7350 7351 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 7352 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 7353 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 7354 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 7355 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 7356 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 7357 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 7358 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 7359 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 7360 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 7361 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 7362 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 7363 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 7364 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 7365 7366 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 7367 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 7368 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 7369 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 7370 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 7371 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 7372 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 7373 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 7374 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 7375 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 7376 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 7377 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 7378 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 7379 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 7380 7381 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 7382 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 7383 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 7384 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 7385 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 7386 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 7387 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 7388 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 7389 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 7390 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 7391 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 7392 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 7393 7394 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 7395 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 7396 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 7397 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 7398 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 7399 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 7400 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 7401 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 7402 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 7403 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 7404 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 7405 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 7406 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 7407 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 7408 7409 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 7410 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 7411 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 7412 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 7413 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 7414 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 7415 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 7416 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 7417 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 7418 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 7419 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 7420 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 7421 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 7422 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 7423 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 7424 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 7425 7426 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 7427 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 7428 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 7429 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 7430 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 7431 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 7432 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 7433 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 7434 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 7435 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 7436 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 7437 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 7438 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 7439 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 7440 7441 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 7442 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 7443 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 7444 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 7445 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 7446 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 7447 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 7448 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 7449 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 7450 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 7451 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 7452 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 7453 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 7454 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 7455 7456 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 7457 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 7458 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 7459 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 7460 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 7461 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 7462 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 7463 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 7464 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 7465 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 7466 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 7467 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 7468 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 7469 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 7470 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 7471 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 7472 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 7473 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 7474 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 7475 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 7476 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 7477 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 7478 7479 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 7480 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 7481 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 7482 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 7483 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 7484 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 7485 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 7486 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 7487 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 7488 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 7489 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 7490 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 7491 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 7492 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 7493 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 7494 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 7495 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 7496 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 7497 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 7498 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 7499 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 7500 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 7501 7502 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 7503 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 7504 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 7505 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 7506 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 7507 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 7508 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 7509 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 7510 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 7511 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 7512 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 7513 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 7514 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 7515 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 7516 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 7517 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 7518 7519 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 7520 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 7521 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 7522 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 7523 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 7524 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 7525 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 7526 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 7527 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 7528 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 7529 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 7530 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 7531 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 7532 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 7533 7534 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 7535 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 7536 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 7537 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 7538 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 7539 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 7540 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 7541 in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 7542 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 7543 out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 7544 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 7545 out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 7546 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 7547 #define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 7548 7549 #define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000f000) 7550 #define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000f000) 7551 #define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000 7552 7553 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000000) 7554 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 7555 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 7556 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 7557 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 7558 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 7559 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 7560 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 7561 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 7562 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 7563 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 7564 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 7565 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 7566 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 7567 7568 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000004) 7569 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 7570 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 7571 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 7572 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 7573 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 7574 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 7575 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 7576 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 7577 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 7578 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 7579 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 7580 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 7581 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 7582 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 7583 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 7584 7585 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000008) 7586 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 7587 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 7588 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 7589 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 7590 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 7591 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 7592 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 7593 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 7594 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 7595 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 7596 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 7597 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 7598 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 7599 7600 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 7601 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 7602 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 7603 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 7604 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 7605 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 7606 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 7607 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 7608 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 7609 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 7610 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 7611 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 7612 7613 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000010) 7614 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 7615 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 7616 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 7617 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 7618 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 7619 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 7620 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 7621 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 7622 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 7623 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 7624 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 7625 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 7626 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 7627 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 7628 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 7629 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 7630 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 7631 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 7632 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 7633 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 7634 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 7635 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 7636 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 7637 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 7638 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 7639 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 7640 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 7641 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 7642 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 7643 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 7644 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 7645 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 7646 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 7647 7648 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 7649 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 7650 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 7651 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 7652 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 7653 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 7654 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 7655 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 7656 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 7657 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 7658 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 7659 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 7660 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 7661 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 7662 7663 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000020) 7664 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 7665 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 7666 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 7667 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 7668 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 7669 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 7670 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 7671 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 7672 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 7673 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 7674 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 7675 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 7676 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 7677 7678 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000030) 7679 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 7680 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 7681 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 7682 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 7683 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 7684 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 7685 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 7686 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 7687 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 7688 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 7689 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 7690 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 7691 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 7692 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 7693 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 7694 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 7695 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 7696 7697 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000034) 7698 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 7699 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 7700 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 7701 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 7702 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 7703 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 7704 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 7705 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 7706 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 7707 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 7708 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 7709 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 7710 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 7711 7712 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000038) 7713 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 7714 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 7715 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 7716 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 7717 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 7718 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 7719 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 7720 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 7721 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 7722 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 7723 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 7724 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 7725 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 7726 7727 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 7728 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 7729 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 7730 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 7731 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 7732 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 7733 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 7734 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 7735 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 7736 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 7737 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 7738 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 7739 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 7740 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 7741 7742 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000040) 7743 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 7744 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 7745 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 7746 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 7747 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 7748 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 7749 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 7750 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 7751 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 7752 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 7753 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 7754 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 7755 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 7756 7757 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000044) 7758 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 7759 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 7760 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 7761 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 7762 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 7763 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 7764 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 7765 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 7766 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 7767 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 7768 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 7769 7770 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000048) 7771 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 7772 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 7773 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 7774 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 7775 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 7776 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 7777 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 7778 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 7779 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 7780 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 7781 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 7782 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 7783 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 7784 7785 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 7786 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 7787 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 7788 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 7789 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 7790 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 7791 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 7792 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 7793 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 7794 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 7795 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 7796 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 7797 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 7798 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 7799 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 7800 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 7801 7802 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000050) 7803 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 7804 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 7805 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 7806 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 7807 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 7808 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 7809 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 7810 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 7811 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 7812 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 7813 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 7814 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 7815 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 7816 7817 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000054) 7818 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 7819 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 7820 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 7821 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 7822 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 7823 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 7824 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 7825 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 7826 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 7827 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 7828 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 7829 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 7830 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 7831 7832 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000058) 7833 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 7834 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 7835 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 7836 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 7837 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 7838 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 7839 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 7840 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 7841 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 7842 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 7843 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 7844 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 7845 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 7846 7847 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 7848 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 7849 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 7850 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 7851 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 7852 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 7853 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 7854 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 7855 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 7856 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 7857 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 7858 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 7859 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 7860 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 7861 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 7862 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 7863 7864 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000060) 7865 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 7866 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 7867 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 7868 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 7869 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 7870 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 7871 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 7872 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 7873 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 7874 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 7875 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 7876 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 7877 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 7878 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 7879 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 7880 7881 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000064) 7882 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 7883 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 7884 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 7885 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 7886 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 7887 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 7888 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 7889 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 7890 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 7891 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 7892 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 7893 7894 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000068) 7895 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 7896 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 7897 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 7898 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 7899 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 7900 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 7901 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 7902 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 7903 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 7904 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 7905 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 7906 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 7907 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 7908 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 7909 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 7910 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 7911 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 7912 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 7913 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 7914 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 7915 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 7916 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 7917 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 7918 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 7919 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 7920 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 7921 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 7922 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 7923 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 7924 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 7925 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 7926 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 7927 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 7928 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 7929 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 7930 7931 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 7932 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 7933 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 7934 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 7935 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 7936 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 7937 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 7938 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 7939 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 7940 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 7941 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 7942 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 7943 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 7944 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 7945 7946 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000070) 7947 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 7948 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 7949 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 7950 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 7951 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 7952 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 7953 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 7954 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 7955 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 7956 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 7957 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 7958 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 7959 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 7960 7961 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 7962 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 7963 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 7964 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 7965 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 7966 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 7967 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 7968 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 7969 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 7970 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 7971 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 7972 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 7973 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 7974 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 7975 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 7976 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 7977 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 7978 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 7979 7980 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000080) 7981 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 7982 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 7983 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 7984 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 7985 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 7986 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 7987 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 7988 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 7989 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 7990 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 7991 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 7992 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 7993 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 7994 7995 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000084) 7996 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 7997 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 7998 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 7999 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 8000 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 8001 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 8002 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 8003 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 8004 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 8005 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 8006 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 8007 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 8008 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 8009 8010 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 8011 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 8012 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 8013 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 8014 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 8015 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 8016 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 8017 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 8018 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 8019 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 8020 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 8021 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 8022 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 8023 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 8024 8025 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 8026 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 8027 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 8028 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 8029 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 8030 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 8031 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 8032 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 8033 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 8034 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 8035 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 8036 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 8037 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 8038 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 8039 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 8040 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 8041 8042 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 8043 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 8044 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 8045 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 8046 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 8047 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 8048 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 8049 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 8050 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 8051 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 8052 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 8053 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 8054 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 8055 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 8056 8057 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 8058 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 8059 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 8060 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 8061 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 8062 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 8063 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 8064 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 8065 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 8066 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 8067 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 8068 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 8069 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 8070 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 8071 8072 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 8073 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 8074 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 8075 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 8076 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 8077 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 8078 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 8079 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 8080 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 8081 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 8082 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 8083 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 8084 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 8085 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 8086 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 8087 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 8088 8089 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 8090 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 8091 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 8092 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 8093 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 8094 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 8095 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 8096 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 8097 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 8098 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 8099 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 8100 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 8101 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 8102 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 8103 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 8104 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 8105 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 8106 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 8107 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 8108 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 8109 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 8110 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 8111 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 8112 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 8113 8114 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 8115 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 8116 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 8117 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 8118 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 8119 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 8120 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 8121 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 8122 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 8123 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 8124 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 8125 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 8126 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 8127 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 8128 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 8129 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 8130 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 8131 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 8132 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 8133 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 8134 8135 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000400) 8136 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 8137 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 8138 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 8139 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 8140 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 8141 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 8142 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 8143 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 8144 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 8145 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 8146 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 8147 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 8148 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 8149 8150 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000404) 8151 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 8152 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 8153 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 8154 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 8155 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 8156 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 8157 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 8158 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 8159 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 8160 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 8161 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 8162 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 8163 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 8164 8165 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000408) 8166 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 8167 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 8168 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 8169 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 8170 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 8171 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 8172 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 8173 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 8174 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 8175 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 8176 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 8177 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 8178 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 8179 8180 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 8181 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 8182 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 8183 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 8184 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 8185 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 8186 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 8187 in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 8188 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 8189 out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 8190 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 8191 out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 8192 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 8193 #define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 8194 8195 #define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00010000) 8196 #define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00010000) 8197 #define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000 8198 8199 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 8200 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 8201 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 8202 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 8203 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 8204 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 8205 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 8206 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 8207 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 8208 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 8209 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 8210 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 8211 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 8212 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 8213 8214 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 8215 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 8216 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 8217 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 8218 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 8219 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 8220 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 8221 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 8222 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 8223 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 8224 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 8225 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 8226 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 8227 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 8228 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 8229 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 8230 8231 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 8232 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 8233 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 8234 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 8235 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 8236 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 8237 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 8238 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 8239 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 8240 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 8241 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 8242 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 8243 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 8244 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 8245 8246 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 8247 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 8248 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 8249 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 8250 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 8251 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 8252 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 8253 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 8254 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 8255 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 8256 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 8257 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 8258 8259 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 8260 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 8261 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 8262 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 8263 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 8264 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 8265 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 8266 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 8267 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 8268 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 8269 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 8270 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 8271 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 8272 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 8273 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 8274 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 8275 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 8276 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 8277 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 8278 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 8279 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 8280 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 8281 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 8282 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 8283 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 8284 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 8285 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 8286 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 8287 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 8288 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 8289 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 8290 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 8291 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 8292 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 8293 8294 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 8295 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 8296 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 8297 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 8298 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 8299 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 8300 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 8301 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 8302 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 8303 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 8304 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 8305 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 8306 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 8307 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 8308 8309 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 8310 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 8311 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 8312 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 8313 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 8314 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 8315 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 8316 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 8317 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 8318 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 8319 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 8320 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 8321 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 8322 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 8323 8324 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 8325 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 8326 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 8327 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 8328 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 8329 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 8330 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 8331 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 8332 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 8333 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 8334 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 8335 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 8336 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 8337 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 8338 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 8339 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 8340 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 8341 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 8342 8343 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 8344 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 8345 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 8346 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 8347 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 8348 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 8349 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 8350 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 8351 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 8352 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 8353 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 8354 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 8355 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 8356 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 8357 8358 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 8359 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 8360 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 8361 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 8362 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 8363 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 8364 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 8365 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 8366 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 8367 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 8368 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 8369 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 8370 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 8371 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 8372 8373 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 8374 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 8375 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 8376 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 8377 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 8378 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 8379 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 8380 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 8381 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 8382 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 8383 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 8384 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 8385 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 8386 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 8387 8388 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 8389 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 8390 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 8391 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 8392 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 8393 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 8394 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 8395 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 8396 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 8397 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 8398 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 8399 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 8400 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 8401 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 8402 8403 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 8404 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 8405 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 8406 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 8407 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 8408 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 8409 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 8410 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 8411 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 8412 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 8413 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 8414 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 8415 8416 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 8417 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 8418 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 8419 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 8420 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 8421 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 8422 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 8423 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 8424 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 8425 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 8426 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 8427 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 8428 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 8429 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 8430 8431 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 8432 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 8433 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 8434 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 8435 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 8436 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 8437 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 8438 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 8439 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 8440 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 8441 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 8442 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 8443 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 8444 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 8445 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 8446 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 8447 8448 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 8449 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 8450 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 8451 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 8452 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 8453 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 8454 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 8455 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 8456 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 8457 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 8458 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 8459 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 8460 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 8461 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 8462 8463 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 8464 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 8465 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 8466 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 8467 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 8468 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 8469 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 8470 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 8471 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 8472 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 8473 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 8474 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 8475 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 8476 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 8477 8478 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 8479 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 8480 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 8481 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 8482 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 8483 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 8484 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 8485 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 8486 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 8487 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 8488 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 8489 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 8490 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 8491 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 8492 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 8493 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 8494 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 8495 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 8496 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 8497 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 8498 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 8499 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 8500 8501 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 8502 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 8503 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 8504 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 8505 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 8506 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 8507 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 8508 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 8509 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 8510 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 8511 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 8512 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 8513 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 8514 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 8515 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 8516 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 8517 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 8518 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 8519 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 8520 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 8521 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 8522 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 8523 8524 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 8525 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 8526 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 8527 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 8528 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 8529 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 8530 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 8531 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 8532 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 8533 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 8534 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 8535 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 8536 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 8537 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 8538 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 8539 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 8540 8541 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 8542 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 8543 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 8544 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 8545 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 8546 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 8547 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 8548 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 8549 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 8550 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 8551 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 8552 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 8553 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 8554 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 8555 8556 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 8557 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 8558 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 8559 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 8560 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 8561 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 8562 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 8563 in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 8564 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 8565 out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 8566 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 8567 out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 8568 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 8569 #define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 8570 8571 #define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00011000) 8572 #define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00011000) 8573 #define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000 8574 8575 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000000) 8576 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 8577 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 8578 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 8579 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 8580 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 8581 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 8582 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 8583 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 8584 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 8585 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 8586 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 8587 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 8588 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 8589 8590 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000004) 8591 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 8592 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 8593 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 8594 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 8595 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 8596 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 8597 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 8598 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 8599 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 8600 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 8601 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 8602 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 8603 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 8604 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 8605 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 8606 8607 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000008) 8608 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 8609 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 8610 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 8611 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 8612 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 8613 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 8614 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 8615 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 8616 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 8617 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 8618 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 8619 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 8620 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 8621 8622 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 8623 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 8624 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 8625 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 8626 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 8627 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 8628 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 8629 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 8630 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 8631 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 8632 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 8633 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 8634 8635 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000010) 8636 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 8637 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 8638 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 8639 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 8640 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 8641 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 8642 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 8643 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 8644 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 8645 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 8646 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 8647 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 8648 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 8649 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 8650 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 8651 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 8652 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 8653 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 8654 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 8655 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 8656 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 8657 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 8658 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 8659 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 8660 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 8661 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 8662 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 8663 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 8664 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 8665 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 8666 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 8667 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 8668 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 8669 8670 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 8671 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 8672 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 8673 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 8674 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 8675 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 8676 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 8677 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 8678 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 8679 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 8680 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 8681 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 8682 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 8683 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 8684 8685 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000020) 8686 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 8687 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 8688 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 8689 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 8690 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 8691 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 8692 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 8693 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 8694 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 8695 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 8696 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 8697 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 8698 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 8699 8700 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000030) 8701 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 8702 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 8703 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 8704 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 8705 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 8706 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 8707 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 8708 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 8709 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 8710 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 8711 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 8712 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 8713 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 8714 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 8715 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 8716 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 8717 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 8718 8719 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000034) 8720 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 8721 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 8722 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 8723 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 8724 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 8725 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 8726 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 8727 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 8728 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 8729 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 8730 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 8731 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 8732 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 8733 8734 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000038) 8735 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 8736 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 8737 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 8738 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 8739 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 8740 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 8741 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 8742 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 8743 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 8744 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 8745 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 8746 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 8747 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 8748 8749 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 8750 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 8751 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 8752 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 8753 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 8754 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 8755 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 8756 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 8757 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 8758 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 8759 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 8760 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 8761 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 8762 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 8763 8764 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000040) 8765 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 8766 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 8767 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 8768 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 8769 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 8770 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 8771 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 8772 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 8773 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 8774 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 8775 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 8776 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 8777 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 8778 8779 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000044) 8780 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 8781 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 8782 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 8783 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 8784 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 8785 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 8786 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 8787 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 8788 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 8789 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 8790 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 8791 8792 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000048) 8793 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 8794 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 8795 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 8796 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 8797 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 8798 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 8799 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 8800 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 8801 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 8802 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 8803 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 8804 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 8805 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 8806 8807 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 8808 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 8809 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 8810 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 8811 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 8812 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 8813 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 8814 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 8815 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 8816 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 8817 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 8818 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 8819 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 8820 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 8821 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 8822 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 8823 8824 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000050) 8825 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 8826 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 8827 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 8828 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 8829 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 8830 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 8831 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 8832 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 8833 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 8834 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 8835 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 8836 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 8837 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 8838 8839 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000054) 8840 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 8841 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 8842 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 8843 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 8844 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 8845 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 8846 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 8847 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 8848 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 8849 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 8850 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 8851 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 8852 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 8853 8854 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000058) 8855 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 8856 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 8857 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 8858 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 8859 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 8860 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 8861 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 8862 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 8863 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 8864 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 8865 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 8866 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 8867 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 8868 8869 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 8870 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 8871 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 8872 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 8873 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 8874 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 8875 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 8876 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 8877 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 8878 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 8879 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 8880 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 8881 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 8882 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 8883 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 8884 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 8885 8886 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000060) 8887 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 8888 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 8889 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 8890 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 8891 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 8892 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 8893 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 8894 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 8895 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 8896 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 8897 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 8898 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 8899 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 8900 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 8901 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 8902 8903 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000064) 8904 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 8905 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 8906 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 8907 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 8908 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 8909 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 8910 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 8911 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 8912 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 8913 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 8914 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 8915 8916 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000068) 8917 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 8918 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 8919 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 8920 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 8921 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 8922 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 8923 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 8924 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 8925 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 8926 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 8927 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 8928 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 8929 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 8930 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 8931 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 8932 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 8933 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 8934 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 8935 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 8936 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 8937 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 8938 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 8939 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 8940 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 8941 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 8942 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 8943 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 8944 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 8945 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 8946 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 8947 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 8948 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 8949 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 8950 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 8951 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 8952 8953 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 8954 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 8955 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 8956 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 8957 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 8958 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 8959 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 8960 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 8961 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 8962 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 8963 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 8964 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 8965 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 8966 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 8967 8968 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000070) 8969 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 8970 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 8971 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 8972 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 8973 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 8974 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 8975 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 8976 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 8977 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 8978 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 8979 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 8980 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 8981 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 8982 8983 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 8984 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 8985 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 8986 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 8987 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 8988 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 8989 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 8990 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 8991 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 8992 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 8993 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 8994 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 8995 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 8996 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 8997 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 8998 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 8999 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 9000 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 9001 9002 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000080) 9003 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 9004 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 9005 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 9006 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 9007 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 9008 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 9009 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 9010 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 9011 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 9012 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 9013 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 9014 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 9015 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 9016 9017 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000084) 9018 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 9019 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 9020 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 9021 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 9022 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 9023 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 9024 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 9025 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 9026 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 9027 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 9028 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 9029 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 9030 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 9031 9032 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 9033 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 9034 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 9035 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 9036 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 9037 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 9038 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 9039 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 9040 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 9041 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 9042 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 9043 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 9044 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 9045 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 9046 9047 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 9048 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 9049 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 9050 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 9051 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 9052 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 9053 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 9054 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 9055 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 9056 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 9057 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 9058 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 9059 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 9060 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 9061 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 9062 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 9063 9064 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 9065 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 9066 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 9067 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 9068 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 9069 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 9070 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 9071 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 9072 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 9073 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 9074 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 9075 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 9076 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 9077 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 9078 9079 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 9080 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 9081 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 9082 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 9083 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 9084 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 9085 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 9086 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 9087 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 9088 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 9089 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 9090 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 9091 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 9092 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 9093 9094 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 9095 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 9096 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 9097 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 9098 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 9099 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 9100 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 9101 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 9102 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 9103 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 9104 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 9105 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 9106 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 9107 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 9108 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 9109 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 9110 9111 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 9112 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 9113 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 9114 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 9115 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 9116 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 9117 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 9118 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 9119 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 9120 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 9121 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 9122 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 9123 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 9124 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 9125 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 9126 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 9127 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 9128 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 9129 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 9130 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 9131 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 9132 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 9133 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 9134 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 9135 9136 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 9137 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 9138 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 9139 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 9140 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 9141 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 9142 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 9143 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 9144 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 9145 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 9146 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 9147 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 9148 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 9149 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 9150 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 9151 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 9152 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 9153 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 9154 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 9155 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 9156 9157 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000400) 9158 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 9159 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 9160 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 9161 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 9162 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 9163 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 9164 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 9165 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 9166 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 9167 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 9168 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 9169 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 9170 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 9171 9172 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000404) 9173 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 9174 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 9175 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 9176 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 9177 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 9178 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 9179 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 9180 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 9181 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 9182 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 9183 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 9184 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 9185 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 9186 9187 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000408) 9188 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 9189 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 9190 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 9191 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 9192 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 9193 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 9194 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 9195 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 9196 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 9197 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 9198 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 9199 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 9200 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 9201 9202 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 9203 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 9204 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 9205 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 9206 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 9207 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 9208 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 9209 in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 9210 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 9211 out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 9212 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 9213 out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 9214 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 9215 #define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 9216 9217 #define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00012000) 9218 #define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00012000) 9219 #define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000 9220 9221 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 9222 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 9223 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 9224 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 9225 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 9226 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 9227 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 9228 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 9229 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 9230 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 9231 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 9232 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 9233 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 9234 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 9235 9236 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 9237 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 9238 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 9239 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 9240 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 9241 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 9242 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 9243 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 9244 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 9245 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 9246 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 9247 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 9248 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 9249 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 9250 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 9251 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 9252 9253 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 9254 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 9255 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 9256 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 9257 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 9258 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 9259 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 9260 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 9261 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 9262 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 9263 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 9264 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 9265 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 9266 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 9267 9268 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 9269 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 9270 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 9271 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 9272 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 9273 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 9274 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 9275 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 9276 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 9277 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 9278 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 9279 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 9280 9281 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 9282 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 9283 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 9284 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 9285 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 9286 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 9287 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 9288 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 9289 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 9290 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 9291 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 9292 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 9293 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 9294 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 9295 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 9296 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 9297 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 9298 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 9299 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 9300 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 9301 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 9302 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 9303 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 9304 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 9305 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 9306 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 9307 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 9308 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 9309 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 9310 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 9311 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 9312 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 9313 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 9314 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 9315 9316 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 9317 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 9318 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 9319 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 9320 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 9321 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 9322 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 9323 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 9324 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 9325 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 9326 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 9327 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 9328 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 9329 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 9330 9331 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 9332 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 9333 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 9334 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 9335 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 9336 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 9337 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 9338 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 9339 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 9340 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 9341 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 9342 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 9343 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 9344 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 9345 9346 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 9347 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 9348 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 9349 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 9350 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 9351 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 9352 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 9353 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 9354 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 9355 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 9356 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 9357 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 9358 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 9359 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 9360 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 9361 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 9362 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 9363 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 9364 9365 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 9366 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 9367 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 9368 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 9369 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 9370 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 9371 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 9372 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 9373 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 9374 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 9375 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 9376 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 9377 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 9378 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 9379 9380 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 9381 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 9382 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 9383 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 9384 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 9385 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 9386 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 9387 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 9388 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 9389 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 9390 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 9391 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 9392 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 9393 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 9394 9395 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 9396 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 9397 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 9398 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 9399 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 9400 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 9401 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 9402 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 9403 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 9404 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 9405 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 9406 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 9407 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 9408 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 9409 9410 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 9411 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 9412 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 9413 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 9414 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 9415 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 9416 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 9417 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 9418 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 9419 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 9420 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 9421 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 9422 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 9423 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 9424 9425 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 9426 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 9427 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 9428 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 9429 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 9430 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 9431 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 9432 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 9433 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 9434 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 9435 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 9436 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 9437 9438 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 9439 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 9440 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 9441 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 9442 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 9443 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 9444 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 9445 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 9446 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 9447 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 9448 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 9449 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 9450 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 9451 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 9452 9453 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 9454 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 9455 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 9456 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 9457 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 9458 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 9459 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 9460 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 9461 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 9462 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 9463 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 9464 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 9465 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 9466 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 9467 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 9468 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 9469 9470 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 9471 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 9472 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 9473 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 9474 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 9475 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 9476 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 9477 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 9478 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 9479 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 9480 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 9481 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 9482 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 9483 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 9484 9485 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 9486 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 9487 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 9488 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 9489 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 9490 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 9491 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 9492 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 9493 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 9494 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 9495 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 9496 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 9497 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 9498 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 9499 9500 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 9501 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 9502 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 9503 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 9504 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 9505 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 9506 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 9507 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 9508 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 9509 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 9510 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 9511 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 9512 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 9513 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 9514 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 9515 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 9516 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 9517 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 9518 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 9519 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 9520 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 9521 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 9522 9523 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 9524 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 9525 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 9526 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 9527 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 9528 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 9529 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 9530 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 9531 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 9532 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 9533 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 9534 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 9535 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 9536 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 9537 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 9538 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 9539 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 9540 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 9541 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 9542 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 9543 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 9544 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 9545 9546 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 9547 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 9548 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 9549 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 9550 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 9551 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 9552 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 9553 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 9554 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 9555 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 9556 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 9557 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 9558 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 9559 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 9560 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 9561 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 9562 9563 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 9564 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 9565 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 9566 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 9567 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 9568 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 9569 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 9570 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 9571 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 9572 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 9573 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 9574 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 9575 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 9576 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 9577 9578 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 9579 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 9580 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 9581 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 9582 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 9583 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 9584 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 9585 in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 9586 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 9587 out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 9588 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 9589 out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 9590 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 9591 #define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 9592 9593 #define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00013000) 9594 #define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00013000) 9595 #define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000 9596 9597 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000000) 9598 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 9599 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 9600 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 9601 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 9602 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 9603 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 9604 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 9605 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 9606 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 9607 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 9608 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 9609 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 9610 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 9611 9612 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000004) 9613 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 9614 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 9615 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 9616 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 9617 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 9618 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 9619 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 9620 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 9621 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 9622 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 9623 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 9624 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 9625 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 9626 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 9627 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 9628 9629 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000008) 9630 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 9631 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 9632 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 9633 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 9634 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 9635 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 9636 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 9637 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 9638 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 9639 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 9640 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 9641 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 9642 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 9643 9644 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 9645 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 9646 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 9647 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 9648 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 9649 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 9650 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 9651 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 9652 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 9653 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 9654 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 9655 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 9656 9657 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000010) 9658 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 9659 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 9660 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 9661 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 9662 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 9663 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 9664 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 9665 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 9666 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 9667 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 9668 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 9669 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 9670 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 9671 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 9672 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 9673 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 9674 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 9675 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 9676 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 9677 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 9678 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 9679 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 9680 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 9681 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 9682 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 9683 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 9684 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 9685 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 9686 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 9687 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 9688 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 9689 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 9690 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 9691 9692 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 9693 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 9694 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 9695 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 9696 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 9697 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 9698 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 9699 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 9700 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 9701 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 9702 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 9703 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 9704 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 9705 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 9706 9707 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000020) 9708 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 9709 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 9710 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 9711 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 9712 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 9713 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 9714 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 9715 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 9716 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 9717 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 9718 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 9719 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 9720 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 9721 9722 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000030) 9723 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 9724 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 9725 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 9726 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 9727 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 9728 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 9729 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 9730 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 9731 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 9732 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 9733 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 9734 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 9735 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 9736 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 9737 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 9738 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 9739 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 9740 9741 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000034) 9742 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 9743 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 9744 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 9745 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 9746 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 9747 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 9748 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 9749 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 9750 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 9751 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 9752 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 9753 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 9754 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 9755 9756 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000038) 9757 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 9758 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 9759 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 9760 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 9761 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 9762 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 9763 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 9764 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 9765 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 9766 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 9767 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 9768 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 9769 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 9770 9771 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 9772 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 9773 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 9774 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 9775 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 9776 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 9777 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 9778 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 9779 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 9780 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 9781 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 9782 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 9783 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 9784 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 9785 9786 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000040) 9787 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 9788 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 9789 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 9790 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 9791 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 9792 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 9793 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 9794 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 9795 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 9796 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 9797 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 9798 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 9799 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 9800 9801 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000044) 9802 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 9803 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 9804 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 9805 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 9806 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 9807 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 9808 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 9809 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 9810 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 9811 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 9812 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 9813 9814 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000048) 9815 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 9816 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 9817 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 9818 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 9819 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 9820 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 9821 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 9822 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 9823 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 9824 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 9825 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 9826 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 9827 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 9828 9829 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 9830 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 9831 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 9832 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 9833 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 9834 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 9835 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 9836 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 9837 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 9838 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 9839 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 9840 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 9841 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 9842 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 9843 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 9844 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 9845 9846 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000050) 9847 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 9848 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 9849 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 9850 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 9851 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 9852 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 9853 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 9854 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 9855 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 9856 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 9857 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 9858 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 9859 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 9860 9861 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000054) 9862 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 9863 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 9864 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 9865 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 9866 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 9867 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 9868 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 9869 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 9870 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 9871 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 9872 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 9873 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 9874 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 9875 9876 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000058) 9877 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 9878 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 9879 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 9880 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 9881 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 9882 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 9883 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 9884 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 9885 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 9886 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 9887 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 9888 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 9889 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 9890 9891 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 9892 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 9893 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 9894 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 9895 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 9896 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 9897 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 9898 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 9899 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 9900 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 9901 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 9902 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 9903 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 9904 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 9905 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 9906 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 9907 9908 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000060) 9909 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 9910 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 9911 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 9912 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 9913 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 9914 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 9915 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 9916 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 9917 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 9918 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 9919 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 9920 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 9921 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 9922 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 9923 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 9924 9925 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000064) 9926 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 9927 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 9928 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 9929 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 9930 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 9931 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 9932 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 9933 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 9934 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 9935 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 9936 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 9937 9938 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000068) 9939 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 9940 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 9941 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 9942 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 9943 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 9944 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 9945 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 9946 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 9947 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 9948 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 9949 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 9950 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 9951 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 9952 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 9953 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 9954 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 9955 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 9956 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 9957 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 9958 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 9959 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 9960 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 9961 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 9962 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 9963 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 9964 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 9965 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 9966 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 9967 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 9968 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 9969 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 9970 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 9971 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 9972 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 9973 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 9974 9975 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 9976 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 9977 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 9978 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 9979 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 9980 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 9981 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 9982 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 9983 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 9984 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 9985 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 9986 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 9987 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 9988 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 9989 9990 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000070) 9991 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 9992 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 9993 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 9994 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 9995 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 9996 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 9997 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 9998 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 9999 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 10000 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 10001 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 10002 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 10003 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 10004 10005 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 10006 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 10007 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 10008 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 10009 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 10010 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 10011 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 10012 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 10013 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 10014 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 10015 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 10016 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 10017 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 10018 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 10019 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 10020 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 10021 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 10022 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 10023 10024 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000080) 10025 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 10026 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 10027 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 10028 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 10029 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 10030 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 10031 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 10032 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 10033 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 10034 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 10035 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 10036 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 10037 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 10038 10039 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000084) 10040 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 10041 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 10042 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 10043 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 10044 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 10045 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 10046 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 10047 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 10048 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 10049 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 10050 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 10051 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 10052 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 10053 10054 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 10055 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 10056 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 10057 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 10058 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 10059 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 10060 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 10061 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 10062 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 10063 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 10064 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 10065 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 10066 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 10067 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 10068 10069 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 10070 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 10071 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 10072 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 10073 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 10074 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 10075 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 10076 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 10077 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 10078 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 10079 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 10080 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 10081 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 10082 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 10083 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 10084 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 10085 10086 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 10087 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 10088 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 10089 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 10090 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 10091 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 10092 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 10093 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 10094 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 10095 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 10096 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 10097 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 10098 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 10099 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 10100 10101 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 10102 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 10103 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 10104 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 10105 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 10106 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 10107 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 10108 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 10109 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 10110 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 10111 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 10112 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 10113 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 10114 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 10115 10116 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 10117 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 10118 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 10119 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 10120 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 10121 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 10122 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 10123 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 10124 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 10125 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 10126 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 10127 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 10128 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 10129 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 10130 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 10131 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 10132 10133 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 10134 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 10135 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 10136 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 10137 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 10138 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 10139 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 10140 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 10141 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 10142 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 10143 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 10144 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 10145 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 10146 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 10147 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 10148 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 10149 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 10150 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 10151 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 10152 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 10153 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 10154 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 10155 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 10156 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 10157 10158 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 10159 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 10160 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 10161 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 10162 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 10163 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 10164 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 10165 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 10166 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 10167 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 10168 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 10169 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 10170 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 10171 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 10172 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 10173 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 10174 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 10175 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 10176 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 10177 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 10178 10179 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000400) 10180 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 10181 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 10182 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 10183 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 10184 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 10185 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 10186 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 10187 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 10188 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 10189 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 10190 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 10191 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 10192 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 10193 10194 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000404) 10195 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 10196 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 10197 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 10198 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 10199 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 10200 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 10201 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 10202 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 10203 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 10204 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 10205 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 10206 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 10207 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 10208 10209 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000408) 10210 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 10211 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 10212 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 10213 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 10214 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 10215 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 10216 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 10217 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 10218 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 10219 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 10220 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 10221 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 10222 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 10223 10224 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 10225 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 10226 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 10227 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 10228 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 10229 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 10230 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 10231 in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 10232 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 10233 out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 10234 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 10235 out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 10236 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 10237 #define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 10238 10239 #define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00014000) 10240 #define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00014000) 10241 #define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000 10242 10243 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 10244 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 10245 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 10246 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 10247 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 10248 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 10249 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 10250 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 10251 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 10252 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 10253 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 10254 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 10255 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 10256 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 10257 10258 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 10259 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 10260 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 10261 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 10262 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 10263 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 10264 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 10265 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 10266 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 10267 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 10268 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 10269 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 10270 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 10271 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 10272 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 10273 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 10274 10275 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 10276 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 10277 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 10278 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 10279 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 10280 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 10281 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 10282 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 10283 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 10284 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 10285 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 10286 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 10287 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 10288 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 10289 10290 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 10291 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 10292 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 10293 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 10294 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 10295 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 10296 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 10297 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 10298 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 10299 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 10300 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 10301 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 10302 10303 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 10304 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 10305 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 10306 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 10307 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 10308 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 10309 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 10310 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 10311 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 10312 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 10313 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 10314 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 10315 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 10316 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 10317 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 10318 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 10319 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 10320 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 10321 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 10322 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 10323 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 10324 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 10325 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 10326 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 10327 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 10328 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 10329 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 10330 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 10331 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 10332 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 10333 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 10334 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 10335 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 10336 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 10337 10338 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 10339 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 10340 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 10341 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 10342 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 10343 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 10344 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 10345 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 10346 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 10347 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 10348 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 10349 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 10350 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 10351 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 10352 10353 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 10354 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 10355 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 10356 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 10357 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 10358 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 10359 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 10360 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 10361 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 10362 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 10363 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 10364 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 10365 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 10366 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 10367 10368 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 10369 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 10370 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 10371 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 10372 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 10373 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 10374 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 10375 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 10376 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 10377 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 10378 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 10379 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 10380 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 10381 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 10382 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 10383 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 10384 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 10385 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 10386 10387 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 10388 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 10389 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 10390 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 10391 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 10392 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 10393 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 10394 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 10395 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 10396 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 10397 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 10398 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 10399 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 10400 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 10401 10402 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 10403 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 10404 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 10405 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 10406 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 10407 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 10408 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 10409 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 10410 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 10411 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 10412 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 10413 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 10414 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 10415 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 10416 10417 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 10418 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 10419 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 10420 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 10421 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 10422 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 10423 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 10424 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 10425 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 10426 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 10427 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 10428 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 10429 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 10430 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 10431 10432 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 10433 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 10434 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 10435 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 10436 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 10437 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 10438 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 10439 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 10440 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 10441 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 10442 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 10443 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 10444 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 10445 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 10446 10447 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 10448 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 10449 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 10450 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 10451 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 10452 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 10453 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 10454 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 10455 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 10456 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 10457 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 10458 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 10459 10460 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 10461 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 10462 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 10463 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 10464 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 10465 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 10466 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 10467 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 10468 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 10469 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 10470 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 10471 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 10472 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 10473 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 10474 10475 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 10476 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 10477 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 10478 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 10479 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 10480 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 10481 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 10482 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 10483 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 10484 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 10485 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 10486 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 10487 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 10488 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 10489 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 10490 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 10491 10492 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 10493 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 10494 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 10495 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 10496 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 10497 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 10498 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 10499 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 10500 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 10501 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 10502 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 10503 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 10504 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 10505 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 10506 10507 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 10508 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 10509 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 10510 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 10511 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 10512 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 10513 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 10514 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 10515 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 10516 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 10517 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 10518 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 10519 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 10520 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 10521 10522 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 10523 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 10524 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 10525 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 10526 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 10527 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 10528 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 10529 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 10530 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 10531 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 10532 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 10533 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 10534 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 10535 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 10536 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 10537 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 10538 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 10539 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 10540 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 10541 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 10542 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 10543 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 10544 10545 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 10546 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 10547 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 10548 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 10549 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 10550 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 10551 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 10552 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 10553 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 10554 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 10555 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 10556 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 10557 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 10558 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 10559 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 10560 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 10561 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 10562 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 10563 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 10564 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 10565 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 10566 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 10567 10568 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 10569 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 10570 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 10571 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 10572 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 10573 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 10574 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 10575 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 10576 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 10577 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 10578 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 10579 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 10580 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 10581 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 10582 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 10583 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 10584 10585 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 10586 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 10587 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 10588 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 10589 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 10590 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 10591 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 10592 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 10593 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 10594 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 10595 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 10596 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 10597 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 10598 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 10599 10600 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 10601 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 10602 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 10603 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 10604 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 10605 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 10606 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 10607 in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 10608 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 10609 out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 10610 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 10611 out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 10612 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 10613 #define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 10614 10615 #define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00015000) 10616 #define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00015000) 10617 #define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000 10618 10619 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000000) 10620 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 10621 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 10622 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 10623 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 10624 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 10625 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 10626 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 10627 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 10628 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 10629 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 10630 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 10631 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 10632 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 10633 10634 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000004) 10635 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 10636 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 10637 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 10638 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 10639 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 10640 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 10641 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 10642 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 10643 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 10644 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 10645 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 10646 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 10647 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 10648 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 10649 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 10650 10651 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000008) 10652 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 10653 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 10654 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 10655 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 10656 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 10657 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 10658 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 10659 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 10660 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 10661 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 10662 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 10663 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 10664 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 10665 10666 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 10667 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 10668 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 10669 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 10670 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 10671 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 10672 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 10673 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 10674 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 10675 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 10676 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 10677 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 10678 10679 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000010) 10680 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 10681 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 10682 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 10683 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 10684 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 10685 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 10686 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 10687 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 10688 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 10689 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 10690 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 10691 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 10692 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 10693 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 10694 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 10695 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 10696 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 10697 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 10698 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 10699 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 10700 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 10701 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 10702 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 10703 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 10704 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 10705 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 10706 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 10707 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 10708 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 10709 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 10710 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 10711 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 10712 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 10713 10714 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 10715 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 10716 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 10717 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 10718 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 10719 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 10720 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 10721 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 10722 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 10723 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 10724 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 10725 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 10726 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 10727 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 10728 10729 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000020) 10730 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 10731 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 10732 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 10733 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 10734 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 10735 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 10736 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 10737 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 10738 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 10739 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 10740 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 10741 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 10742 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 10743 10744 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000030) 10745 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 10746 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 10747 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 10748 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 10749 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 10750 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 10751 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 10752 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 10753 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 10754 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 10755 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 10756 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 10757 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 10758 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 10759 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 10760 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 10761 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 10762 10763 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000034) 10764 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 10765 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 10766 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 10767 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 10768 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 10769 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 10770 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 10771 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 10772 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 10773 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 10774 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 10775 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 10776 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 10777 10778 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000038) 10779 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 10780 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 10781 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 10782 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 10783 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 10784 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 10785 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 10786 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 10787 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 10788 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 10789 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 10790 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 10791 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 10792 10793 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 10794 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 10795 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 10796 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 10797 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 10798 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 10799 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 10800 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 10801 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 10802 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 10803 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 10804 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 10805 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 10806 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 10807 10808 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000040) 10809 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 10810 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 10811 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 10812 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 10813 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 10814 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 10815 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 10816 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 10817 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 10818 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 10819 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 10820 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 10821 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 10822 10823 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000044) 10824 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 10825 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 10826 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 10827 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 10828 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 10829 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 10830 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 10831 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 10832 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 10833 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 10834 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 10835 10836 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000048) 10837 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 10838 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 10839 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 10840 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 10841 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 10842 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 10843 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 10844 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 10845 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 10846 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 10847 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 10848 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 10849 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 10850 10851 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 10852 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 10853 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 10854 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 10855 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 10856 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 10857 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 10858 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 10859 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 10860 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 10861 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 10862 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 10863 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 10864 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 10865 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 10866 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 10867 10868 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000050) 10869 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 10870 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 10871 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 10872 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 10873 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 10874 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 10875 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 10876 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 10877 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 10878 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 10879 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 10880 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 10881 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 10882 10883 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000054) 10884 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 10885 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 10886 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 10887 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 10888 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 10889 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 10890 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 10891 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 10892 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 10893 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 10894 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 10895 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 10896 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 10897 10898 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000058) 10899 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 10900 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 10901 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 10902 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 10903 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 10904 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 10905 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 10906 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 10907 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 10908 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 10909 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 10910 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 10911 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 10912 10913 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 10914 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 10915 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 10916 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 10917 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 10918 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 10919 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 10920 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 10921 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 10922 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 10923 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 10924 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 10925 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 10926 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 10927 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 10928 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 10929 10930 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000060) 10931 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 10932 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 10933 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 10934 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 10935 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 10936 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 10937 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 10938 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 10939 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 10940 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 10941 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 10942 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 10943 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 10944 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 10945 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 10946 10947 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000064) 10948 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 10949 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 10950 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 10951 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 10952 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 10953 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 10954 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 10955 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 10956 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 10957 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 10958 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 10959 10960 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000068) 10961 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 10962 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 10963 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 10964 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 10965 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 10966 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 10967 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 10968 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 10969 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 10970 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 10971 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 10972 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 10973 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 10974 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 10975 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 10976 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 10977 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 10978 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 10979 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 10980 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 10981 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 10982 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 10983 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 10984 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 10985 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 10986 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 10987 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 10988 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 10989 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 10990 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 10991 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 10992 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 10993 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 10994 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 10995 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 10996 10997 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 10998 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 10999 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 11000 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 11001 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 11002 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 11003 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 11004 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 11005 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 11006 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 11007 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 11008 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 11009 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 11010 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 11011 11012 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000070) 11013 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 11014 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 11015 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 11016 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 11017 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 11018 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 11019 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 11020 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 11021 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 11022 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 11023 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 11024 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 11025 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 11026 11027 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 11028 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 11029 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 11030 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 11031 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 11032 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 11033 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 11034 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 11035 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 11036 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 11037 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 11038 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 11039 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 11040 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 11041 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 11042 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 11043 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 11044 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 11045 11046 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000080) 11047 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 11048 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 11049 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 11050 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 11051 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 11052 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 11053 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 11054 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 11055 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 11056 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 11057 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 11058 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 11059 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 11060 11061 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000084) 11062 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 11063 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 11064 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 11065 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 11066 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 11067 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 11068 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 11069 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 11070 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 11071 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 11072 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 11073 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 11074 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 11075 11076 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 11077 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 11078 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 11079 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 11080 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 11081 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 11082 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 11083 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 11084 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 11085 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 11086 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 11087 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 11088 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 11089 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 11090 11091 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 11092 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 11093 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 11094 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 11095 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 11096 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 11097 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 11098 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 11099 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 11100 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 11101 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 11102 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 11103 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 11104 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 11105 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 11106 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 11107 11108 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 11109 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 11110 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 11111 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 11112 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 11113 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 11114 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 11115 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 11116 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 11117 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 11118 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 11119 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 11120 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 11121 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 11122 11123 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 11124 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 11125 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 11126 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 11127 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 11128 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 11129 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 11130 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 11131 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 11132 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 11133 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 11134 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 11135 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 11136 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 11137 11138 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 11139 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 11140 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 11141 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 11142 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 11143 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 11144 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 11145 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 11146 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 11147 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 11148 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 11149 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 11150 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 11151 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 11152 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 11153 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 11154 11155 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 11156 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 11157 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 11158 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 11159 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 11160 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 11161 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 11162 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 11163 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 11164 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 11165 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 11166 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 11167 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 11168 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 11169 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 11170 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 11171 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 11172 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 11173 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 11174 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 11175 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 11176 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 11177 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 11178 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 11179 11180 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 11181 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 11182 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 11183 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 11184 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 11185 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 11186 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 11187 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 11188 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 11189 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 11190 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 11191 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 11192 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 11193 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 11194 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 11195 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 11196 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 11197 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 11198 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 11199 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 11200 11201 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000400) 11202 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 11203 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 11204 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 11205 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 11206 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 11207 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 11208 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 11209 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 11210 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 11211 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 11212 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 11213 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 11214 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 11215 11216 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000404) 11217 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 11218 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 11219 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 11220 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 11221 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 11222 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 11223 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 11224 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 11225 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 11226 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 11227 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 11228 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 11229 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 11230 11231 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000408) 11232 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 11233 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 11234 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 11235 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 11236 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 11237 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 11238 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 11239 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 11240 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 11241 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 11242 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 11243 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 11244 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 11245 11246 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 11247 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 11248 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 11249 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 11250 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 11251 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 11252 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 11253 in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 11254 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 11255 out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 11256 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 11257 out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 11258 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 11259 #define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 11260 11261 #define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00016000) 11262 #define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00016000) 11263 #define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000 11264 11265 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000000) 11266 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) 11267 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) 11268 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 11269 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ 11270 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 11271 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ 11272 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) 11273 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ 11274 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) 11275 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ 11276 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) 11277 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 11278 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 11279 11280 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000004) 11281 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) 11282 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) 11283 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff 11284 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ 11285 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 11286 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ 11287 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) 11288 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ 11289 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) 11290 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ 11291 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) 11292 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 11293 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 11294 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 11295 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 11296 11297 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000008) 11298 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) 11299 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) 11300 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff 11301 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ 11302 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 11303 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ 11304 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) 11305 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ 11306 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) 11307 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ 11308 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) 11309 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff 11310 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 11311 11312 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) 11313 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) 11314 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) 11315 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 11316 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ 11317 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 11318 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ 11319 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) 11320 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 11321 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 11322 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 11323 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 11324 11325 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000010) 11326 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) 11327 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) 11328 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff 11329 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ 11330 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 11331 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ 11332 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) 11333 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ 11334 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) 11335 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ 11336 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) 11337 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 11338 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 11339 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 11340 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 11341 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 11342 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 11343 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 11344 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 11345 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 11346 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 11347 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 11348 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 11349 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 11350 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 11351 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 11352 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 11353 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 11354 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 11355 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 11356 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 11357 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 11358 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 11359 11360 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) 11361 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) 11362 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) 11363 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 11364 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ 11365 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 11366 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ 11367 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) 11368 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ 11369 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) 11370 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ 11371 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) 11372 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 11373 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 11374 11375 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000020) 11376 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) 11377 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) 11378 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff 11379 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ 11380 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 11381 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ 11382 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) 11383 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ 11384 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) 11385 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ 11386 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) 11387 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 11388 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 11389 11390 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000030) 11391 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) 11392 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) 11393 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 11394 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ 11395 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 11396 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 11397 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 11398 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 11399 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 11400 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 11401 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) 11402 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 11403 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 11404 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 11405 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 11406 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 11407 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 11408 11409 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000034) 11410 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) 11411 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) 11412 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 11413 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ 11414 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 11415 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 11416 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 11417 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 11418 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 11419 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 11420 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) 11421 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 11422 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 11423 11424 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000038) 11425 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) 11426 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) 11427 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 11428 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ 11429 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 11430 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ 11431 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) 11432 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 11433 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 11434 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 11435 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 11436 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 11437 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 11438 11439 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) 11440 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) 11441 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) 11442 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 11443 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ 11444 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 11445 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 11446 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 11447 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 11448 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 11449 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 11450 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) 11451 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 11452 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 11453 11454 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000040) 11455 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) 11456 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) 11457 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 11458 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ 11459 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 11460 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 11461 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 11462 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 11463 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 11464 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 11465 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) 11466 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 11467 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 11468 11469 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000044) 11470 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) 11471 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) 11472 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 11473 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ 11474 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 11475 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 11476 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 11477 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 11478 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 11479 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 11480 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 11481 11482 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000048) 11483 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) 11484 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) 11485 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 11486 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ 11487 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 11488 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ 11489 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) 11490 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ 11491 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) 11492 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ 11493 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) 11494 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 11495 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 11496 11497 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) 11498 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) 11499 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) 11500 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff 11501 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ 11502 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 11503 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ 11504 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) 11505 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ 11506 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) 11507 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ 11508 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) 11509 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 11510 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 11511 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 11512 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 11513 11514 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000050) 11515 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) 11516 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) 11517 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 11518 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ 11519 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 11520 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ 11521 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) 11522 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ 11523 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) 11524 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ 11525 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) 11526 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 11527 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 11528 11529 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000054) 11530 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) 11531 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) 11532 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff 11533 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ 11534 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 11535 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ 11536 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) 11537 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ 11538 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) 11539 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 11540 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) 11541 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 11542 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 11543 11544 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000058) 11545 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) 11546 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) 11547 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f 11548 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ 11549 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 11550 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ 11551 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) 11552 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ 11553 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) 11554 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ 11555 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) 11556 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 11557 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 11558 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 11559 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 11560 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 11561 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 11562 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 11563 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 11564 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 11565 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 11566 11567 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) 11568 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) 11569 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) 11570 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f 11571 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ 11572 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 11573 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ 11574 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) 11575 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ 11576 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) 11577 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ 11578 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) 11579 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 11580 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 11581 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 11582 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 11583 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 11584 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 11585 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 11586 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 11587 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 11588 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 11589 11590 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000060) 11591 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) 11592 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) 11593 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 11594 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ 11595 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 11596 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ 11597 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) 11598 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ 11599 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) 11600 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ 11601 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) 11602 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 11603 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 11604 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff 11605 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 11606 11607 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000400) 11608 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) 11609 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) 11610 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff 11611 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ 11612 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 11613 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ 11614 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) 11615 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ 11616 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) 11617 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ 11618 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) 11619 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff 11620 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 11621 11622 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000404) 11623 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) 11624 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) 11625 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff 11626 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ 11627 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 11628 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ 11629 in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) 11630 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ 11631 out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) 11632 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ 11633 out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) 11634 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff 11635 #define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 11636 11637 #define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00017000) 11638 #define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00017000) 11639 #define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000 11640 11641 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000000) 11642 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) 11643 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) 11644 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 11645 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ 11646 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 11647 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ 11648 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) 11649 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ 11650 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) 11651 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ 11652 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) 11653 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 11654 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 11655 11656 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000004) 11657 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) 11658 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) 11659 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff 11660 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ 11661 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 11662 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ 11663 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) 11664 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ 11665 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) 11666 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ 11667 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) 11668 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 11669 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 11670 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 11671 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 11672 11673 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000008) 11674 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) 11675 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) 11676 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff 11677 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ 11678 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 11679 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ 11680 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) 11681 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ 11682 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) 11683 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ 11684 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) 11685 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff 11686 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 11687 11688 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000000c) 11689 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) 11690 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) 11691 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 11692 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ 11693 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 11694 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ 11695 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) 11696 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 11697 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 11698 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 11699 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 11700 11701 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000010) 11702 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) 11703 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) 11704 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff 11705 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ 11706 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 11707 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ 11708 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) 11709 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ 11710 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) 11711 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ 11712 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) 11713 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 11714 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 11715 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 11716 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 11717 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 11718 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 11719 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 11720 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 11721 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 11722 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 11723 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 11724 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 11725 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 11726 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 11727 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 11728 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 11729 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 11730 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 11731 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 11732 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 11733 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 11734 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 11735 11736 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000001c) 11737 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) 11738 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) 11739 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 11740 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ 11741 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 11742 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ 11743 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) 11744 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ 11745 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) 11746 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ 11747 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) 11748 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 11749 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 11750 11751 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000020) 11752 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) 11753 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) 11754 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff 11755 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ 11756 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 11757 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ 11758 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) 11759 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ 11760 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) 11761 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ 11762 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) 11763 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff 11764 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 11765 11766 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000030) 11767 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) 11768 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) 11769 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 11770 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ 11771 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 11772 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ 11773 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) 11774 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ 11775 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) 11776 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ 11777 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) 11778 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 11779 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 11780 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 11781 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 11782 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 11783 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 11784 11785 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000034) 11786 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) 11787 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) 11788 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff 11789 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ 11790 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 11791 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ 11792 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) 11793 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ 11794 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) 11795 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ 11796 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) 11797 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 11798 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 11799 11800 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000038) 11801 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) 11802 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) 11803 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 11804 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ 11805 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 11806 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ 11807 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) 11808 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 11809 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 11810 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 11811 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 11812 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 11813 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 11814 11815 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000003c) 11816 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) 11817 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) 11818 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff 11819 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ 11820 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 11821 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ 11822 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) 11823 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ 11824 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) 11825 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ 11826 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) 11827 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff 11828 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 11829 11830 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000040) 11831 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) 11832 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) 11833 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 11834 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ 11835 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 11836 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ 11837 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) 11838 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ 11839 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) 11840 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ 11841 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) 11842 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 11843 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 11844 11845 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000044) 11846 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) 11847 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) 11848 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff 11849 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ 11850 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 11851 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ 11852 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) 11853 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 11854 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 11855 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff 11856 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 11857 11858 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000048) 11859 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) 11860 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) 11861 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 11862 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ 11863 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 11864 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ 11865 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) 11866 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ 11867 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) 11868 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ 11869 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) 11870 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 11871 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 11872 11873 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000004c) 11874 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) 11875 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) 11876 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff 11877 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ 11878 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 11879 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ 11880 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) 11881 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ 11882 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) 11883 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ 11884 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) 11885 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 11886 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 11887 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 11888 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 11889 11890 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000050) 11891 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) 11892 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) 11893 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 11894 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ 11895 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 11896 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ 11897 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) 11898 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ 11899 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) 11900 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ 11901 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) 11902 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 11903 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 11904 11905 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000054) 11906 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) 11907 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) 11908 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff 11909 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ 11910 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 11911 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ 11912 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) 11913 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ 11914 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) 11915 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 11916 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) 11917 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 11918 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 11919 11920 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000058) 11921 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) 11922 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) 11923 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 11924 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ 11925 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 11926 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ 11927 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) 11928 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ 11929 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) 11930 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ 11931 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) 11932 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 11933 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 11934 11935 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000005c) 11936 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) 11937 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) 11938 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff 11939 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ 11940 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 11941 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ 11942 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) 11943 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ 11944 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) 11945 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ 11946 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) 11947 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 11948 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 11949 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 11950 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 11951 11952 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000060) 11953 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) 11954 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) 11955 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff 11956 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ 11957 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 11958 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ 11959 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) 11960 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ 11961 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) 11962 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ 11963 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) 11964 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 11965 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 11966 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff 11967 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 11968 11969 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000064) 11970 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) 11971 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) 11972 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 11973 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ 11974 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 11975 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ 11976 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) 11977 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 11978 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 11979 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff 11980 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 11981 11982 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000068) 11983 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) 11984 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) 11985 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff 11986 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ 11987 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 11988 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ 11989 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) 11990 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ 11991 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) 11992 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ 11993 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) 11994 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 11995 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 11996 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 11997 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 11998 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 11999 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 12000 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 12001 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 12002 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 12003 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 12004 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 12005 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 12006 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 12007 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 12008 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 12009 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 12010 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 12011 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 12012 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 12013 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 12014 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 12015 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 12016 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 12017 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 12018 12019 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000006c) 12020 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) 12021 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) 12022 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 12023 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ 12024 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 12025 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ 12026 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) 12027 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ 12028 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) 12029 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ 12030 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) 12031 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 12032 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 12033 12034 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000070) 12035 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) 12036 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) 12037 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff 12038 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ 12039 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 12040 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ 12041 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) 12042 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ 12043 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) 12044 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ 12045 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) 12046 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff 12047 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 12048 12049 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000007c) 12050 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) 12051 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) 12052 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 12053 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ 12054 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 12055 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ 12056 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) 12057 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ 12058 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) 12059 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ 12060 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) 12061 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 12062 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 12063 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 12064 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 12065 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 12066 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 12067 12068 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000080) 12069 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) 12070 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) 12071 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 12072 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ 12073 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 12074 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ 12075 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) 12076 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 12077 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 12078 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 12079 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 12080 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff 12081 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 12082 12083 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000084) 12084 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) 12085 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) 12086 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff 12087 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ 12088 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 12089 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ 12090 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) 12091 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ 12092 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) 12093 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ 12094 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) 12095 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff 12096 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 12097 12098 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a0) 12099 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) 12100 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) 12101 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 12102 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ 12103 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 12104 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ 12105 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) 12106 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ 12107 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) 12108 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ 12109 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) 12110 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 12111 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 12112 12113 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a4) 12114 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) 12115 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) 12116 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff 12117 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ 12118 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 12119 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ 12120 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) 12121 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ 12122 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) 12123 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ 12124 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) 12125 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 12126 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 12127 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 12128 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 12129 12130 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a8) 12131 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) 12132 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) 12133 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 12134 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ 12135 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 12136 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ 12137 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) 12138 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ 12139 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) 12140 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ 12141 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) 12142 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 12143 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 12144 12145 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000ac) 12146 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) 12147 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) 12148 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff 12149 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ 12150 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 12151 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ 12152 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) 12153 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ 12154 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) 12155 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ 12156 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) 12157 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff 12158 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 12159 12160 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b0) 12161 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) 12162 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) 12163 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff 12164 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ 12165 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 12166 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ 12167 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) 12168 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ 12169 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) 12170 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ 12171 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) 12172 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 12173 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 12174 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff 12175 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 12176 12177 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b4) 12178 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) 12179 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) 12180 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f 12181 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ 12182 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 12183 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ 12184 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) 12185 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ 12186 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) 12187 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ 12188 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) 12189 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 12190 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 12191 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 12192 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 12193 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 12194 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 12195 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 12196 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 12197 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 12198 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 12199 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 12200 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 12201 12202 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b8) 12203 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) 12204 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) 12205 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf 12206 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ 12207 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 12208 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ 12209 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) 12210 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ 12211 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) 12212 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ 12213 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) 12214 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 12215 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 12216 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 12217 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 12218 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 12219 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 12220 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 12221 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 12222 12223 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000400) 12224 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) 12225 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) 12226 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff 12227 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ 12228 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 12229 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ 12230 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) 12231 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ 12232 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) 12233 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ 12234 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) 12235 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff 12236 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 12237 12238 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000404) 12239 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) 12240 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) 12241 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff 12242 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ 12243 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 12244 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ 12245 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) 12246 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ 12247 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) 12248 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ 12249 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) 12250 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff 12251 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 12252 12253 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000408) 12254 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) 12255 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) 12256 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff 12257 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ 12258 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 12259 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ 12260 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) 12261 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ 12262 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) 12263 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ 12264 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) 12265 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff 12266 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 12267 12268 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000040c) 12269 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) 12270 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) 12271 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff 12272 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ 12273 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 12274 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ 12275 in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) 12276 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ 12277 out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) 12278 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ 12279 out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) 12280 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff 12281 #define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 12282 12283 #define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00018000) 12284 #define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00018000) 12285 #define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00018000 12286 12287 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000000) 12288 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000000) 12289 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000000) 12290 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff 12291 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN \ 12292 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) 12293 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(m) \ 12294 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, m) 12295 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 12296 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 12297 12298 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000004) 12299 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000004) 12300 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000004) 12301 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xff 12302 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN \ 12303 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) 12304 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(m) \ 12305 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, m) 12306 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xff 12307 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 12308 12309 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000008) 12310 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000008) 12311 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000008) 12312 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfff 12313 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN \ 12314 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) 12315 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(m) \ 12316 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, m) 12317 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 12318 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 12319 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 12320 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 12321 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf 12322 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 12323 12324 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000000c) 12325 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000000c) 12326 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000000c) 12327 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1 12328 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN \ 12329 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) 12330 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(m) \ 12331 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, m) 12332 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(v) \ 12333 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,v) 12334 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(m,v) \ 12335 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN) 12336 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 12337 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 12338 12339 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000010) 12340 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000010) 12341 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000010) 12342 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff 12343 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN \ 12344 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) 12345 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(m) \ 12346 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, m) 12347 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(v) \ 12348 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,v) 12349 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(m,v) \ 12350 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN) 12351 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 12352 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 12353 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800 12354 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 12355 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 12356 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 12357 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 12358 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 12359 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 12360 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 12361 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 12362 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 12363 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 12364 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 12365 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 12366 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 12367 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 12368 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 12369 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 12370 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 12371 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 12372 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 12373 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 12374 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 12375 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 12376 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 12377 12378 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000014) 12379 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000014) 12380 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000014) 12381 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101 12382 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN \ 12383 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) 12384 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(m) \ 12385 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, m) 12386 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000 12387 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 12388 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000 12389 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 12390 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100 12391 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 12392 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1 12393 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 12394 12395 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000018) 12396 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000018) 12397 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000018) 12398 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3f 12399 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN \ 12400 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) 12401 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(m) \ 12402 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, m) 12403 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000 12404 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 12405 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00 12406 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 12407 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3f 12408 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 12409 12410 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000001c) 12411 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000001c) 12412 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000001c) 12413 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 12414 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN \ 12415 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) 12416 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(m) \ 12417 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, m) 12418 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(v) \ 12419 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,v) 12420 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(m,v) \ 12421 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN) 12422 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 12423 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 12424 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 12425 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 12426 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 12427 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 12428 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f 12429 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 12430 12431 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000020) 12432 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000020) 12433 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000020) 12434 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 12435 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN \ 12436 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) 12437 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(m) \ 12438 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, m) 12439 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(v) \ 12440 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,v) 12441 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(m,v) \ 12442 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN) 12443 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 12444 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 12445 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 12446 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 12447 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 12448 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 12449 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f 12450 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 12451 12452 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000024) 12453 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000024) 12454 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000024) 12455 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xfffffff 12456 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN \ 12457 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) 12458 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(m) \ 12459 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, m) 12460 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(v) \ 12461 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,v) 12462 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(m,v) \ 12463 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN) 12464 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000 12465 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 12466 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000 12467 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 12468 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000 12469 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 12470 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000 12471 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 12472 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000 12473 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 12474 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000 12475 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 12476 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000 12477 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 12478 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00 12479 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 12480 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1fe 12481 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 12482 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1 12483 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 12484 12485 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000028) 12486 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000028) 12487 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000028) 12488 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 12489 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN \ 12490 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) 12491 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(m) \ 12492 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, m) 12493 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(v) \ 12494 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,v) 12495 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(m,v) \ 12496 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN) 12497 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 12498 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 12499 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1 12500 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 12501 12502 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000002c) 12503 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000002c) 12504 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000002c) 12505 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffff 12506 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN \ 12507 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) 12508 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(m) \ 12509 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, m) 12510 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffff 12511 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 12512 12513 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000030) 12514 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000030) 12515 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000030) 12516 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff 12517 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN \ 12518 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) 12519 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(m) \ 12520 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, m) 12521 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 12522 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 12523 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff 12524 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 12525 12526 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000034) 12527 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000034) 12528 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000034) 12529 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xfffff 12530 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN \ 12531 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) 12532 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(m) \ 12533 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, m) 12534 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(v) \ 12535 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,v) 12536 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(m,v) \ 12537 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN) 12538 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 12539 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 12540 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 12541 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 12542 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff 12543 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 12544 12545 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000038) 12546 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000038) 12547 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000038) 12548 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xfffff 12549 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN \ 12550 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) 12551 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(m) \ 12552 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, m) 12553 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(v) \ 12554 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,v) 12555 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(m,v) \ 12556 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN) 12557 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 12558 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 12559 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 12560 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 12561 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff 12562 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 12563 12564 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000003c) 12565 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000003c) 12566 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000003c) 12567 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 12568 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN \ 12569 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 12570 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(m) \ 12571 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, m) 12572 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(v) \ 12573 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,v) 12574 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ 12575 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN) 12576 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 12577 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 12578 12579 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000040) 12580 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000040) 12581 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000040) 12582 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 12583 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN \ 12584 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 12585 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(m) \ 12586 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, m) 12587 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(v) \ 12588 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,v) 12589 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ 12590 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN) 12591 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 12592 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 12593 12594 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000044) 12595 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000044) 12596 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000044) 12597 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 12598 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN \ 12599 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 12600 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(m) \ 12601 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, m) 12602 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(v) \ 12603 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,v) 12604 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ 12605 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN) 12606 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 12607 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 12608 12609 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000048) 12610 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000048) 12611 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000048) 12612 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 12613 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN \ 12614 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 12615 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(m) \ 12616 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, m) 12617 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(v) \ 12618 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,v) 12619 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ 12620 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN) 12621 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 12622 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 12623 12624 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000004c) 12625 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000004c) 12626 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000004c) 12627 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1ffffff 12628 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN \ 12629 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) 12630 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(m) \ 12631 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, m) 12632 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(v) \ 12633 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,v) 12634 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(m,v) \ 12635 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN) 12636 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000 12637 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 12638 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000 12639 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc 12640 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfff 12641 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 12642 12643 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000050) 12644 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000050) 12645 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000050) 12646 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfff 12647 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN \ 12648 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) 12649 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(m) \ 12650 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, m) 12651 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(v) \ 12652 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,v) 12653 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(m,v) \ 12654 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN) 12655 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfff 12656 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 12657 12658 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000054) 12659 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000054) 12660 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000054) 12661 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xffffff 12662 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN \ 12663 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) 12664 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_INM(m) \ 12665 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, m) 12666 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(v) \ 12667 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,v) 12668 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(m,v) \ 12669 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN) 12670 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000 12671 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc 12672 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfff 12673 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 12674 12675 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000058) 12676 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000058) 12677 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000058) 12678 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1ffffff 12679 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN \ 12680 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) 12681 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(m) \ 12682 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, m) 12683 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(v) \ 12684 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,v) 12685 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(m,v) \ 12686 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN) 12687 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000 12688 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 12689 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000 12690 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc 12691 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfff 12692 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 12693 12694 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000005c) 12695 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000005c) 12696 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000005c) 12697 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfff 12698 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN \ 12699 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) 12700 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(m) \ 12701 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, m) 12702 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(v) \ 12703 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,v) 12704 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(m,v) \ 12705 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN) 12706 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfff 12707 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 12708 12709 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000060) 12710 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000060) 12711 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000060) 12712 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff 12713 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN \ 12714 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) 12715 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(m) \ 12716 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, m) 12717 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(v) \ 12718 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,v) 12719 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(m,v) \ 12720 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN) 12721 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff 12722 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 12723 12724 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000064) 12725 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000064) 12726 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000064) 12727 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xffffffff 12728 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN \ 12729 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) 12730 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(m) \ 12731 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, m) 12732 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(v) \ 12733 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,v) 12734 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(m,v) \ 12735 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN) 12736 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xffffffff 12737 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 12738 12739 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000068) 12740 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000068) 12741 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000068) 12742 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1 12743 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN \ 12744 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK) 12745 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(m) \ 12746 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, m) 12747 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(v) \ 12748 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,v) 12749 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(m,v) \ 12750 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN) 12751 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1 12752 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0x0 12753 12754 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000006c) 12755 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000006c) 12756 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000006c) 12757 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff 12758 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN \ 12759 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) 12760 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(m) \ 12761 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, m) 12762 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(v) \ 12763 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,v) 12764 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(m,v) \ 12765 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN) 12766 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff 12767 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0 12768 12769 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000070) 12770 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000070) 12771 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000070) 12772 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xffffffff 12773 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN \ 12774 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) 12775 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(m) \ 12776 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, m) 12777 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(v) \ 12778 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,v) 12779 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(m,v) \ 12780 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN) 12781 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xffffffff 12782 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0 12783 12784 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000074) 12785 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000074) 12786 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000074) 12787 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1 12788 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN \ 12789 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK) 12790 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(m) \ 12791 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, m) 12792 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(v) \ 12793 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,v) 12794 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(m,v) \ 12795 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN) 12796 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1 12797 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0x0 12798 12799 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000078) 12800 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000078) 12801 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000078) 12802 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff 12803 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN \ 12804 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) 12805 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(m) \ 12806 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, m) 12807 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff 12808 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 12809 12810 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000007c) 12811 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000007c) 12812 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000007c) 12813 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff 12814 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN \ 12815 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) 12816 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(m) \ 12817 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, m) 12818 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff 12819 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 12820 12821 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000080) 12822 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000080) 12823 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000080) 12824 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff 12825 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN \ 12826 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) 12827 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(m) \ 12828 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, m) 12829 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff 12830 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 12831 12832 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000084) 12833 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000084) 12834 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000084) 12835 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff 12836 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN \ 12837 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) 12838 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(m) \ 12839 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, m) 12840 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff 12841 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 12842 12843 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000088) 12844 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000088) 12845 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000088) 12846 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdffff 12847 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN \ 12848 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK) 12849 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(m) \ 12850 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, m) 12851 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(v) \ 12852 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,v) 12853 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(m,v) \ 12854 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN) 12855 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000 12856 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 0x1f 12857 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000 12858 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 0x1e 12859 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000 12860 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 0x12 12861 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000 12862 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 0x10 12863 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000 12864 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 0xc 12865 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfff 12866 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0x0 12867 12868 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000008c) 12869 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000008c) 12870 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000008c) 12871 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xffffff 12872 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN \ 12873 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK) 12874 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(m) \ 12875 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, m) 12876 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(v) \ 12877 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,v) 12878 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(m,v) \ 12879 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN) 12880 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000 12881 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 0xc 12882 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfff 12883 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0x0 12884 12885 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000090) 12886 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000090) 12887 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000090) 12888 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fff 12889 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN \ 12890 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK) 12891 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(m) \ 12892 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, m) 12893 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(v) \ 12894 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,v) 12895 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(m,v) \ 12896 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN) 12897 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000 12898 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 0xc 12899 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfff 12900 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0x0 12901 12902 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000094) 12903 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000094) 12904 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000094) 12905 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfff 12906 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN \ 12907 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) 12908 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(m) \ 12909 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, m) 12910 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(v) \ 12911 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,v) 12912 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(m,v) \ 12913 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN) 12914 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfff 12915 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0x0 12916 12917 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000098) 12918 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000098) 12919 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000098) 12920 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 12921 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN \ 12922 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK) 12923 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(m) \ 12924 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, m) 12925 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xffffffff 12926 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0x0 12927 12928 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000009c) 12929 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000009c) 12930 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000009c) 12931 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff 12932 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN \ 12933 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) 12934 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(m) \ 12935 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, m) 12936 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(v) \ 12937 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,v) 12938 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(m,v) \ 12939 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN) 12940 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff 12941 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0x0 12942 12943 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a0) 12944 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a0) 12945 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a0) 12946 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK 0xf00ff 12947 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN \ 12948 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK) 12949 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(m) \ 12950 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, m) 12951 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(v) \ 12952 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,v) 12953 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(m,v) \ 12954 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN) 12955 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK 0xf0000 12956 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT 0x10 12957 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc0 12958 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT 0x6 12959 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK 0x30 12960 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT 0x4 12961 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc 12962 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT 0x2 12963 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK 0x3 12964 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT 0x0 12965 12966 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a4) 12967 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a4) 12968 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a4) 12969 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK 0x10fff 12970 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN \ 12971 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK) 12972 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(m) \ 12973 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, m) 12974 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(v) \ 12975 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,v) 12976 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(m,v) \ 12977 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN) 12978 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK 0x10000 12979 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT 0x10 12980 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK 0xfff 12981 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT 0x0 12982 12983 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a8) 12984 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a8) 12985 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a8) 12986 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK 0x10fff 12987 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN \ 12988 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK) 12989 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(m) \ 12990 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, m) 12991 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK 0x10000 12992 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT 0x10 12993 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK 0xfff 12994 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT 0x0 12995 12996 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000ac) 12997 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000ac) 12998 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000ac) 12999 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK 0x300ff 13000 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN \ 13001 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK) 13002 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(m) \ 13003 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, m) 13004 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(v) \ 13005 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,v) 13006 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(m,v) \ 13007 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN) 13008 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_BMSK 0x20000 13009 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_SHFT 0x11 13010 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK 0x10000 13011 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT 0x10 13012 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK 0xe0 13013 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT 0x5 13014 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK 0x1c 13015 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT 0x2 13016 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK 0x2 13017 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT 0x1 13018 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK 0x1 13019 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT 0x0 13020 13021 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b0) 13022 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b0) 13023 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b0) 13024 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK 0xffffffff 13025 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN \ 13026 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK) 13027 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(m) \ 13028 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, m) 13029 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK 0xffffffff 13030 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT 0x0 13031 13032 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b4) 13033 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b4) 13034 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b4) 13035 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK 0xffffffff 13036 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN \ 13037 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK) 13038 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(m) \ 13039 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, m) 13040 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK 0xffffffff 13041 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT 0x0 13042 13043 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b8) 13044 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b8) 13045 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b8) 13046 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK 0xffffffff 13047 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN \ 13048 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK) 13049 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(m) \ 13050 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, m) 13051 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK 0xffffffff 13052 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT 0x0 13053 13054 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000bc) 13055 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000bc) 13056 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000bc) 13057 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK 0xffffffff 13058 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN \ 13059 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK) 13060 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(m) \ 13061 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, m) 13062 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK 0xffffffff 13063 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT 0x0 13064 13065 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000c0) 13066 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c0) 13067 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c0) 13068 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK 0xffffffff 13069 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN \ 13070 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK) 13071 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(m) \ 13072 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, m) 13073 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK 0xffffffff 13074 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT 0x0 13075 13076 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000c4) 13077 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c4) 13078 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c4) 13079 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK 0x3 13080 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN \ 13081 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK) 13082 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(m) \ 13083 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, m) 13084 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK 0x2 13085 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT 0x1 13086 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK 0x1 13087 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT 0x0 13088 13089 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000400) 13090 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000400) 13091 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000400) 13092 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100ff 13093 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN \ 13094 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) 13095 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(m) \ 13096 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, m) 13097 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(v) \ 13098 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,v) 13099 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(m,v) \ 13100 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN) 13101 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 13102 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x10 13103 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xff 13104 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 13105 13106 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000404) 13107 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000404) 13108 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000404) 13109 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff 13110 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN \ 13111 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) 13112 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(m) \ 13113 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, m) 13114 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(v) \ 13115 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,v) 13116 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(m,v) \ 13117 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN) 13118 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 13119 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 13120 13121 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000408) 13122 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000408) 13123 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000408) 13124 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff 13125 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN \ 13126 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) 13127 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(m) \ 13128 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, m) 13129 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(v) \ 13130 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,v) 13131 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(m,v) \ 13132 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN) 13133 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 13134 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 13135 13136 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000040c) 13137 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000040c) 13138 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000040c) 13139 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff 13140 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN \ 13141 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) 13142 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(m) \ 13143 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, m) 13144 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 13145 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 13146 13147 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000410) 13148 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000410) 13149 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000410) 13150 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xff 13151 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN \ 13152 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) 13153 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(m) \ 13154 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, m) 13155 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xff 13156 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 13157 13158 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000414) 13159 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000414) 13160 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000414) 13161 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 13162 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN \ 13163 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 13164 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(m) \ 13165 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, m) 13166 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(v) \ 13167 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,v) 13168 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(m,v) \ 13169 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN) 13170 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 13171 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 13172 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc 13173 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 13174 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 13175 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 13176 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 13177 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 13178 13179 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000418) 13180 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000418) 13181 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000418) 13182 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1 13183 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN \ 13184 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) 13185 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(m) \ 13186 in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, m) 13187 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(v) \ 13188 out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,v) 13189 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(m,v) \ 13190 out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN) 13191 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 13192 #define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 13193 13194 #endif 13195