1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _TX_FES_SETUP_H_ 19*5113495bSYour Name #define _TX_FES_SETUP_H_ 20*5113495bSYour Name 21*5113495bSYour Name #define NUM_OF_DWORDS_TX_FES_SETUP 10 22*5113495bSYour Name 23*5113495bSYour Name struct tx_fes_setup { 24*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25*5113495bSYour Name uint32_t schedule_id : 32; 26*5113495bSYour Name uint32_t fes_in_11ax_trigger_response_config : 1, 27*5113495bSYour Name bo_based_tid_aggregation_limit : 4, 28*5113495bSYour Name __reserved_g_0005 : 1, 29*5113495bSYour Name expect_i2r_lmr : 1, 30*5113495bSYour Name transmit_start_reason : 3, 31*5113495bSYour Name use_alt_power_sr : 1, 32*5113495bSYour Name static_2_pwr_mode_status : 1, 33*5113495bSYour Name obss_srg_opport_transmit_status : 1, 34*5113495bSYour Name srp_based_transmit_status : 1, 35*5113495bSYour Name obss_pd_based_transmit_status : 1, 36*5113495bSYour Name puncture_from_all_allowed_modes : 1, 37*5113495bSYour Name schedule_cmd_ring_id : 5, 38*5113495bSYour Name fes_control_mode : 2, 39*5113495bSYour Name number_of_users : 6, 40*5113495bSYour Name mu_type : 1, 41*5113495bSYour Name ofdma_triggered_response : 1, 42*5113495bSYour Name response_to_response_cmd : 1; 43*5113495bSYour Name uint32_t schedule_try : 4, 44*5113495bSYour Name ndp_frame : 2, 45*5113495bSYour Name txbf : 1, 46*5113495bSYour Name allow_txop_exceed_in_1st_pkt : 1, 47*5113495bSYour Name ignore_bw_available : 1, 48*5113495bSYour Name ignore_tbtt : 1, 49*5113495bSYour Name static_bandwidth : 3, 50*5113495bSYour Name set_txop_duration_all_ones : 1, 51*5113495bSYour Name transmission_contains_mu_rts : 1, 52*5113495bSYour Name bw_restricted_frames_embedded : 1, 53*5113495bSYour Name ast_index : 16; 54*5113495bSYour Name uint32_t cv_id : 8, 55*5113495bSYour Name trigger_resp_txpdu_ppdu_boundary : 2, 56*5113495bSYour Name rxpcu_setup_complete_present : 1, 57*5113495bSYour Name rbo_must_have_data_user_limit : 4, 58*5113495bSYour Name mu_ndp : 1, 59*5113495bSYour Name bf_type : 2, 60*5113495bSYour Name cbf_nc_index_mask : 1, 61*5113495bSYour Name cbf_nc_index : 3, 62*5113495bSYour Name cbf_nr_index_mask : 1, 63*5113495bSYour Name cbf_nr_index : 3, 64*5113495bSYour Name secure___reserved_g_0005_ista : 1, 65*5113495bSYour Name ndpa : 1, 66*5113495bSYour Name wait_sifs : 2, 67*5113495bSYour Name cbf_feedback_type_mask : 1, 68*5113495bSYour Name cbf_feedback_type : 1; 69*5113495bSYour Name uint32_t cbf_sounding_token : 6, 70*5113495bSYour Name cbf_sounding_token_mask : 1, 71*5113495bSYour Name cbf_bw_mask : 1, 72*5113495bSYour Name cbf_bw : 3, 73*5113495bSYour Name use_static_bw : 1, 74*5113495bSYour Name coex_nack_count : 5, 75*5113495bSYour Name sch_tx_burst_ongoing : 1, 76*5113495bSYour Name gen_tqm_update_mpdu_count_tlv : 1, 77*5113495bSYour Name rts_tx_over___reserved_g_0016 : 1, 78*5113495bSYour Name reserved_4a : 3, 79*5113495bSYour Name optimal_bw_retry_count : 4, 80*5113495bSYour Name fes_continuation_ratio_threshold : 5; 81*5113495bSYour Name uint32_t transmit_cca_bitmap : 32; 82*5113495bSYour Name uint32_t tb___reserved_g_0005 : 1, 83*5113495bSYour Name __reserved_g_0005_trigger_subtype : 4, 84*5113495bSYour Name min_cts2self_count : 4, 85*5113495bSYour Name max_cts2self_count : 4, 86*5113495bSYour Name wifi_radar_enable : 1, 87*5113495bSYour Name reserved_6a : 1, 88*5113495bSYour Name wait_for_chksum_done : 1, 89*5113495bSYour Name reserved_6b : 15, 90*5113495bSYour Name enable_hw_qos_null : 1; 91*5113495bSYour Name uint32_t monitor_override_sta_31_0 : 32; 92*5113495bSYour Name uint32_t monitor_override_sta_36_32 : 5, 93*5113495bSYour Name enable_qos_null_switch_for_eosp : 1, 94*5113495bSYour Name reserved_8a : 26; 95*5113495bSYour Name uint32_t fw2sw_info : 32; 96*5113495bSYour Name #else 97*5113495bSYour Name uint32_t schedule_id : 32; 98*5113495bSYour Name uint32_t response_to_response_cmd : 1, 99*5113495bSYour Name ofdma_triggered_response : 1, 100*5113495bSYour Name mu_type : 1, 101*5113495bSYour Name number_of_users : 6, 102*5113495bSYour Name fes_control_mode : 2, 103*5113495bSYour Name schedule_cmd_ring_id : 5, 104*5113495bSYour Name puncture_from_all_allowed_modes : 1, 105*5113495bSYour Name obss_pd_based_transmit_status : 1, 106*5113495bSYour Name srp_based_transmit_status : 1, 107*5113495bSYour Name obss_srg_opport_transmit_status : 1, 108*5113495bSYour Name static_2_pwr_mode_status : 1, 109*5113495bSYour Name use_alt_power_sr : 1, 110*5113495bSYour Name transmit_start_reason : 3, 111*5113495bSYour Name expect_i2r_lmr : 1, 112*5113495bSYour Name __reserved_g_0005 : 1, 113*5113495bSYour Name bo_based_tid_aggregation_limit : 4, 114*5113495bSYour Name fes_in_11ax_trigger_response_config : 1; 115*5113495bSYour Name uint32_t ast_index : 16, 116*5113495bSYour Name bw_restricted_frames_embedded : 1, 117*5113495bSYour Name transmission_contains_mu_rts : 1, 118*5113495bSYour Name set_txop_duration_all_ones : 1, 119*5113495bSYour Name static_bandwidth : 3, 120*5113495bSYour Name ignore_tbtt : 1, 121*5113495bSYour Name ignore_bw_available : 1, 122*5113495bSYour Name allow_txop_exceed_in_1st_pkt : 1, 123*5113495bSYour Name txbf : 1, 124*5113495bSYour Name ndp_frame : 2, 125*5113495bSYour Name schedule_try : 4; 126*5113495bSYour Name uint32_t cbf_feedback_type : 1, 127*5113495bSYour Name cbf_feedback_type_mask : 1, 128*5113495bSYour Name wait_sifs : 2, 129*5113495bSYour Name ndpa : 1, 130*5113495bSYour Name secure___reserved_g_0005_ista : 1, 131*5113495bSYour Name cbf_nr_index : 3, 132*5113495bSYour Name cbf_nr_index_mask : 1, 133*5113495bSYour Name cbf_nc_index : 3, 134*5113495bSYour Name cbf_nc_index_mask : 1, 135*5113495bSYour Name bf_type : 2, 136*5113495bSYour Name mu_ndp : 1, 137*5113495bSYour Name rbo_must_have_data_user_limit : 4, 138*5113495bSYour Name rxpcu_setup_complete_present : 1, 139*5113495bSYour Name trigger_resp_txpdu_ppdu_boundary : 2, 140*5113495bSYour Name cv_id : 8; 141*5113495bSYour Name uint32_t fes_continuation_ratio_threshold : 5, 142*5113495bSYour Name optimal_bw_retry_count : 4, 143*5113495bSYour Name reserved_4a : 3, 144*5113495bSYour Name rts_tx_over___reserved_g_0016 : 1, 145*5113495bSYour Name gen_tqm_update_mpdu_count_tlv : 1, 146*5113495bSYour Name sch_tx_burst_ongoing : 1, 147*5113495bSYour Name coex_nack_count : 5, 148*5113495bSYour Name use_static_bw : 1, 149*5113495bSYour Name cbf_bw : 3, 150*5113495bSYour Name cbf_bw_mask : 1, 151*5113495bSYour Name cbf_sounding_token_mask : 1, 152*5113495bSYour Name cbf_sounding_token : 6; 153*5113495bSYour Name uint32_t transmit_cca_bitmap : 32; 154*5113495bSYour Name uint32_t enable_hw_qos_null : 1, 155*5113495bSYour Name reserved_6b : 15, 156*5113495bSYour Name wait_for_chksum_done : 1, 157*5113495bSYour Name reserved_6a : 1, 158*5113495bSYour Name wifi_radar_enable : 1, 159*5113495bSYour Name max_cts2self_count : 4, 160*5113495bSYour Name min_cts2self_count : 4, 161*5113495bSYour Name __reserved_g_0005_trigger_subtype : 4, 162*5113495bSYour Name tb___reserved_g_0005 : 1; 163*5113495bSYour Name uint32_t monitor_override_sta_31_0 : 32; 164*5113495bSYour Name uint32_t reserved_8a : 26, 165*5113495bSYour Name enable_qos_null_switch_for_eosp : 1, 166*5113495bSYour Name monitor_override_sta_36_32 : 5; 167*5113495bSYour Name uint32_t fw2sw_info : 32; 168*5113495bSYour Name #endif 169*5113495bSYour Name }; 170*5113495bSYour Name 171*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000 172*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_ID_LSB 0 173*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_ID_MSB 31 174*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff 175*5113495bSYour Name 176*5113495bSYour Name #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 177*5113495bSYour Name #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0 178*5113495bSYour Name #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0 179*5113495bSYour Name #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001 180*5113495bSYour Name 181*5113495bSYour Name #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004 182*5113495bSYour Name #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1 183*5113495bSYour Name #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4 184*5113495bSYour Name #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e 185*5113495bSYour Name 186*5113495bSYour Name #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004 187*5113495bSYour Name #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6 188*5113495bSYour Name #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6 189*5113495bSYour Name #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040 190*5113495bSYour Name 191*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004 192*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7 193*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9 194*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380 195*5113495bSYour Name 196*5113495bSYour Name #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004 197*5113495bSYour Name #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10 198*5113495bSYour Name #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10 199*5113495bSYour Name #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400 200*5113495bSYour Name 201*5113495bSYour Name #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004 202*5113495bSYour Name #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11 203*5113495bSYour Name #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11 204*5113495bSYour Name #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800 205*5113495bSYour Name 206*5113495bSYour Name #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004 207*5113495bSYour Name #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12 208*5113495bSYour Name #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12 209*5113495bSYour Name #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000 210*5113495bSYour Name 211*5113495bSYour Name #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 212*5113495bSYour Name #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13 213*5113495bSYour Name #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13 214*5113495bSYour Name #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000 215*5113495bSYour Name 216*5113495bSYour Name #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 217*5113495bSYour Name #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14 218*5113495bSYour Name #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14 219*5113495bSYour Name #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000 220*5113495bSYour Name 221*5113495bSYour Name #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004 222*5113495bSYour Name #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15 223*5113495bSYour Name #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15 224*5113495bSYour Name #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000 225*5113495bSYour Name 226*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 227*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16 228*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20 229*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 230*5113495bSYour Name 231*5113495bSYour Name #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004 232*5113495bSYour Name #define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21 233*5113495bSYour Name #define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22 234*5113495bSYour Name #define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000 235*5113495bSYour Name 236*5113495bSYour Name #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004 237*5113495bSYour Name #define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23 238*5113495bSYour Name #define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28 239*5113495bSYour Name #define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000 240*5113495bSYour Name 241*5113495bSYour Name #define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004 242*5113495bSYour Name #define TX_FES_SETUP_MU_TYPE_LSB 29 243*5113495bSYour Name #define TX_FES_SETUP_MU_TYPE_MSB 29 244*5113495bSYour Name #define TX_FES_SETUP_MU_TYPE_MASK 0x20000000 245*5113495bSYour Name 246*5113495bSYour Name #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004 247*5113495bSYour Name #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30 248*5113495bSYour Name #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30 249*5113495bSYour Name #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000 250*5113495bSYour Name 251*5113495bSYour Name #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004 252*5113495bSYour Name #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31 253*5113495bSYour Name #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31 254*5113495bSYour Name #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000 255*5113495bSYour Name 256*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008 257*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 258*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 259*5113495bSYour Name #define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f 260*5113495bSYour Name 261*5113495bSYour Name #define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008 262*5113495bSYour Name #define TX_FES_SETUP_NDP_FRAME_LSB 4 263*5113495bSYour Name #define TX_FES_SETUP_NDP_FRAME_MSB 5 264*5113495bSYour Name #define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030 265*5113495bSYour Name 266*5113495bSYour Name #define TX_FES_SETUP_TXBF_OFFSET 0x00000008 267*5113495bSYour Name #define TX_FES_SETUP_TXBF_LSB 6 268*5113495bSYour Name #define TX_FES_SETUP_TXBF_MSB 6 269*5113495bSYour Name #define TX_FES_SETUP_TXBF_MASK 0x00000040 270*5113495bSYour Name 271*5113495bSYour Name #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008 272*5113495bSYour Name #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 273*5113495bSYour Name #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 274*5113495bSYour Name #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080 275*5113495bSYour Name 276*5113495bSYour Name #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008 277*5113495bSYour Name #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 278*5113495bSYour Name #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 279*5113495bSYour Name #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100 280*5113495bSYour Name 281*5113495bSYour Name #define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008 282*5113495bSYour Name #define TX_FES_SETUP_IGNORE_TBTT_LSB 9 283*5113495bSYour Name #define TX_FES_SETUP_IGNORE_TBTT_MSB 9 284*5113495bSYour Name #define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200 285*5113495bSYour Name 286*5113495bSYour Name #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008 287*5113495bSYour Name #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 288*5113495bSYour Name #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 289*5113495bSYour Name #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00 290*5113495bSYour Name 291*5113495bSYour Name #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008 292*5113495bSYour Name #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 293*5113495bSYour Name #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 294*5113495bSYour Name #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000 295*5113495bSYour Name 296*5113495bSYour Name #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008 297*5113495bSYour Name #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 298*5113495bSYour Name #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 299*5113495bSYour Name #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000 300*5113495bSYour Name 301*5113495bSYour Name #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008 302*5113495bSYour Name #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 303*5113495bSYour Name #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 304*5113495bSYour Name #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000 305*5113495bSYour Name 306*5113495bSYour Name #define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008 307*5113495bSYour Name #define TX_FES_SETUP_AST_INDEX_LSB 16 308*5113495bSYour Name #define TX_FES_SETUP_AST_INDEX_MSB 31 309*5113495bSYour Name #define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000 310*5113495bSYour Name 311*5113495bSYour Name #define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c 312*5113495bSYour Name #define TX_FES_SETUP_CV_ID_LSB 0 313*5113495bSYour Name #define TX_FES_SETUP_CV_ID_MSB 7 314*5113495bSYour Name #define TX_FES_SETUP_CV_ID_MASK 0x000000ff 315*5113495bSYour Name 316*5113495bSYour Name #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c 317*5113495bSYour Name #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8 318*5113495bSYour Name #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9 319*5113495bSYour Name #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300 320*5113495bSYour Name 321*5113495bSYour Name #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c 322*5113495bSYour Name #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10 323*5113495bSYour Name #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10 324*5113495bSYour Name #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400 325*5113495bSYour Name 326*5113495bSYour Name #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c 327*5113495bSYour Name #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11 328*5113495bSYour Name #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14 329*5113495bSYour Name #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800 330*5113495bSYour Name 331*5113495bSYour Name #define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c 332*5113495bSYour Name #define TX_FES_SETUP_MU_NDP_LSB 15 333*5113495bSYour Name #define TX_FES_SETUP_MU_NDP_MSB 15 334*5113495bSYour Name #define TX_FES_SETUP_MU_NDP_MASK 0x00008000 335*5113495bSYour Name 336*5113495bSYour Name #define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c 337*5113495bSYour Name #define TX_FES_SETUP_BF_TYPE_LSB 16 338*5113495bSYour Name #define TX_FES_SETUP_BF_TYPE_MSB 17 339*5113495bSYour Name #define TX_FES_SETUP_BF_TYPE_MASK 0x00030000 340*5113495bSYour Name 341*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c 342*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18 343*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18 344*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000 345*5113495bSYour Name 346*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c 347*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_LSB 19 348*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MSB 21 349*5113495bSYour Name #define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000 350*5113495bSYour Name 351*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c 352*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22 353*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22 354*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000 355*5113495bSYour Name 356*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c 357*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_LSB 23 358*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MSB 25 359*5113495bSYour Name #define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000 360*5113495bSYour Name 361*5113495bSYour Name #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c 362*5113495bSYour Name #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26 363*5113495bSYour Name #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26 364*5113495bSYour Name #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000 365*5113495bSYour Name 366*5113495bSYour Name #define TX_FES_SETUP_NDPA_OFFSET 0x0000000c 367*5113495bSYour Name #define TX_FES_SETUP_NDPA_LSB 27 368*5113495bSYour Name #define TX_FES_SETUP_NDPA_MSB 27 369*5113495bSYour Name #define TX_FES_SETUP_NDPA_MASK 0x08000000 370*5113495bSYour Name 371*5113495bSYour Name #define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c 372*5113495bSYour Name #define TX_FES_SETUP_WAIT_SIFS_LSB 28 373*5113495bSYour Name #define TX_FES_SETUP_WAIT_SIFS_MSB 29 374*5113495bSYour Name #define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000 375*5113495bSYour Name 376*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c 377*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30 378*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30 379*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000 380*5113495bSYour Name 381*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c 382*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31 383*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31 384*5113495bSYour Name #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000 385*5113495bSYour Name 386*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010 387*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 388*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 389*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f 390*5113495bSYour Name 391*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010 392*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 393*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 394*5113495bSYour Name #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040 395*5113495bSYour Name 396*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010 397*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MASK_LSB 7 398*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MASK_MSB 7 399*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080 400*5113495bSYour Name 401*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010 402*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_LSB 8 403*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MSB 10 404*5113495bSYour Name #define TX_FES_SETUP_CBF_BW_MASK 0x00000700 405*5113495bSYour Name 406*5113495bSYour Name #define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010 407*5113495bSYour Name #define TX_FES_SETUP_USE_STATIC_BW_LSB 11 408*5113495bSYour Name #define TX_FES_SETUP_USE_STATIC_BW_MSB 11 409*5113495bSYour Name #define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800 410*5113495bSYour Name 411*5113495bSYour Name #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010 412*5113495bSYour Name #define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 413*5113495bSYour Name #define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 414*5113495bSYour Name #define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000 415*5113495bSYour Name 416*5113495bSYour Name #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010 417*5113495bSYour Name #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 418*5113495bSYour Name #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 419*5113495bSYour Name #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000 420*5113495bSYour Name 421*5113495bSYour Name #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010 422*5113495bSYour Name #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 423*5113495bSYour Name #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 424*5113495bSYour Name #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000 425*5113495bSYour Name 426*5113495bSYour Name #define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010 427*5113495bSYour Name #define TX_FES_SETUP_RESERVED_4A_LSB 20 428*5113495bSYour Name #define TX_FES_SETUP_RESERVED_4A_MSB 22 429*5113495bSYour Name #define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000 430*5113495bSYour Name 431*5113495bSYour Name #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010 432*5113495bSYour Name #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 433*5113495bSYour Name #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 434*5113495bSYour Name #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000 435*5113495bSYour Name 436*5113495bSYour Name #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010 437*5113495bSYour Name #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 438*5113495bSYour Name #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 439*5113495bSYour Name #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000 440*5113495bSYour Name 441*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014 442*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0 443*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31 444*5113495bSYour Name #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff 445*5113495bSYour Name 446*5113495bSYour Name #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018 447*5113495bSYour Name #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 448*5113495bSYour Name #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 449*5113495bSYour Name #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e 450*5113495bSYour Name 451*5113495bSYour Name #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018 452*5113495bSYour Name #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 453*5113495bSYour Name #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 454*5113495bSYour Name #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0 455*5113495bSYour Name 456*5113495bSYour Name #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018 457*5113495bSYour Name #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 458*5113495bSYour Name #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 459*5113495bSYour Name #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00 460*5113495bSYour Name 461*5113495bSYour Name #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018 462*5113495bSYour Name #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 463*5113495bSYour Name #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 464*5113495bSYour Name #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000 465*5113495bSYour Name 466*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018 467*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6A_LSB 14 468*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6A_MSB 14 469*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000 470*5113495bSYour Name 471*5113495bSYour Name #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018 472*5113495bSYour Name #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 473*5113495bSYour Name #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 474*5113495bSYour Name #define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000 475*5113495bSYour Name 476*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018 477*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6B_LSB 16 478*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6B_MSB 30 479*5113495bSYour Name #define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000 480*5113495bSYour Name 481*5113495bSYour Name #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018 482*5113495bSYour Name #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 483*5113495bSYour Name #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 484*5113495bSYour Name #define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000 485*5113495bSYour Name 486*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c 487*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0 488*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31 489*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff 490*5113495bSYour Name 491*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020 492*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 493*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 494*5113495bSYour Name #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f 495*5113495bSYour Name 496*5113495bSYour Name #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020 497*5113495bSYour Name #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 498*5113495bSYour Name #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 499*5113495bSYour Name #define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020 500*5113495bSYour Name 501*5113495bSYour Name #define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020 502*5113495bSYour Name #define TX_FES_SETUP_RESERVED_8A_LSB 6 503*5113495bSYour Name #define TX_FES_SETUP_RESERVED_8A_MSB 31 504*5113495bSYour Name #define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0 505*5113495bSYour Name 506*5113495bSYour Name #define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024 507*5113495bSYour Name #define TX_FES_SETUP_FW2SW_INFO_LSB 0 508*5113495bSYour Name #define TX_FES_SETUP_FW2SW_INFO_MSB 31 509*5113495bSYour Name #define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff 510*5113495bSYour Name 511*5113495bSYour Name #endif 512