1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _TX_FES_STATUS_USER_PPDU_H_ 19 #define _TX_FES_STATUS_USER_PPDU_H_ 20 21 #define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 22 23 struct tx_fes_status_user_ppdu { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t underflow_mpdu_count : 9, 26 data_underflow_warning : 2, 27 bw_drop_underflow_warning : 1, 28 qc_eosp_setting : 1, 29 fc_more_data_setting : 1, 30 fc_pwr_mgt_setting : 1, 31 mpdu_tx_count : 9, 32 user_blocked : 1, 33 pre_trig_response_delim_count : 7; 34 uint32_t underflow_byte_count : 16, 35 coex_abort_mpdu_count_valid : 1, 36 coex_abort_mpdu_count : 9, 37 transmitted_tid : 4, 38 txdma_dropped_mpdu_warning : 1, 39 reserved_1 : 1; 40 uint32_t duration : 16, 41 num_eof_delim_added : 16; 42 uint32_t psdu_octet : 24, 43 qos_buf_state : 8; 44 uint32_t num_null_delim_added : 22, 45 reserved_4a : 2, 46 cv_corr_user_valid_in_phy : 1, 47 nss : 3, 48 mcs : 4; 49 uint32_t ht_control : 32; 50 #else 51 uint32_t pre_trig_response_delim_count : 7, 52 user_blocked : 1, 53 mpdu_tx_count : 9, 54 fc_pwr_mgt_setting : 1, 55 fc_more_data_setting : 1, 56 qc_eosp_setting : 1, 57 bw_drop_underflow_warning : 1, 58 data_underflow_warning : 2, 59 underflow_mpdu_count : 9; 60 uint32_t reserved_1 : 1, 61 txdma_dropped_mpdu_warning : 1, 62 transmitted_tid : 4, 63 coex_abort_mpdu_count : 9, 64 coex_abort_mpdu_count_valid : 1, 65 underflow_byte_count : 16; 66 uint32_t num_eof_delim_added : 16, 67 duration : 16; 68 uint32_t qos_buf_state : 8, 69 psdu_octet : 24; 70 uint32_t mcs : 4, 71 nss : 3, 72 cv_corr_user_valid_in_phy : 1, 73 reserved_4a : 2, 74 num_null_delim_added : 22; 75 uint32_t ht_control : 32; 76 #endif 77 }; 78 79 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000000 80 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 81 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 82 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff 83 84 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 85 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 86 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 87 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x00000600 88 89 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x00000000 90 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 91 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 92 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x00000800 93 94 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x00000000 95 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 96 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 97 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x00001000 98 99 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x00000000 100 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 101 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 102 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x00002000 103 104 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x00000000 105 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 106 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 107 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x00004000 108 109 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x00000000 110 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 111 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 112 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x00ff8000 113 114 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x00000000 115 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 116 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 117 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x01000000 118 119 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x00000000 120 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 121 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 122 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0xfe000000 123 124 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x00000004 125 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 0 126 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 15 127 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff 128 129 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x00000004 130 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 16 131 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 16 132 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x00010000 133 134 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x00000004 135 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 17 136 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 25 137 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe0000 138 139 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x00000004 140 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 26 141 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 29 142 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c000000 143 144 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000004 145 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 30 146 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 30 147 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x40000000 148 149 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x00000004 150 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 31 151 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 31 152 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x80000000 153 154 #define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x00000008 155 #define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 156 #define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 157 #define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x0000ffff 158 159 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x00000008 160 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 161 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 162 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0xffff0000 163 164 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000c 165 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 0 166 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 23 167 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff 168 169 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000c 170 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 24 171 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 31 172 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff000000 173 174 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x00000010 175 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 176 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 177 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x003fffff 178 179 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x00000010 180 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 181 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 182 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x00c00000 183 184 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x00000010 185 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 186 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 187 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x01000000 188 189 #define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x00000010 190 #define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 191 #define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 192 #define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0e000000 193 194 #define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x00000010 195 #define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 196 #define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 197 #define TX_FES_STATUS_USER_PPDU_MCS_MASK 0xf0000000 198 199 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x00000014 200 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 0 201 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 31 202 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff 203 204 #endif 205