1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 19 #define _U_SIG_EHT_SU_MU_INFO_H_ 20 21 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 22 23 struct u_sig_eht_su_mu_info { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t phy_version : 3, 26 transmit_bw : 3, 27 dl_ul_flag : 1, 28 bss_color_id : 6, 29 txop_duration : 7, 30 disregard_0a : 5, 31 validate_0b : 1, 32 reserved_0c : 6; 33 uint32_t eht_ppdu_sig_cmn_type : 2, 34 validate_1a : 1, 35 punctured_channel_information : 5, 36 validate_1b : 1, 37 mcs_of_eht_sig : 2, 38 num_eht_sig_symbols : 5, 39 crc : 4, 40 tail : 6, 41 dot11ax_su_extended : 1, 42 reserved_1d : 3, 43 rx_ndp : 1, 44 rx_integrity_check_passed : 1; 45 #else 46 uint32_t reserved_0c : 6, 47 validate_0b : 1, 48 disregard_0a : 5, 49 txop_duration : 7, 50 bss_color_id : 6, 51 dl_ul_flag : 1, 52 transmit_bw : 3, 53 phy_version : 3; 54 uint32_t rx_integrity_check_passed : 1, 55 rx_ndp : 1, 56 reserved_1d : 3, 57 dot11ax_su_extended : 1, 58 tail : 6, 59 crc : 4, 60 num_eht_sig_symbols : 5, 61 mcs_of_eht_sig : 2, 62 validate_1b : 1, 63 punctured_channel_information : 5, 64 validate_1a : 1, 65 eht_ppdu_sig_cmn_type : 2; 66 #endif 67 }; 68 69 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 70 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 71 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 72 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 73 74 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 75 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 76 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 77 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 78 79 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 80 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 81 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 82 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 83 84 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 85 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 86 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 87 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 88 89 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 90 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 91 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 92 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 93 94 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 95 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 96 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 97 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 98 99 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 100 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 101 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 102 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 103 104 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 105 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 106 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 107 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 108 109 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 110 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 111 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 112 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 113 114 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 115 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 116 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 117 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 118 119 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 120 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 121 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 122 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 123 124 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 125 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 126 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 127 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 128 129 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 130 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 131 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 132 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 133 134 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 135 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 136 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 137 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 138 139 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 140 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 141 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 142 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 143 144 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 145 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 146 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 147 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 148 149 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 150 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 151 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 152 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 153 154 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 155 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 156 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 157 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 158 159 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 160 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 161 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 162 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 163 164 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 165 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 166 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 167 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 168 169 #endif 170