1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 19 #define _WBM2SW_COMPLETION_RING_RX_H_ 20 21 #include "rx_msdu_desc_info.h" 22 #include "rx_mpdu_desc_info.h" 23 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 24 25 struct wbm2sw_completion_ring_rx { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t buffer_virt_addr_31_0 : 32; 28 uint32_t buffer_virt_addr_63_32 : 32; 29 uint32_t release_source_module : 3, 30 bm_action : 3, 31 buffer_or_desc_type : 3, 32 return_buffer_manager : 4, 33 reserved_2a : 2, 34 cache_id : 1, 35 cookie_conversion_status : 1, 36 rxdma_push_reason : 2, 37 rxdma_error_code : 5, 38 reo_push_reason : 2, 39 reo_error_code : 5, 40 wbm_internal_error : 1; 41 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 42 struct rx_msdu_desc_info rx_msdu_desc_info_details; 43 uint32_t buffer_phys_addr_31_0 : 32; 44 uint32_t buffer_phys_addr_39_32 : 8, 45 sw_buffer_cookie : 20, 46 looping_count : 4; 47 #else 48 uint32_t buffer_virt_addr_31_0 : 32; 49 uint32_t buffer_virt_addr_63_32 : 32; 50 uint32_t wbm_internal_error : 1, 51 reo_error_code : 5, 52 reo_push_reason : 2, 53 rxdma_error_code : 5, 54 rxdma_push_reason : 2, 55 cookie_conversion_status : 1, 56 cache_id : 1, 57 reserved_2a : 2, 58 return_buffer_manager : 4, 59 buffer_or_desc_type : 3, 60 bm_action : 3, 61 release_source_module : 3; 62 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 63 struct rx_msdu_desc_info rx_msdu_desc_info_details; 64 uint32_t buffer_phys_addr_31_0 : 32; 65 uint32_t looping_count : 4, 66 sw_buffer_cookie : 20, 67 buffer_phys_addr_39_32 : 8; 68 #endif 69 }; 70 71 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 72 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 73 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 74 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 75 76 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 77 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 78 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 79 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 80 81 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 82 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 83 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 84 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 85 86 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 87 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 88 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 89 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 90 91 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 92 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 93 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 94 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 95 96 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 97 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 98 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 99 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 100 101 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 102 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 103 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 104 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 105 106 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 107 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 108 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 109 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 110 111 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 112 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 113 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 114 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 115 116 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 117 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 118 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 119 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 120 121 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 122 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 123 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 124 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 125 126 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 127 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 128 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 129 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 130 131 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 132 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 133 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 134 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 135 136 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 137 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 138 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 139 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 140 141 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 142 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 143 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 144 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 145 146 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 147 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 148 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 149 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 150 151 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 152 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 153 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 154 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 155 156 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 157 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 158 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 159 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 160 161 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 162 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 163 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 164 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 165 166 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 167 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 168 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 169 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 170 171 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 172 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 173 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 174 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 175 176 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 177 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 178 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 179 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 180 181 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 182 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 183 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 184 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 185 186 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 187 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 188 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 189 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 190 191 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 192 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 193 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 194 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 195 196 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 197 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 198 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 199 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 200 201 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 202 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 203 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 204 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 205 206 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 207 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 208 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 209 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 210 211 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 212 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 213 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 214 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 215 216 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 217 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 218 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 219 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 220 221 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 222 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 223 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 224 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 225 226 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 227 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 228 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 229 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 230 231 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 232 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 233 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 234 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 235 236 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 237 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 238 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 239 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 240 241 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 242 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 243 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 244 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 245 246 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 247 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 248 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 249 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 250 251 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 252 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 253 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 254 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 255 256 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 257 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 258 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 259 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 260 261 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 262 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 263 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 264 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 265 266 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 267 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 268 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 269 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 270 271 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 272 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 273 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 274 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 275 276 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 277 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 278 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 279 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 280 281 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 282 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 283 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 284 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 285 286 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 287 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 288 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 289 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 290 291 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 292 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 293 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 294 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 295 296 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 297 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 298 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 299 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 300 301 #endif 302