1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_RSSI_LEGACY_H_ 18 #define _PHYRX_RSSI_LEGACY_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "receive_rssi_info.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0 reception_type[3:0], rx_chain_mask_type[4], reserved_0[5], receive_bandwidth[7:6], rx_chain_mask[15:8], phy_ppdu_id[31:16] 28 // 1 sw_phy_meta_data[31:0] 29 // 2 ppdu_start_timestamp[31:0] 30 // 3-18 struct receive_rssi_info pre_rssi_info_details; 31 // 19-34 struct receive_rssi_info preamble_rssi_info_details; 32 // 35 pre_rssi_comb[7:0], rssi_comb[15:8], normalized_pre_rssi_comb[23:16], normalized_rssi_comb[31:24] 33 // 36 rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], rssi_for_spatial_reuse[23:16], rssi_for_trigger_resp[31:24] 34 // 35 // ################ END SUMMARY ################# 36 37 #define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37 38 39 struct phyrx_rssi_legacy { 40 uint32_t reception_type : 4, //[3:0] 41 rx_chain_mask_type : 1, //[4] 42 reserved_0 : 1, //[5] 43 receive_bandwidth : 2, //[7:6] 44 rx_chain_mask : 8, //[15:8] 45 phy_ppdu_id : 16; //[31:16] 46 uint32_t sw_phy_meta_data : 32; //[31:0] 47 uint32_t ppdu_start_timestamp : 32; //[31:0] 48 struct receive_rssi_info pre_rssi_info_details; 49 struct receive_rssi_info preamble_rssi_info_details; 50 uint32_t pre_rssi_comb : 8, //[7:0] 51 rssi_comb : 8, //[15:8] 52 normalized_pre_rssi_comb : 8, //[23:16] 53 normalized_rssi_comb : 8; //[31:24] 54 uint32_t rssi_comb_ppdu : 8, //[7:0] 55 rssi_db_to_dbm_offset : 8, //[15:8] 56 rssi_for_spatial_reuse : 8, //[23:16] 57 rssi_for_trigger_resp : 8; //[31:24] 58 }; 59 60 /* 61 62 reception_type 63 64 This field helps MAC SW determine which field in this 65 (and following TLVs) will contain valid information. For 66 example some RSSI info not valid in case of uplink_ofdma.. 67 68 69 70 In case of UL MU OFDMA or UL MU-MIMO reception 71 pre-announced by MAC during trigger Tx, e-nums 0 or 1 should 72 be used. 73 74 75 76 In case of UL MU OFDMA+MIMO reception, or in case of UL 77 MU reception when PHY has not been pre-informed, e-num 2 78 should be used. 79 80 If this happens, the UL MU frame in the medium is by 81 definition not for this device. 82 83 As reference, see doc: 84 85 Lithium_mac_phy_interface_hld.docx 86 87 Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when 88 this device is not targeted. 89 90 91 92 <enum 0 reception_is_uplink_ofdma> 93 94 <enum 1 reception_is_uplink_mimo> 95 96 <enum 2 reception_is_other> 97 98 <enum 3 reception_is_frameless> PHY RX has been 99 instructed in advance that the upcoming reception is 100 frameless. This implieas that in advance it is known that 101 all frames will collide in the medium, and nothing can be 102 properly decoded... This can happen during the CTS reception 103 in response to the triggered MU-RTS transmission. 104 105 MAC takes no action when seeing this e_num. For the 106 frameless reception the indication in pkt_end is the final 107 one evaluated by the MAC 108 109 110 111 For the relationship between pkt_type and this field, 112 see the table at the end of this TLV description. 113 114 <legal 0-3> 115 116 rx_chain_mask_type 117 118 Indicates if the field rx_chain_mask represents the mask 119 at start of reception (on which the Rssi_comb value is 120 based), or the setting used during the remainder of the 121 reception 122 123 124 125 1'b0: rxtd.listen_pri80_mask 126 127 1'b1: Final receive mask 128 129 130 131 <legal all> 132 133 reserved_0 134 135 <legal 0> 136 137 receive_bandwidth 138 139 Full receive Bandwidth 140 141 142 143 <enum 0 full_rx_bw_20_mhz> 144 145 <enum 1 full_rx_bw_40_mhz> 146 147 <enum 2 full_rx_bw_80_mhz> 148 149 <enum 3 full_rx_bw_160_mhz> 150 151 152 153 <legal 0-3> 154 155 rx_chain_mask 156 157 The chain mask at the start of the reception of this 158 frame. 159 160 161 162 each bit is one antenna 163 164 0: the chain is NOT used 165 166 1: the chain is used 167 168 169 170 Supports up to 8 chains 171 172 173 174 Used in 11ax TPC calculations for UL OFDMA/MIMO and has 175 to be in sync with the rssi_comb value as this is also used 176 by the MAC for the TPC calculations. 177 178 <legal all> 179 180 phy_ppdu_id 181 182 A ppdu counter value that PHY increments for every PPDU 183 received. The counter value wraps around 184 185 <legal all> 186 187 sw_phy_meta_data 188 189 32 bit Meta data that SW can program in a 32 bit PHY 190 register and PHY will insert the value in every 191 RX_RSSI_LEGACY TLV that it generates. 192 193 SW uses this field to embed among other things some SW 194 channel info. 195 196 ppdu_start_timestamp 197 198 Timestamp that indicates when the PPDU that contained 199 this MPDU started on the medium. 200 201 202 203 Note that PHY will detect the start later, and will have 204 to derive out of the preamble info when the frame actually 205 appeared on the medium 206 207 <legal 0- 10> 208 209 struct receive_rssi_info pre_rssi_info_details 210 211 This field is not valid when reception_is_uplink_ofdma 212 213 214 215 Overview of the pre-RSSI values. That is RSSI values 216 measured on the medium before this reception started. 217 218 struct receive_rssi_info preamble_rssi_info_details 219 220 This field is not valid when reception_is_uplink_ofdma 221 222 223 224 Overview of the RSSI values measured during the 225 pre-amble phase of this reception 226 227 pre_rssi_comb 228 229 Combined pre_rssi of all chains. Based on primary 230 channel RSSI. 231 232 233 234 RSSI is reported as 8b signed values. Nominally value is 235 in dB units above or below the noisefloor(minCCApwr). 236 237 238 239 The resolution can be: 240 241 1dB or 0.5dB. This is statically configured within the 242 PHY and MAC 243 244 245 246 In case of 1dB, the Range is: 247 248 -128dB to 127dB 249 250 251 252 In case of 0.5dB, the Range is: 253 254 -64dB to 63.5dB 255 256 257 258 <legal all> 259 260 rssi_comb 261 262 Combined rssi of all chains. Based on primary channel 263 RSSI. 264 265 266 267 RSSI is reported as 8b signed values. Nominally value is 268 in dB units above or below the noisefloor(minCCApwr). 269 270 271 272 The resolution can be: 273 274 1dB or 0.5dB. This is statically configured within the 275 PHY and MAC 276 277 278 279 In case of 1dB, the Range is: 280 281 -128dB to 127dB 282 283 284 285 In case of 0.5dB, the Range is: 286 287 -64dB to 63.5dB 288 289 290 291 <legal all> 292 293 normalized_pre_rssi_comb 294 295 Combined pre_rssi of all chains, but normalized back to 296 a single chain. This avoids PDG from having to evaluate this 297 in combination with receive chain mask and perform all kinds 298 of pre-processing algorithms. 299 300 301 302 Based on primary channel RSSI. 303 304 305 306 RSSI is reported as 8b signed values. Nominally value is 307 in dB units above or below the noisefloor(minCCApwr). 308 309 310 311 The resolution can be: 312 313 1dB or 0.5dB. This is statically configured within the 314 PHY and MAC 315 316 317 318 In case of 1dB, the Range is: 319 320 -128dB to 127dB 321 322 323 324 In case of 0.5dB, the Range is: 325 326 -64dB to 63.5dB 327 328 329 330 <legal all> 331 332 normalized_rssi_comb 333 334 Combined rssi of all chains, but normalized back to a 335 single chain. This avoids PDG from having to evaluate this 336 in combination with receive chain mask and perform all kinds 337 of pre-processing algorithms. 338 339 340 341 Based on primary channel RSSI. 342 343 344 345 RSSI is reported as 8b signed values. Nominally value is 346 in dB units above or below the noisefloor(minCCApwr). 347 348 349 350 The resolution can be: 351 352 1dB or 0.5dB. This is statically configured within the 353 PHY and MAC 354 355 In case of 1dB, the Range is: 356 357 -128dB to 127dB 358 359 360 361 In case of 0.5dB, the Range is: 362 363 -64dB to 63.5dB 364 365 366 367 <legal all> 368 369 rssi_comb_ppdu 370 371 Combined rssi of all chains, based on active 372 RUs/subchannels, a.k.a. rssi_pkt_bw_mac 373 374 375 376 RSSI is reported as 8b signed values. Nominally value is 377 in dB units above or below the noisefloor(minCCApwr). 378 379 380 381 The resolution can be: 382 383 1dB or 0.5dB. This is statically configured within the 384 PHY and MAC 385 386 387 388 In case of 1dB, the Range is: 389 390 -128dB to 127dB 391 392 393 394 In case of 0.5dB, the Range is: 395 396 -64dB to 63.5dB 397 398 399 400 When packet BW is 20 MHz, 401 402 rssi_comb_ppdu = rssi_comb. 403 404 405 406 When packet BW > 20 MHz, 407 408 rssi_comb < rssi_comb_ppdu because rssi_comb only 409 includes power of primary 20 MHz while rssi_comb_ppdu 410 includes power of active RUs/subchannels. 411 412 413 414 <legal all> 415 416 rssi_db_to_dbm_offset 417 418 Offset between 'dB' and 'dBm' values. SW can use this 419 value to convert RSSI 'dBm' values back to 'dB,' and report 420 both the values. 421 422 423 424 When rssi_db_to_dbm_offset = 0, 425 426 all rssi_xxx fields are defined in dB. 427 428 429 430 When rssi_db_to_dbm_offset is a large negative value, 431 all rssi_xxx fields are defined in dBm. 432 433 434 435 <legal all> 436 437 rssi_for_spatial_reuse 438 439 RSSI to be used by HWSCH for transmit (power) selection 440 during an SR opportunity, reported as an 8-bit signed value 441 442 443 444 The resolution can be: 445 446 1dB or 0.5dB. This is statically configured within the 447 PHY and MAC 448 449 450 451 In case of 1dB, the Range is: 452 453 -128dB to 127dB 454 455 456 457 In case of 0.5dB, the Range is: 458 459 -64dB to 63.5dB 460 461 462 463 As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for 464 OBSS PD spatial reuse, the received signal strength level 465 should be measured from the L-STF or L-LTF (but not L-SIG), 466 just as measured to indicate CCA. 467 468 469 470 Also, as per 802.11ax draft 3.3, for OBSS PD spatial 471 reuse, MAC should compare this value with its programmed 472 OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth. 473 Since MAC does not do this scaling, PHY is instead expected 474 to normalize the reported RSSI to 20 MHz. 475 476 477 478 Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, 479 for SRP spatial reuse, the received power level should be 480 measured from the L-STF or L-LTF (but not L-SIG) and 481 normalized to 20 MHz. 482 483 <legal all> 484 485 rssi_for_trigger_resp 486 487 RSSI to be used by PDG for transmit (power) selection 488 during trigger response, reported as an 8-bit signed value 489 490 491 492 The resolution can be: 493 494 1dB or 0.5dB. This is statically configured within the 495 PHY and MAC 496 497 498 499 In case of 1dB, the Range is: 500 501 -128dB to 127dB 502 503 504 505 In case of 0.5dB, the Range is: 506 507 -64dB to 63.5dB 508 509 510 511 As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for 512 trigger response, the received power should be measured from 513 the non-HE portion of the preamble of the PPDU containing 514 the trigger, normalized to 20 MHz, averaged over the 515 antennas over which the average pathloss is being computed. 516 517 <legal all> 518 */ 519 520 521 /* Description PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE 522 523 This field helps MAC SW determine which field in this 524 (and following TLVs) will contain valid information. For 525 example some RSSI info not valid in case of uplink_ofdma.. 526 527 528 529 In case of UL MU OFDMA or UL MU-MIMO reception 530 pre-announced by MAC during trigger Tx, e-nums 0 or 1 should 531 be used. 532 533 534 535 In case of UL MU OFDMA+MIMO reception, or in case of UL 536 MU reception when PHY has not been pre-informed, e-num 2 537 should be used. 538 539 If this happens, the UL MU frame in the medium is by 540 definition not for this device. 541 542 As reference, see doc: 543 544 Lithium_mac_phy_interface_hld.docx 545 546 Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when 547 this device is not targeted. 548 549 550 551 <enum 0 reception_is_uplink_ofdma> 552 553 <enum 1 reception_is_uplink_mimo> 554 555 <enum 2 reception_is_other> 556 557 <enum 3 reception_is_frameless> PHY RX has been 558 instructed in advance that the upcoming reception is 559 frameless. This implieas that in advance it is known that 560 all frames will collide in the medium, and nothing can be 561 properly decoded... This can happen during the CTS reception 562 in response to the triggered MU-RTS transmission. 563 564 MAC takes no action when seeing this e_num. For the 565 frameless reception the indication in pkt_end is the final 566 one evaluated by the MAC 567 568 569 570 For the relationship between pkt_type and this field, 571 see the table at the end of this TLV description. 572 573 <legal 0-3> 574 */ 575 #define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000 576 #define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0 577 #define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f 578 579 /* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE 580 581 Indicates if the field rx_chain_mask represents the mask 582 at start of reception (on which the Rssi_comb value is 583 based), or the setting used during the remainder of the 584 reception 585 586 587 588 1'b0: rxtd.listen_pri80_mask 589 590 1'b1: Final receive mask 591 592 593 594 <legal all> 595 */ 596 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 597 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4 598 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010 599 600 /* Description PHYRX_RSSI_LEGACY_0_RESERVED_0 601 602 <legal 0> 603 */ 604 #define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000 605 #define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5 606 #define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020 607 608 /* Description PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH 609 610 Full receive Bandwidth 611 612 613 614 <enum 0 full_rx_bw_20_mhz> 615 616 <enum 1 full_rx_bw_40_mhz> 617 618 <enum 2 full_rx_bw_80_mhz> 619 620 <enum 3 full_rx_bw_160_mhz> 621 622 623 624 <legal 0-3> 625 */ 626 #define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000 627 #define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6 628 #define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0 629 630 /* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK 631 632 The chain mask at the start of the reception of this 633 frame. 634 635 636 637 each bit is one antenna 638 639 0: the chain is NOT used 640 641 1: the chain is used 642 643 644 645 Supports up to 8 chains 646 647 648 649 Used in 11ax TPC calculations for UL OFDMA/MIMO and has 650 to be in sync with the rssi_comb value as this is also used 651 by the MAC for the TPC calculations. 652 653 <legal all> 654 */ 655 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000 656 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8 657 #define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00 658 659 /* Description PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID 660 661 A ppdu counter value that PHY increments for every PPDU 662 received. The counter value wraps around 663 664 <legal all> 665 */ 666 #define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000 667 #define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16 668 #define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000 669 670 /* Description PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA 671 672 32 bit Meta data that SW can program in a 32 bit PHY 673 register and PHY will insert the value in every 674 RX_RSSI_LEGACY TLV that it generates. 675 676 SW uses this field to embed among other things some SW 677 channel info. 678 */ 679 #define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004 680 #define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0 681 #define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff 682 683 /* Description PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP 684 685 Timestamp that indicates when the PPDU that contained 686 this MPDU started on the medium. 687 688 689 690 Note that PHY will detect the start later, and will have 691 to derive out of the preamble info when the frame actually 692 appeared on the medium 693 694 <legal 0- 10> 695 */ 696 #define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 697 #define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0 698 #define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff 699 700 /* EXTERNAL REFERENCE : struct receive_rssi_info pre_rssi_info_details */ 701 702 703 /* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 704 705 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 706 707 Value of 0x80 indicates invalid. 708 */ 709 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c 710 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 711 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 712 713 /* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 714 715 RSSI of RX PPDU on chain 0 of extension 20 MHz 716 bandwidth. 717 718 Value of 0x80 indicates invalid. 719 */ 720 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c 721 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 722 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 723 724 /* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 725 726 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 727 bandwidth. 728 729 Value of 0x80 indicates invalid. 730 */ 731 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c 732 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 733 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 734 735 /* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 736 737 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 738 bandwidth. 739 740 Value of 0x80 indicates invalid. 741 */ 742 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c 743 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 744 #define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 745 746 /* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 747 748 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 749 bandwidth. 750 751 Value of 0x80 indicates invalid. 752 */ 753 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010 754 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 755 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 756 757 /* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 758 759 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 760 MHz bandwidth. 761 762 Value of 0x80 indicates invalid. 763 */ 764 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010 765 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 766 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 767 768 /* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 769 770 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 771 MHz bandwidth. 772 773 Value of 0x80 indicates invalid. 774 */ 775 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010 776 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 777 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 778 779 /* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 780 781 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 782 bandwidth. 783 784 Value of 0x80 indicates invalid. 785 */ 786 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010 787 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 788 #define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 789 790 /* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 791 792 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 793 794 Value of 0x80 indicates invalid. 795 */ 796 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014 797 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 798 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 799 800 /* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 801 802 RSSI of RX PPDU on chain 1 of extension 20 MHz 803 bandwidth. 804 805 Value of 0x80 indicates invalid. 806 */ 807 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014 808 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 809 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 810 811 /* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 812 813 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 814 bandwidth. 815 816 Value of 0x80 indicates invalid. 817 */ 818 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014 819 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 820 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 821 822 /* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 823 824 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 825 bandwidth. 826 827 Value of 0x80 indicates invalid. 828 */ 829 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014 830 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 831 #define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 832 833 /* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 834 835 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 836 bandwidth. 837 838 Value of 0x80 indicates invalid. 839 */ 840 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018 841 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 842 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 843 844 /* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 845 846 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 847 MHz bandwidth. 848 849 Value of 0x80 indicates invalid. 850 */ 851 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018 852 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 853 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 854 855 /* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 856 857 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 858 MHz bandwidth. 859 860 Value of 0x80 indicates invalid. 861 */ 862 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018 863 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 864 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 865 866 /* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 867 868 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 869 bandwidth. 870 871 Value of 0x80 indicates invalid. 872 */ 873 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018 874 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 875 #define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 876 877 /* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 878 879 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 880 881 Value of 0x80 indicates invalid. 882 */ 883 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c 884 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 885 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 886 887 /* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 888 889 RSSI of RX PPDU on chain 2 of extension 20 MHz 890 bandwidth. 891 892 Value of 0x80 indicates invalid. 893 */ 894 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c 895 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 896 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 897 898 /* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 899 900 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 901 bandwidth. 902 903 Value of 0x80 indicates invalid. 904 */ 905 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c 906 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 907 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 908 909 /* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 910 911 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 912 bandwidth. 913 914 Value of 0x80 indicates invalid. 915 */ 916 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c 917 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 918 #define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 919 920 /* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 921 922 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 923 bandwidth. 924 925 Value of 0x80 indicates invalid. 926 */ 927 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020 928 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 929 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 930 931 /* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 932 933 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 934 MHz bandwidth. 935 936 Value of 0x80 indicates invalid. 937 */ 938 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020 939 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 940 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 941 942 /* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 943 944 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 945 MHz bandwidth. 946 947 Value of 0x80 indicates invalid. 948 */ 949 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020 950 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 951 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 952 953 /* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 954 955 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 956 bandwidth. 957 958 Value of 0x80 indicates invalid. 959 */ 960 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020 961 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 962 #define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 963 964 /* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 965 966 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 967 968 Value of 0x80 indicates invalid. 969 */ 970 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024 971 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 972 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 973 974 /* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 975 976 RSSI of RX PPDU on chain 3 of extension 20 MHz 977 bandwidth. 978 979 Value of 0x80 indicates invalid. 980 */ 981 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024 982 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 983 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 984 985 /* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 986 987 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 988 bandwidth. 989 990 Value of 0x80 indicates invalid. 991 */ 992 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024 993 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 994 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 995 996 /* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 997 998 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 999 bandwidth. 1000 1001 Value of 0x80 indicates invalid. 1002 */ 1003 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024 1004 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1005 #define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1006 1007 /* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1008 1009 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1010 bandwidth. 1011 1012 Value of 0x80 indicates invalid. 1013 */ 1014 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028 1015 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1016 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1017 1018 /* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1019 1020 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1021 MHz bandwidth. 1022 1023 Value of 0x80 indicates invalid. 1024 */ 1025 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028 1026 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1027 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1028 1029 /* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1030 1031 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1032 MHz bandwidth. 1033 1034 Value of 0x80 indicates invalid. 1035 */ 1036 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028 1037 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1038 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1039 1040 /* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1041 1042 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1043 bandwidth. 1044 1045 Value of 0x80 indicates invalid. 1046 */ 1047 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028 1048 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1049 #define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1050 1051 /* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1052 1053 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1054 1055 Value of 0x80 indicates invalid. 1056 */ 1057 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c 1058 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1059 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1060 1061 /* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1062 1063 RSSI of RX PPDU on chain 4 of extension 20 MHz 1064 bandwidth. 1065 1066 Value of 0x80 indicates invalid. 1067 */ 1068 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c 1069 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1070 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1071 1072 /* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1073 1074 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1075 bandwidth. 1076 1077 Value of 0x80 indicates invalid. 1078 */ 1079 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c 1080 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1081 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1082 1083 /* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1084 1085 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1086 bandwidth. 1087 1088 Value of 0x80 indicates invalid. 1089 */ 1090 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c 1091 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1092 #define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1093 1094 /* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1095 1096 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1097 bandwidth. 1098 1099 Value of 0x80 indicates invalid. 1100 */ 1101 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030 1102 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1103 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1104 1105 /* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1106 1107 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1108 MHz bandwidth. 1109 1110 Value of 0x80 indicates invalid. 1111 */ 1112 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030 1113 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1114 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1115 1116 /* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1117 1118 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1119 MHz bandwidth. 1120 1121 Value of 0x80 indicates invalid. 1122 */ 1123 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030 1124 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1125 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1126 1127 /* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1128 1129 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1130 bandwidth. 1131 1132 Value of 0x80 indicates invalid. 1133 */ 1134 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030 1135 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1136 #define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1137 1138 /* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1139 1140 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1141 1142 Value of 0x80 indicates invalid. 1143 */ 1144 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034 1145 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1146 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1147 1148 /* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1149 1150 RSSI of RX PPDU on chain 5 of extension 20 MHz 1151 bandwidth. 1152 1153 Value of 0x80 indicates invalid. 1154 */ 1155 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034 1156 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1157 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1158 1159 /* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1160 1161 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1162 bandwidth. 1163 1164 Value of 0x80 indicates invalid. 1165 */ 1166 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034 1167 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1168 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1169 1170 /* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1171 1172 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1173 bandwidth. 1174 1175 Value of 0x80 indicates invalid. 1176 */ 1177 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034 1178 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1179 #define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1180 1181 /* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1182 1183 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1184 bandwidth. 1185 1186 Value of 0x80 indicates invalid. 1187 */ 1188 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038 1189 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1190 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1191 1192 /* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1193 1194 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1195 MHz bandwidth. 1196 1197 Value of 0x80 indicates invalid. 1198 */ 1199 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038 1200 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1201 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1202 1203 /* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1204 1205 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1206 MHz bandwidth. 1207 1208 Value of 0x80 indicates invalid. 1209 */ 1210 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038 1211 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1212 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1213 1214 /* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1215 1216 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1217 bandwidth. 1218 1219 Value of 0x80 indicates invalid. 1220 */ 1221 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038 1222 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1223 #define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1224 1225 /* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1226 1227 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1228 1229 Value of 0x80 indicates invalid. 1230 */ 1231 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c 1232 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1233 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1234 1235 /* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1236 1237 RSSI of RX PPDU on chain 6 of extension 20 MHz 1238 bandwidth. 1239 1240 Value of 0x80 indicates invalid. 1241 */ 1242 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c 1243 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1244 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1245 1246 /* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1247 1248 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1249 bandwidth. 1250 1251 Value of 0x80 indicates invalid. 1252 */ 1253 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c 1254 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1255 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1256 1257 /* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1258 1259 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1260 bandwidth. 1261 1262 Value of 0x80 indicates invalid. 1263 */ 1264 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c 1265 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1266 #define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1267 1268 /* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1269 1270 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1271 bandwidth. 1272 1273 Value of 0x80 indicates invalid. 1274 */ 1275 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040 1276 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1277 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1278 1279 /* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1280 1281 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1282 MHz bandwidth. 1283 1284 Value of 0x80 indicates invalid. 1285 */ 1286 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040 1287 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1288 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1289 1290 /* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1291 1292 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1293 MHz bandwidth. 1294 1295 Value of 0x80 indicates invalid. 1296 */ 1297 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040 1298 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1299 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1300 1301 /* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1302 1303 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1304 bandwidth. 1305 1306 Value of 0x80 indicates invalid. 1307 */ 1308 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040 1309 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1310 #define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1311 1312 /* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1313 1314 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1315 1316 Value of 0x80 indicates invalid. 1317 */ 1318 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044 1319 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1320 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1321 1322 /* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1323 1324 RSSI of RX PPDU on chain 7 of extension 20 MHz 1325 bandwidth. 1326 1327 Value of 0x80 indicates invalid. 1328 */ 1329 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044 1330 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1331 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1332 1333 /* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1334 1335 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1336 bandwidth. 1337 1338 Value of 0x80 indicates invalid. 1339 */ 1340 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044 1341 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1342 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1343 1344 /* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1345 1346 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1347 bandwidth. 1348 1349 Value of 0x80 indicates invalid. 1350 */ 1351 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044 1352 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1353 #define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1354 1355 /* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1356 1357 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1358 bandwidth. 1359 1360 Value of 0x80 indicates invalid. 1361 */ 1362 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048 1363 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1364 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1365 1366 /* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1367 1368 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1369 MHz bandwidth. 1370 1371 Value of 0x80 indicates invalid. 1372 */ 1373 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048 1374 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1375 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1376 1377 /* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1378 1379 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1380 MHz bandwidth. 1381 1382 Value of 0x80 indicates invalid. 1383 */ 1384 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048 1385 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1386 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1387 1388 /* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1389 1390 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1391 bandwidth. 1392 1393 Value of 0x80 indicates invalid. 1394 */ 1395 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048 1396 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1397 #define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1398 1399 /* EXTERNAL REFERENCE : struct receive_rssi_info preamble_rssi_info_details */ 1400 1401 1402 /* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 1403 1404 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1405 1406 Value of 0x80 indicates invalid. 1407 */ 1408 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c 1409 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1410 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 1411 1412 /* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 1413 1414 RSSI of RX PPDU on chain 0 of extension 20 MHz 1415 bandwidth. 1416 1417 Value of 0x80 indicates invalid. 1418 */ 1419 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c 1420 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1421 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 1422 1423 /* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 1424 1425 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1426 bandwidth. 1427 1428 Value of 0x80 indicates invalid. 1429 */ 1430 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c 1431 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1432 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1433 1434 /* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1435 1436 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1437 bandwidth. 1438 1439 Value of 0x80 indicates invalid. 1440 */ 1441 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c 1442 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1443 #define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1444 1445 /* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1446 1447 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1448 bandwidth. 1449 1450 Value of 0x80 indicates invalid. 1451 */ 1452 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050 1453 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1454 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1455 1456 /* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1457 1458 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1459 MHz bandwidth. 1460 1461 Value of 0x80 indicates invalid. 1462 */ 1463 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050 1464 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1465 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1466 1467 /* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1468 1469 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1470 MHz bandwidth. 1471 1472 Value of 0x80 indicates invalid. 1473 */ 1474 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050 1475 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1476 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1477 1478 /* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1479 1480 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1481 bandwidth. 1482 1483 Value of 0x80 indicates invalid. 1484 */ 1485 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050 1486 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1487 #define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1488 1489 /* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1490 1491 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1492 1493 Value of 0x80 indicates invalid. 1494 */ 1495 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054 1496 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1497 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1498 1499 /* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1500 1501 RSSI of RX PPDU on chain 1 of extension 20 MHz 1502 bandwidth. 1503 1504 Value of 0x80 indicates invalid. 1505 */ 1506 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054 1507 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1508 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1509 1510 /* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1511 1512 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1513 bandwidth. 1514 1515 Value of 0x80 indicates invalid. 1516 */ 1517 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054 1518 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1519 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1520 1521 /* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1522 1523 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1524 bandwidth. 1525 1526 Value of 0x80 indicates invalid. 1527 */ 1528 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054 1529 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1530 #define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1531 1532 /* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1533 1534 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1535 bandwidth. 1536 1537 Value of 0x80 indicates invalid. 1538 */ 1539 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058 1540 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1541 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1542 1543 /* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1544 1545 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1546 MHz bandwidth. 1547 1548 Value of 0x80 indicates invalid. 1549 */ 1550 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058 1551 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1552 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1553 1554 /* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1555 1556 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1557 MHz bandwidth. 1558 1559 Value of 0x80 indicates invalid. 1560 */ 1561 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058 1562 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1563 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1564 1565 /* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1566 1567 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1568 bandwidth. 1569 1570 Value of 0x80 indicates invalid. 1571 */ 1572 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058 1573 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1574 #define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1575 1576 /* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1577 1578 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1579 1580 Value of 0x80 indicates invalid. 1581 */ 1582 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c 1583 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1584 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1585 1586 /* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1587 1588 RSSI of RX PPDU on chain 2 of extension 20 MHz 1589 bandwidth. 1590 1591 Value of 0x80 indicates invalid. 1592 */ 1593 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c 1594 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1595 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1596 1597 /* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1598 1599 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1600 bandwidth. 1601 1602 Value of 0x80 indicates invalid. 1603 */ 1604 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c 1605 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1606 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1607 1608 /* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1609 1610 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1611 bandwidth. 1612 1613 Value of 0x80 indicates invalid. 1614 */ 1615 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c 1616 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1617 #define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1618 1619 /* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1620 1621 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1622 bandwidth. 1623 1624 Value of 0x80 indicates invalid. 1625 */ 1626 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060 1627 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1628 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1629 1630 /* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1631 1632 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1633 MHz bandwidth. 1634 1635 Value of 0x80 indicates invalid. 1636 */ 1637 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060 1638 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1639 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1640 1641 /* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1642 1643 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1644 MHz bandwidth. 1645 1646 Value of 0x80 indicates invalid. 1647 */ 1648 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060 1649 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1650 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1651 1652 /* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1653 1654 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1655 bandwidth. 1656 1657 Value of 0x80 indicates invalid. 1658 */ 1659 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060 1660 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1661 #define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1662 1663 /* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1664 1665 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1666 1667 Value of 0x80 indicates invalid. 1668 */ 1669 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064 1670 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1671 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1672 1673 /* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1674 1675 RSSI of RX PPDU on chain 3 of extension 20 MHz 1676 bandwidth. 1677 1678 Value of 0x80 indicates invalid. 1679 */ 1680 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064 1681 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1682 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1683 1684 /* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1685 1686 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1687 bandwidth. 1688 1689 Value of 0x80 indicates invalid. 1690 */ 1691 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064 1692 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1693 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1694 1695 /* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1696 1697 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1698 bandwidth. 1699 1700 Value of 0x80 indicates invalid. 1701 */ 1702 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064 1703 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1704 #define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1705 1706 /* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1707 1708 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1709 bandwidth. 1710 1711 Value of 0x80 indicates invalid. 1712 */ 1713 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068 1714 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1715 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1716 1717 /* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1718 1719 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1720 MHz bandwidth. 1721 1722 Value of 0x80 indicates invalid. 1723 */ 1724 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068 1725 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1726 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1727 1728 /* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1729 1730 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1731 MHz bandwidth. 1732 1733 Value of 0x80 indicates invalid. 1734 */ 1735 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068 1736 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1737 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1738 1739 /* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1740 1741 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1742 bandwidth. 1743 1744 Value of 0x80 indicates invalid. 1745 */ 1746 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068 1747 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1748 #define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1749 1750 /* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1751 1752 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1753 1754 Value of 0x80 indicates invalid. 1755 */ 1756 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c 1757 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1758 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1759 1760 /* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1761 1762 RSSI of RX PPDU on chain 4 of extension 20 MHz 1763 bandwidth. 1764 1765 Value of 0x80 indicates invalid. 1766 */ 1767 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c 1768 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1769 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1770 1771 /* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1772 1773 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1774 bandwidth. 1775 1776 Value of 0x80 indicates invalid. 1777 */ 1778 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c 1779 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1780 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1781 1782 /* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1783 1784 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1785 bandwidth. 1786 1787 Value of 0x80 indicates invalid. 1788 */ 1789 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c 1790 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1791 #define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1792 1793 /* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1794 1795 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1796 bandwidth. 1797 1798 Value of 0x80 indicates invalid. 1799 */ 1800 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070 1801 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1802 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1803 1804 /* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1805 1806 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1807 MHz bandwidth. 1808 1809 Value of 0x80 indicates invalid. 1810 */ 1811 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070 1812 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1813 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1814 1815 /* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1816 1817 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1818 MHz bandwidth. 1819 1820 Value of 0x80 indicates invalid. 1821 */ 1822 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070 1823 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1824 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1825 1826 /* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1827 1828 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1829 bandwidth. 1830 1831 Value of 0x80 indicates invalid. 1832 */ 1833 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070 1834 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1835 #define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1836 1837 /* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1838 1839 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1840 1841 Value of 0x80 indicates invalid. 1842 */ 1843 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074 1844 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1845 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1846 1847 /* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1848 1849 RSSI of RX PPDU on chain 5 of extension 20 MHz 1850 bandwidth. 1851 1852 Value of 0x80 indicates invalid. 1853 */ 1854 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074 1855 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1856 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1857 1858 /* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1859 1860 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1861 bandwidth. 1862 1863 Value of 0x80 indicates invalid. 1864 */ 1865 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074 1866 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1867 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1868 1869 /* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1870 1871 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1872 bandwidth. 1873 1874 Value of 0x80 indicates invalid. 1875 */ 1876 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074 1877 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1878 #define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1879 1880 /* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1881 1882 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1883 bandwidth. 1884 1885 Value of 0x80 indicates invalid. 1886 */ 1887 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078 1888 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1889 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1890 1891 /* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1892 1893 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1894 MHz bandwidth. 1895 1896 Value of 0x80 indicates invalid. 1897 */ 1898 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078 1899 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1900 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1901 1902 /* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1903 1904 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1905 MHz bandwidth. 1906 1907 Value of 0x80 indicates invalid. 1908 */ 1909 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078 1910 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1911 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1912 1913 /* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1914 1915 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1916 bandwidth. 1917 1918 Value of 0x80 indicates invalid. 1919 */ 1920 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078 1921 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1922 #define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1923 1924 /* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1925 1926 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1927 1928 Value of 0x80 indicates invalid. 1929 */ 1930 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c 1931 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1932 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1933 1934 /* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1935 1936 RSSI of RX PPDU on chain 6 of extension 20 MHz 1937 bandwidth. 1938 1939 Value of 0x80 indicates invalid. 1940 */ 1941 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c 1942 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1943 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1944 1945 /* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1946 1947 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1948 bandwidth. 1949 1950 Value of 0x80 indicates invalid. 1951 */ 1952 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c 1953 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1954 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1955 1956 /* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1957 1958 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1959 bandwidth. 1960 1961 Value of 0x80 indicates invalid. 1962 */ 1963 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c 1964 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1965 #define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1966 1967 /* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1968 1969 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1970 bandwidth. 1971 1972 Value of 0x80 indicates invalid. 1973 */ 1974 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080 1975 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1976 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1977 1978 /* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1979 1980 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1981 MHz bandwidth. 1982 1983 Value of 0x80 indicates invalid. 1984 */ 1985 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080 1986 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1987 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1988 1989 /* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1990 1991 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1992 MHz bandwidth. 1993 1994 Value of 0x80 indicates invalid. 1995 */ 1996 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080 1997 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1998 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1999 2000 /* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 2001 2002 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 2003 bandwidth. 2004 2005 Value of 0x80 indicates invalid. 2006 */ 2007 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080 2008 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 2009 #define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 2010 2011 /* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 2012 2013 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 2014 2015 Value of 0x80 indicates invalid. 2016 */ 2017 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084 2018 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 2019 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 2020 2021 /* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 2022 2023 RSSI of RX PPDU on chain 7 of extension 20 MHz 2024 bandwidth. 2025 2026 Value of 0x80 indicates invalid. 2027 */ 2028 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084 2029 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 2030 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 2031 2032 /* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 2033 2034 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 2035 bandwidth. 2036 2037 Value of 0x80 indicates invalid. 2038 */ 2039 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084 2040 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 2041 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 2042 2043 /* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 2044 2045 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 2046 bandwidth. 2047 2048 Value of 0x80 indicates invalid. 2049 */ 2050 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084 2051 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 2052 #define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 2053 2054 /* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 2055 2056 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 2057 bandwidth. 2058 2059 Value of 0x80 indicates invalid. 2060 */ 2061 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088 2062 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 2063 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 2064 2065 /* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 2066 2067 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 2068 MHz bandwidth. 2069 2070 Value of 0x80 indicates invalid. 2071 */ 2072 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088 2073 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 2074 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 2075 2076 /* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 2077 2078 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 2079 MHz bandwidth. 2080 2081 Value of 0x80 indicates invalid. 2082 */ 2083 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088 2084 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 2085 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 2086 2087 /* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 2088 2089 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 2090 bandwidth. 2091 2092 Value of 0x80 indicates invalid. 2093 */ 2094 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088 2095 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 2096 #define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 2097 2098 /* Description PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB 2099 2100 Combined pre_rssi of all chains. Based on primary 2101 channel RSSI. 2102 2103 2104 2105 RSSI is reported as 8b signed values. Nominally value is 2106 in dB units above or below the noisefloor(minCCApwr). 2107 2108 2109 2110 The resolution can be: 2111 2112 1dB or 0.5dB. This is statically configured within the 2113 PHY and MAC 2114 2115 2116 2117 In case of 1dB, the Range is: 2118 2119 -128dB to 127dB 2120 2121 2122 2123 In case of 0.5dB, the Range is: 2124 2125 -64dB to 63.5dB 2126 2127 2128 2129 <legal all> 2130 */ 2131 #define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c 2132 #define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0 2133 #define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff 2134 2135 /* Description PHYRX_RSSI_LEGACY_35_RSSI_COMB 2136 2137 Combined rssi of all chains. Based on primary channel 2138 RSSI. 2139 2140 2141 2142 RSSI is reported as 8b signed values. Nominally value is 2143 in dB units above or below the noisefloor(minCCApwr). 2144 2145 2146 2147 The resolution can be: 2148 2149 1dB or 0.5dB. This is statically configured within the 2150 PHY and MAC 2151 2152 2153 2154 In case of 1dB, the Range is: 2155 2156 -128dB to 127dB 2157 2158 2159 2160 In case of 0.5dB, the Range is: 2161 2162 -64dB to 63.5dB 2163 2164 2165 2166 <legal all> 2167 */ 2168 #define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c 2169 #define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8 2170 #define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00 2171 2172 /* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB 2173 2174 Combined pre_rssi of all chains, but normalized back to 2175 a single chain. This avoids PDG from having to evaluate this 2176 in combination with receive chain mask and perform all kinds 2177 of pre-processing algorithms. 2178 2179 2180 2181 Based on primary channel RSSI. 2182 2183 2184 2185 RSSI is reported as 8b signed values. Nominally value is 2186 in dB units above or below the noisefloor(minCCApwr). 2187 2188 2189 2190 The resolution can be: 2191 2192 1dB or 0.5dB. This is statically configured within the 2193 PHY and MAC 2194 2195 2196 2197 In case of 1dB, the Range is: 2198 2199 -128dB to 127dB 2200 2201 2202 2203 In case of 0.5dB, the Range is: 2204 2205 -64dB to 63.5dB 2206 2207 2208 2209 <legal all> 2210 */ 2211 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c 2212 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16 2213 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 2214 2215 /* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB 2216 2217 Combined rssi of all chains, but normalized back to a 2218 single chain. This avoids PDG from having to evaluate this 2219 in combination with receive chain mask and perform all kinds 2220 of pre-processing algorithms. 2221 2222 2223 2224 Based on primary channel RSSI. 2225 2226 2227 2228 RSSI is reported as 8b signed values. Nominally value is 2229 in dB units above or below the noisefloor(minCCApwr). 2230 2231 2232 2233 The resolution can be: 2234 2235 1dB or 0.5dB. This is statically configured within the 2236 PHY and MAC 2237 2238 In case of 1dB, the Range is: 2239 2240 -128dB to 127dB 2241 2242 2243 2244 In case of 0.5dB, the Range is: 2245 2246 -64dB to 63.5dB 2247 2248 2249 2250 <legal all> 2251 */ 2252 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c 2253 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24 2254 #define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000 2255 2256 /* Description PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU 2257 2258 Combined rssi of all chains, based on active 2259 RUs/subchannels, a.k.a. rssi_pkt_bw_mac 2260 2261 2262 2263 RSSI is reported as 8b signed values. Nominally value is 2264 in dB units above or below the noisefloor(minCCApwr). 2265 2266 2267 2268 The resolution can be: 2269 2270 1dB or 0.5dB. This is statically configured within the 2271 PHY and MAC 2272 2273 2274 2275 In case of 1dB, the Range is: 2276 2277 -128dB to 127dB 2278 2279 2280 2281 In case of 0.5dB, the Range is: 2282 2283 -64dB to 63.5dB 2284 2285 2286 2287 When packet BW is 20 MHz, 2288 2289 rssi_comb_ppdu = rssi_comb. 2290 2291 2292 2293 When packet BW > 20 MHz, 2294 2295 rssi_comb < rssi_comb_ppdu because rssi_comb only 2296 includes power of primary 20 MHz while rssi_comb_ppdu 2297 includes power of active RUs/subchannels. 2298 2299 2300 2301 <legal all> 2302 */ 2303 #define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090 2304 #define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0 2305 #define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff 2306 2307 /* Description PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET 2308 2309 Offset between 'dB' and 'dBm' values. SW can use this 2310 value to convert RSSI 'dBm' values back to 'dB,' and report 2311 both the values. 2312 2313 2314 2315 When rssi_db_to_dbm_offset = 0, 2316 2317 all rssi_xxx fields are defined in dB. 2318 2319 2320 2321 When rssi_db_to_dbm_offset is a large negative value, 2322 all rssi_xxx fields are defined in dBm. 2323 2324 2325 2326 <legal all> 2327 */ 2328 #define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090 2329 #define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8 2330 #define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 2331 2332 /* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE 2333 2334 RSSI to be used by HWSCH for transmit (power) selection 2335 during an SR opportunity, reported as an 8-bit signed value 2336 2337 2338 2339 The resolution can be: 2340 2341 1dB or 0.5dB. This is statically configured within the 2342 PHY and MAC 2343 2344 2345 2346 In case of 1dB, the Range is: 2347 2348 -128dB to 127dB 2349 2350 2351 2352 In case of 0.5dB, the Range is: 2353 2354 -64dB to 63.5dB 2355 2356 2357 2358 As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for 2359 OBSS PD spatial reuse, the received signal strength level 2360 should be measured from the L-STF or L-LTF (but not L-SIG), 2361 just as measured to indicate CCA. 2362 2363 2364 2365 Also, as per 802.11ax draft 3.3, for OBSS PD spatial 2366 reuse, MAC should compare this value with its programmed 2367 OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth. 2368 Since MAC does not do this scaling, PHY is instead expected 2369 to normalize the reported RSSI to 20 MHz. 2370 2371 2372 2373 Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, 2374 for SRP spatial reuse, the received power level should be 2375 measured from the L-STF or L-LTF (but not L-SIG) and 2376 normalized to 20 MHz. 2377 2378 <legal all> 2379 */ 2380 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090 2381 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16 2382 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 2383 2384 /* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP 2385 2386 RSSI to be used by PDG for transmit (power) selection 2387 during trigger response, reported as an 8-bit signed value 2388 2389 2390 2391 The resolution can be: 2392 2393 1dB or 0.5dB. This is statically configured within the 2394 PHY and MAC 2395 2396 2397 2398 In case of 1dB, the Range is: 2399 2400 -128dB to 127dB 2401 2402 2403 2404 In case of 0.5dB, the Range is: 2405 2406 -64dB to 63.5dB 2407 2408 2409 2410 As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for 2411 trigger response, the received power should be measured from 2412 the non-HE portion of the preamble of the PPDU containing 2413 the trigger, normalized to 20 MHz, averaged over the 2414 antennas over which the average pathloss is being computed. 2415 2416 <legal all> 2417 */ 2418 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090 2419 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24 2420 #define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 2421 2422 2423 #endif // _PHYRX_RSSI_LEGACY_H_ 2424