xref: /wlan-driver/fw-api/hw/qca5018/reo_flush_cache.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _REO_FLUSH_CACHE_H_
18 #define _REO_FLUSH_CACHE_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #include "uniform_reo_cmd_header.h"
23 
24 // ################ START SUMMARY #################
25 //
26 //	Dword	Fields
27 //	0	struct uniform_reo_cmd_header cmd_header;
28 //	1	flush_addr_31_0[31:0]
29 //	2	flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
30 //	3	reserved_3a[31:0]
31 //	4	reserved_4a[31:0]
32 //	5	reserved_5a[31:0]
33 //	6	reserved_6a[31:0]
34 //	7	reserved_7a[31:0]
35 //	8	reserved_8a[31:0]
36 //
37 // ################ END SUMMARY #################
38 
39 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
40 
41 struct reo_flush_cache {
42     struct            uniform_reo_cmd_header                       cmd_header;
43              uint32_t flush_addr_31_0                 : 32; //[31:0]
44              uint32_t flush_addr_39_32                :  8, //[7:0]
45                       forward_all_mpdus_in_queue      :  1, //[8]
46                       release_cache_block_index       :  1, //[9]
47                       cache_block_resource_index      :  2, //[11:10]
48                       flush_without_invalidate        :  1, //[12]
49                       block_cache_usage_after_flush   :  1, //[13]
50                       flush_entire_cache              :  1, //[14]
51                       reserved_2b                     : 17; //[31:15]
52              uint32_t reserved_3a                     : 32; //[31:0]
53              uint32_t reserved_4a                     : 32; //[31:0]
54              uint32_t reserved_5a                     : 32; //[31:0]
55              uint32_t reserved_6a                     : 32; //[31:0]
56              uint32_t reserved_7a                     : 32; //[31:0]
57              uint32_t reserved_8a                     : 32; //[31:0]
58 };
59 
60 /*
61 
62 struct uniform_reo_cmd_header cmd_header
63 
64 			Consumer: REO
65 
66 			Producer: SW
67 
68 
69 
70 			Details for command execution tracking purposes.
71 
72 flush_addr_31_0
73 
74 			Consumer: REO
75 
76 			Producer: SW
77 
78 
79 
80 			Address (lower 32 bits) of the descriptor to flush
81 
82 			<legal all>
83 
84 flush_addr_39_32
85 
86 			Consumer: REO
87 
88 			Producer: SW
89 
90 
91 
92 			Address (upper 8 bits) of the descriptor to flush
93 
94 			<legal all>
95 
96 forward_all_mpdus_in_queue
97 
98 			Is only allowed to be set when the flush address
99 			corresponds with a REO descriptor.
100 
101 
102 
103 			When set, REO shall first forward all the MPDUs held in
104 			the indicated re-order queue, before flushing the descriptor
105 			from the cache.
106 
107 			<legal all>
108 
109 release_cache_block_index
110 
111 			Field not valid when Flush_entire_cache is set.
112 
113 
114 
115 			If SW has previously used a blocking resource that it
116 			now wants to re-use for this command, this bit shall be set.
117 			It prevents SW from having to send a separate
118 			REO_UNBLOCK_CACHE command.
119 
120 
121 
122 			When set, HW will first release the blocking resource
123 			(indicated in field 'Cache_block_resouce_index') before this
124 			command gets executed.
125 
126 			If that resource was already unblocked, this will be
127 			considered an error. This command will not be executed, and
128 			an error shall be returned.
129 
130 			<legal all>
131 
132 cache_block_resource_index
133 
134 			Field not valid when Flush_entire_cache is set.
135 
136 
137 
138 			Indicates which of the four blocking resources in REO
139 			will be assigned for managing the blocking of this
140 			(descriptor) address
141 
142 			<legal all>
143 
144 flush_without_invalidate
145 
146 			Field not valid when Flush_entire_cache is set.
147 
148 
149 
150 			When set, REO shall flush the cache line contents from
151 			the cache, but there is NO need to invalidate the cache line
152 			entry... The contents in the cache can be maintained. This
153 			feature can be used by SW (and DV) to get a current snapshot
154 			of the contents in the cache
155 
156 
157 
158 			<legal all>
159 
160 block_cache_usage_after_flush
161 
162 			Field not valid when Flush_entire_cache is set.
163 
164 
165 
166 			When set, REO shall block any cache accesses to this
167 			address till explicitly unblocked.
168 
169 
170 
171 			Whenever SW sets this bit, SW shall also set bit
172 			'Forward_all_mpdus_in_queue' to ensure all packets are
173 			flushed out in order to make sure this queue desc is not in
174 			one of the aging link lists. In case SW does not want to
175 			flush the MPDUs in the queue, see the recipe description
176 			below this TLV definition.
177 
178 
179 
180 			The 'blocking' index to be used for this is indicated in
181 			field 'cache_block_resource_index'. If SW had previously
182 			used this blocking resource and was not freed up yet, SW
183 			shall first unblock that index (by setting bit
184 			Release_cache_block_index) or use an unblock command.
185 
186 
187 
188 			If the resource indicated here was already blocked (and
189 			did not get unblocked in this command), it is considered an
190 			error scenario...
191 
192 			No flush shall happen. The status for this command shall
193 			indicate error.
194 
195 
196 
197 			<legal all>
198 
199 flush_entire_cache
200 
201 			When set, the entire cache shall be flushed. The entire
202 			cache will also remain blocked, till the
203 			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
204 			to unblock_cache. All other fields in this command are to be
205 			ignored.
206 
207 
208 
209 			Note that flushing the entire cache has no changes to
210 			the current settings of the blocking resource settings
211 
212 
213 
214 			<legal all>
215 
216 reserved_2b
217 
218 			<legal 0>
219 
220 reserved_3a
221 
222 			<legal 0>
223 
224 reserved_4a
225 
226 			<legal 0>
227 
228 reserved_5a
229 
230 			<legal 0>
231 
232 reserved_6a
233 
234 			<legal 0>
235 
236 reserved_7a
237 
238 			<legal 0>
239 
240 reserved_8a
241 
242 			<legal 0>
243 */
244 
245 
246  /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
247 
248 
249 /* Description		REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER
250 
251 			Consumer: REO/SW/DEBUG
252 
253 			Producer: SW
254 
255 
256 
257 			This number can be used by SW to track, identify and
258 			link the created commands with the command statusses
259 
260 
261 
262 
263 
264 			<legal all>
265 */
266 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET           0x00000000
267 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB              0
268 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK             0x0000ffff
269 
270 /* Description		REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED
271 
272 			Consumer: REO
273 
274 			Producer: SW
275 
276 
277 
278 			<enum 0 NoStatus> REO does not need to generate a status
279 			TLV for the execution of this command
280 
281 			<enum 1 StatusRequired> REO shall generate a status TLV
282 			for the execution of this command
283 
284 
285 
286 			<legal all>
287 */
288 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET      0x00000000
289 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB         16
290 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK        0x00010000
291 
292 /* Description		REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A
293 
294 			<legal 0>
295 */
296 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET              0x00000000
297 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB                 17
298 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK                0xfffe0000
299 
300 /* Description		REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
301 
302 			Consumer: REO
303 
304 			Producer: SW
305 
306 
307 
308 			Address (lower 32 bits) of the descriptor to flush
309 
310 			<legal all>
311 */
312 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET                     0x00000004
313 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB                        0
314 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK                       0xffffffff
315 
316 /* Description		REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
317 
318 			Consumer: REO
319 
320 			Producer: SW
321 
322 
323 
324 			Address (upper 8 bits) of the descriptor to flush
325 
326 			<legal all>
327 */
328 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET                    0x00000008
329 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB                       0
330 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK                      0x000000ff
331 
332 /* Description		REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
333 
334 			Is only allowed to be set when the flush address
335 			corresponds with a REO descriptor.
336 
337 
338 
339 			When set, REO shall first forward all the MPDUs held in
340 			the indicated re-order queue, before flushing the descriptor
341 			from the cache.
342 
343 			<legal all>
344 */
345 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET          0x00000008
346 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB             8
347 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK            0x00000100
348 
349 /* Description		REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
350 
351 			Field not valid when Flush_entire_cache is set.
352 
353 
354 
355 			If SW has previously used a blocking resource that it
356 			now wants to re-use for this command, this bit shall be set.
357 			It prevents SW from having to send a separate
358 			REO_UNBLOCK_CACHE command.
359 
360 
361 
362 			When set, HW will first release the blocking resource
363 			(indicated in field 'Cache_block_resouce_index') before this
364 			command gets executed.
365 
366 			If that resource was already unblocked, this will be
367 			considered an error. This command will not be executed, and
368 			an error shall be returned.
369 
370 			<legal all>
371 */
372 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET           0x00000008
373 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB              9
374 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK             0x00000200
375 
376 /* Description		REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
377 
378 			Field not valid when Flush_entire_cache is set.
379 
380 
381 
382 			Indicates which of the four blocking resources in REO
383 			will be assigned for managing the blocking of this
384 			(descriptor) address
385 
386 			<legal all>
387 */
388 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET          0x00000008
389 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB             10
390 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK            0x00000c00
391 
392 /* Description		REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
393 
394 			Field not valid when Flush_entire_cache is set.
395 
396 
397 
398 			When set, REO shall flush the cache line contents from
399 			the cache, but there is NO need to invalidate the cache line
400 			entry... The contents in the cache can be maintained. This
401 			feature can be used by SW (and DV) to get a current snapshot
402 			of the contents in the cache
403 
404 
405 
406 			<legal all>
407 */
408 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET            0x00000008
409 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB               12
410 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK              0x00001000
411 
412 /* Description		REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
413 
414 			Field not valid when Flush_entire_cache is set.
415 
416 
417 
418 			When set, REO shall block any cache accesses to this
419 			address till explicitly unblocked.
420 
421 
422 
423 			Whenever SW sets this bit, SW shall also set bit
424 			'Forward_all_mpdus_in_queue' to ensure all packets are
425 			flushed out in order to make sure this queue desc is not in
426 			one of the aging link lists. In case SW does not want to
427 			flush the MPDUs in the queue, see the recipe description
428 			below this TLV definition.
429 
430 
431 
432 			The 'blocking' index to be used for this is indicated in
433 			field 'cache_block_resource_index'. If SW had previously
434 			used this blocking resource and was not freed up yet, SW
435 			shall first unblock that index (by setting bit
436 			Release_cache_block_index) or use an unblock command.
437 
438 
439 
440 			If the resource indicated here was already blocked (and
441 			did not get unblocked in this command), it is considered an
442 			error scenario...
443 
444 			No flush shall happen. The status for this command shall
445 			indicate error.
446 
447 
448 
449 			<legal all>
450 */
451 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET       0x00000008
452 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB          13
453 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK         0x00002000
454 
455 /* Description		REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
456 
457 			When set, the entire cache shall be flushed. The entire
458 			cache will also remain blocked, till the
459 			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
460 			to unblock_cache. All other fields in this command are to be
461 			ignored.
462 
463 
464 
465 			Note that flushing the entire cache has no changes to
466 			the current settings of the blocking resource settings
467 
468 
469 
470 			<legal all>
471 */
472 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET                  0x00000008
473 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB                     14
474 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK                    0x00004000
475 
476 /* Description		REO_FLUSH_CACHE_2_RESERVED_2B
477 
478 			<legal 0>
479 */
480 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET                         0x00000008
481 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB                            15
482 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK                           0xffff8000
483 
484 /* Description		REO_FLUSH_CACHE_3_RESERVED_3A
485 
486 			<legal 0>
487 */
488 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET                         0x0000000c
489 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB                            0
490 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK                           0xffffffff
491 
492 /* Description		REO_FLUSH_CACHE_4_RESERVED_4A
493 
494 			<legal 0>
495 */
496 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET                         0x00000010
497 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB                            0
498 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK                           0xffffffff
499 
500 /* Description		REO_FLUSH_CACHE_5_RESERVED_5A
501 
502 			<legal 0>
503 */
504 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET                         0x00000014
505 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB                            0
506 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK                           0xffffffff
507 
508 /* Description		REO_FLUSH_CACHE_6_RESERVED_6A
509 
510 			<legal 0>
511 */
512 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET                         0x00000018
513 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB                            0
514 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK                           0xffffffff
515 
516 /* Description		REO_FLUSH_CACHE_7_RESERVED_7A
517 
518 			<legal 0>
519 */
520 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET                         0x0000001c
521 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB                            0
522 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK                           0xffffffff
523 
524 /* Description		REO_FLUSH_CACHE_8_RESERVED_8A
525 
526 			<legal 0>
527 */
528 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET                         0x00000020
529 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB                            0
530 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK                           0xffffffff
531 
532 
533 #endif // _REO_FLUSH_CACHE_H_
534