1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_START_H_ 18 #define _RX_MPDU_START_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_info.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0-22 struct rx_mpdu_info rx_mpdu_info_details; 28 // 29 // ################ END SUMMARY ################# 30 31 #define NUM_OF_DWORDS_RX_MPDU_START 23 32 33 struct rx_mpdu_start { 34 struct rx_mpdu_info rx_mpdu_info_details; 35 }; 36 37 /* 38 39 struct rx_mpdu_info rx_mpdu_info_details 40 41 Structure containing all the MPDU header details that 42 might be needed for other modules further down the received 43 path 44 */ 45 46 47 /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */ 48 49 50 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 51 52 53 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 54 55 The ID of the REO exit ring where the MSDU frame shall 56 push after (MPDU level) reordering has finished. 57 58 59 60 <enum 0 reo_destination_tcl> Reo will push the frame 61 into the REO2TCL ring 62 63 <enum 1 reo_destination_sw1> Reo will push the frame 64 into the REO2SW1 ring 65 66 <enum 2 reo_destination_sw2> Reo will push the frame 67 into the REO2SW2 ring 68 69 <enum 3 reo_destination_sw3> Reo will push the frame 70 into the REO2SW3 ring 71 72 <enum 4 reo_destination_sw4> Reo will push the frame 73 into the REO2SW4 ring 74 75 <enum 5 reo_destination_release> Reo will push the frame 76 into the REO_release ring 77 78 <enum 6 reo_destination_fw> Reo will push the frame into 79 the REO2FW ring 80 81 <enum 7 reo_destination_sw5> Reo will push the frame 82 into the REO2SW5 ring (REO remaps this in chips without 83 REO2SW5 ring, e.g. Pine) 84 85 <enum 8 reo_destination_sw6> Reo will push the frame 86 into the REO2SW6 ring (REO remaps this in chips without 87 REO2SW6 ring, e.g. Pine) 88 89 <enum 9 reo_destination_9> REO remaps this <enum 10 90 reo_destination_10> REO remaps this 91 92 <enum 11 reo_destination_11> REO remaps this 93 94 <enum 12 reo_destination_12> REO remaps this <enum 13 95 reo_destination_13> REO remaps this 96 97 <enum 14 reo_destination_14> REO remaps this 98 99 <enum 15 reo_destination_15> REO remaps this 100 101 <enum 16 reo_destination_16> REO remaps this 102 103 <enum 17 reo_destination_17> REO remaps this 104 105 <enum 18 reo_destination_18> REO remaps this 106 107 <enum 19 reo_destination_19> REO remaps this 108 109 <enum 20 reo_destination_20> REO remaps this 110 111 <enum 21 reo_destination_21> REO remaps this 112 113 <enum 22 reo_destination_22> REO remaps this 114 115 <enum 23 reo_destination_23> REO remaps this 116 117 <enum 24 reo_destination_24> REO remaps this 118 119 <enum 25 reo_destination_25> REO remaps this 120 121 <enum 26 reo_destination_26> REO remaps this 122 123 <enum 27 reo_destination_27> REO remaps this 124 125 <enum 28 reo_destination_28> REO remaps this 126 127 <enum 29 reo_destination_29> REO remaps this 128 129 <enum 30 reo_destination_30> REO remaps this 130 131 <enum 31 reo_destination_31> REO remaps this 132 133 134 135 <legal all> 136 */ 137 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 138 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 139 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 140 141 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 142 143 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 144 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 145 hash[3:0]} using the chosen Toeplitz hash from Common Parser 146 if flow search fails. 147 148 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 149 's not 2'b00, Rx OLE uses a REO desination indication of 150 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 151 from Common Parser if flow search fails. 152 153 This LMAC/peer-based routing is not supported in 154 Hastings80 and HastingsPrime. 155 156 <legal all> 157 */ 158 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 159 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 160 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 161 162 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 163 164 Indication to Rx OLE to enable REO destination routing 165 based on the chosen Toeplitz hash from Common Parser, in 166 case flow search fails 167 168 <legal all> 169 */ 170 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 171 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 172 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 173 174 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 175 176 Filter pass Unicast data frame (matching 177 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 178 selection 179 180 181 182 1'b0: source and destination rings are selected from the 183 RxOLE register settings for the packet type 184 185 186 187 1'b1: source ring and destination ring is selected from 188 the rxdma0_source_ring_selection and 189 rxdma0_destination_ring_selection fields in this STRUCT 190 191 <legal all> 192 */ 193 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 194 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 195 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 196 197 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 198 199 Filter pass Multicast data frame (matching 200 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 201 selection 202 203 204 205 1'b0: source and destination rings are selected from the 206 RxOLE register settings for the packet type 207 208 209 210 1'b1: source ring and destination ring is selected from 211 the rxdma0_source_ring_selection and 212 rxdma0_destination_ring_selection fields in this STRUCT 213 214 <legal all> 215 */ 216 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 217 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 218 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 219 220 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 221 222 Filter pass BAR frame (matching rxpcu_filter_pass and 223 sw_frame_group_ctrl_1000) routing selection 224 225 226 227 1'b0: source and destination rings are selected from the 228 RxOLE register settings for the packet type 229 230 231 232 1'b1: source ring and destination ring is selected from 233 the rxdma0_source_ring_selection and 234 rxdma0_destination_ring_selection fields in this STRUCT 235 236 <legal all> 237 */ 238 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 239 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 240 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 241 242 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 243 244 Field only valid when for the received frame type the 245 corresponding pkt_selection_fp_... bit is set 246 247 248 249 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 250 251 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 252 this frame shall be sourced by fw2rxdma buffer source ring. 253 254 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 255 this frame shall be sourced by sw2rxdma buffer source ring. 256 257 <enum 3 no_buffer_ring> The frame shall not be written 258 to any data buffer. 259 260 261 262 <legal all> 263 */ 264 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 265 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 266 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 267 268 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 269 270 Field only valid when for the received frame type the 271 corresponding pkt_selection_fp_... bit is set 272 273 274 275 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 276 to the Release ring. Effectively this means the frame needs 277 to be dropped. 278 279 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 280 the FW ring. 281 282 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 283 the SW ring. 284 285 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 286 the REO entrance ring. 287 288 289 290 <legal all> 291 */ 292 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 293 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 294 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 295 296 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 297 298 <legal 0> 299 */ 300 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 301 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 302 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 303 304 /* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0 305 306 In case of ndp or phy_err or AST_based_lookup_valid == 307 0, this field will be set to 0 308 309 310 311 Address (lower 32 bits) of the REO queue descriptor. 312 313 314 315 If no Peer entry lookup happened for this frame, the 316 value wil be set to 0, and the frame shall never be pushed 317 to REO entrance ring. 318 319 <legal all> 320 */ 321 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 322 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 323 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 324 325 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32 326 327 In case of ndp or phy_err or AST_based_lookup_valid == 328 0, this field will be set to 0 329 330 331 332 Address (upper 8 bits) of the REO queue descriptor. 333 334 335 336 If no Peer entry lookup happened for this frame, the 337 value wil be set to 0, and the frame shall never be pushed 338 to REO entrance ring. 339 340 <legal all> 341 */ 342 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 343 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 344 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 345 346 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER 347 348 In case of ndp or phy_err or AST_based_lookup_valid == 349 0, this field will be set to 0 350 351 352 353 Indicates the MPDU queue ID to which this MPDU link 354 descriptor belongs 355 356 Used for tracking and debugging 357 358 <legal all> 359 */ 360 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 361 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 362 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 363 364 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING 365 366 Indicates that a delimiter FCS error was found in 367 between the Previous MPDU and this MPDU. 368 369 370 371 Note that this is just a warning, and does not mean that 372 this MPDU is corrupted in any way. If it is, there will be 373 other errors indicated such as FCS or decrypt errors 374 375 376 377 In case of ndp or phy_err, this field will indicate at 378 least one of delimiters located after the last MPDU in the 379 previous PPDU has been corrupted. 380 */ 381 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 382 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 383 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 384 385 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR 386 387 Indicates that the first delimiter had a FCS failure. 388 Only valid when first_mpdu and first_msdu are set. 389 390 391 392 */ 393 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 394 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 395 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 396 397 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A 398 399 <legal 0> 400 */ 401 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 402 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 403 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 404 405 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0 406 407 408 409 410 411 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 412 is valid. 413 414 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 415 WEPSeed[1], pn1}. Only pn[47:0] is valid. 416 417 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 418 pn1, pn0}. Only pn[47:0] is valid. 419 420 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 421 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 422 pn0}. pn[127:0] are valid. 423 424 425 426 */ 427 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c 428 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 429 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff 430 431 /* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32 432 433 434 435 436 Bits [63:32] of the PN number. See description for 437 pn_31_0. 438 439 440 441 */ 442 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 443 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 444 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff 445 446 /* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64 447 448 449 450 451 Bits [95:64] of the PN number. See description for 452 pn_31_0. 453 454 455 456 */ 457 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 458 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 459 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff 460 461 /* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96 462 463 464 465 466 Bits [127:96] of the PN number. See description for 467 pn_31_0. 468 469 470 471 */ 472 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 473 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 474 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff 475 476 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN 477 478 Field only valid when AST_based_lookup_valid == 1. 479 480 481 482 483 484 In case of ndp or phy_err or AST_based_lookup_valid == 485 0, this field will be set to 0 486 487 488 489 If set to one use EPD instead of LPD 490 491 492 493 494 <legal all> 495 */ 496 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c 497 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 498 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 499 500 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED 501 502 In case of ndp or phy_err or AST_based_lookup_valid == 503 0, this field will be set to 0 504 505 506 507 When set, all frames (data only ?) shall be encrypted. 508 If not, RX CRYPTO shall set an error flag. 509 510 <legal all> 511 */ 512 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 513 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 514 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 515 516 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE 517 518 In case of ndp or phy_err or AST_based_lookup_valid == 519 0, this field will be set to 0 520 521 522 523 Indicates type of decrypt cipher used (as defined in the 524 peer entry) 525 526 527 528 <enum 0 wep_40> WEP 40-bit 529 530 <enum 1 wep_104> WEP 104-bit 531 532 <enum 2 tkip_no_mic> TKIP without MIC 533 534 <enum 3 wep_128> WEP 128-bit 535 536 <enum 4 tkip_with_mic> TKIP with MIC 537 538 <enum 5 wapi> WAPI 539 540 <enum 6 aes_ccmp_128> AES CCMP 128 541 542 <enum 7 no_cipher> No crypto 543 544 <enum 8 aes_ccmp_256> AES CCMP 256 545 546 <enum 9 aes_gcmp_128> AES CCMP 128 547 548 <enum 10 aes_gcmp_256> AES CCMP 256 549 550 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 551 552 553 554 <enum 12 wep_varied_width> WEP encryption. As for WEP 555 per keyid the key bit width can vary, the key bit width for 556 this MPDU will be indicated in field 557 wep_key_width_for_variable key 558 559 <legal 0-12> 560 */ 561 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c 562 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 563 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c 564 565 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 566 567 Field only valid when key_type is set to 568 wep_varied_width. 569 570 571 572 This field indicates the size of the wep key for this 573 MPDU. 574 575 576 577 <enum 0 wep_varied_width_40> WEP 40-bit 578 579 <enum 1 wep_varied_width_104> WEP 104-bit 580 581 <enum 2 wep_varied_width_128> WEP 128-bit 582 583 584 585 <legal 0-2> 586 */ 587 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 588 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 589 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 590 591 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA 592 593 In case of ndp or phy_err or AST_based_lookup_valid == 594 0, this field will be set to 0 595 596 597 598 When set, this is a Mesh (11s) STA. 599 600 601 602 The interpretation of the A-MSDU 'Length' field in the 603 MPDU (if any) is decided by the e-numerations below. 604 605 606 607 <enum 0 MESH_DISABLE> 608 609 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 610 includes the length of Mesh Control. 611 612 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 613 excludes the length of Mesh Control. 614 615 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 616 and excludes the length of Mesh Control. This is 617 802.11s-compliant. 618 619 <legal all> 620 */ 621 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000001c 622 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8 623 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000300 624 625 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT 626 627 In case of ndp or phy_err or AST_based_lookup_valid == 628 0, this field will be set to 0 629 630 631 632 When set, the BSSID of the incoming frame matched one of 633 the 8 BSSID register values 634 635 636 637 <legal all> 638 */ 639 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c 640 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 641 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 642 643 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER 644 645 Field only valid when bssid_hit is set. 646 647 648 649 This number indicates which one out of the 8 BSSID 650 register values matched the incoming frame 651 652 <legal all> 653 */ 654 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c 655 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 656 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 657 658 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID 659 660 Field only valid when mpdu_qos_control_valid is set 661 662 663 664 The TID field in the QoS control field 665 666 <legal all> 667 */ 668 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c 669 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 670 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 671 672 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A 673 674 <legal 0> 675 */ 676 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c 677 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 678 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 679 680 /* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA 681 682 In case of ndp or phy_err or AST_based_lookup_valid == 683 0, this field will be set to 0 684 685 686 687 Meta data that SW has programmed in the Peer table entry 688 of the transmitting STA. 689 690 <legal all> 691 */ 692 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 693 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 694 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 695 696 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY 697 698 Field indicates what the reason was that this MPDU frame 699 was allowed to come into the receive path by RXPCU 700 701 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 702 frame filter programming of rxpcu 703 704 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 705 regular frame filter and would have been dropped, were it 706 not for the frame fitting into the 'monitor_client' 707 category. 708 709 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 710 regular frame filter and also did not pass the 711 rxpcu_monitor_client filter. It would have been dropped 712 accept that it did pass the 'monitor_other' category. 713 714 715 716 Note: for ndp frame, if it was expected because the 717 preceding NDPA was filter_pass, the setting 718 rxpcu_filter_pass will be used. This setting will also be 719 used for every ndp frame in case Promiscuous mode is 720 enabled. 721 722 723 724 In case promiscuous is not enabled, and an NDP is not 725 preceded by a NPDA filter pass frame, the only other setting 726 that could appear here for the NDP is rxpcu_monitor_other. 727 728 (rxpcu has a configuration bit specifically for this 729 scenario) 730 731 732 733 Note: for 734 735 <legal 0-2> 736 */ 737 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 738 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 739 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 740 741 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID 742 743 SW processes frames based on certain classifications. 744 This field indicates to what sw classification this MPDU is 745 mapped. 746 747 The classification is given in priority order 748 749 750 751 <enum 0 sw_frame_group_NDP_frame> Note: The 752 corresponding Rxpcu_Mpdu_filter_in_category can be 753 rxpcu_filter_pass or rxpcu_monitor_other 754 755 756 757 <enum 1 sw_frame_group_Multicast_data> 758 759 <enum 2 sw_frame_group_Unicast_data> 760 761 <enum 3 sw_frame_group_Null_data > This includes mpdus 762 of type Data Null as well as QoS Data Null 763 764 765 766 <enum 4 sw_frame_group_mgmt_0000 > 767 768 <enum 5 sw_frame_group_mgmt_0001 > 769 770 <enum 6 sw_frame_group_mgmt_0010 > 771 772 <enum 7 sw_frame_group_mgmt_0011 > 773 774 <enum 8 sw_frame_group_mgmt_0100 > 775 776 <enum 9 sw_frame_group_mgmt_0101 > 777 778 <enum 10 sw_frame_group_mgmt_0110 > 779 780 <enum 11 sw_frame_group_mgmt_0111 > 781 782 <enum 12 sw_frame_group_mgmt_1000 > 783 784 <enum 13 sw_frame_group_mgmt_1001 > 785 786 <enum 14 sw_frame_group_mgmt_1010 > 787 788 <enum 15 sw_frame_group_mgmt_1011 > 789 790 <enum 16 sw_frame_group_mgmt_1100 > 791 792 <enum 17 sw_frame_group_mgmt_1101 > 793 794 <enum 18 sw_frame_group_mgmt_1110 > 795 796 <enum 19 sw_frame_group_mgmt_1111 > 797 798 799 800 <enum 20 sw_frame_group_ctrl_0000 > 801 802 <enum 21 sw_frame_group_ctrl_0001 > 803 804 <enum 22 sw_frame_group_ctrl_0010 > 805 806 <enum 23 sw_frame_group_ctrl_0011 > 807 808 <enum 24 sw_frame_group_ctrl_0100 > 809 810 <enum 25 sw_frame_group_ctrl_0101 > 811 812 <enum 26 sw_frame_group_ctrl_0110 > 813 814 <enum 27 sw_frame_group_ctrl_0111 > 815 816 <enum 28 sw_frame_group_ctrl_1000 > 817 818 <enum 29 sw_frame_group_ctrl_1001 > 819 820 <enum 30 sw_frame_group_ctrl_1010 > 821 822 <enum 31 sw_frame_group_ctrl_1011 > 823 824 <enum 32 sw_frame_group_ctrl_1100 > 825 826 <enum 33 sw_frame_group_ctrl_1101 > 827 828 <enum 34 sw_frame_group_ctrl_1110 > 829 830 <enum 35 sw_frame_group_ctrl_1111 > 831 832 833 834 <enum 36 sw_frame_group_unsupported> This covers type 3 835 and protocol version != 0 836 837 Note: The corresponding Rxpcu_Mpdu_filter_in_category 838 can only be rxpcu_monitor_other 839 840 841 842 843 Note: The corresponding Rxpcu_Mpdu_filter_in_category 844 can be rxpcu_filter_pass 845 846 847 848 <legal 0-37> 849 */ 850 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 851 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 852 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc 853 854 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME 855 856 When set, the received frame was an NDP frame, and thus 857 there will be no MPDU data. 858 859 <legal all> 860 */ 861 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 862 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 863 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 864 865 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR 866 867 When set, a PHY error was received before MAC received 868 any data, and thus there will be no MPDU data. 869 870 <legal all> 871 */ 872 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 873 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 874 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 875 876 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER 877 878 When set, a PHY error was received before MAC received 879 the complete MPDU header which was needed for proper 880 decoding 881 882 <legal all> 883 */ 884 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 885 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 886 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 887 888 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR 889 890 Set when RXPCU detected a version error in the Frame 891 control field 892 893 <legal all> 894 */ 895 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 896 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 897 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 898 899 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID 900 901 When set, AST based lookup for this frame has found a 902 valid result. 903 904 905 906 Note that for NDP frame this will never be set 907 908 <legal all> 909 */ 910 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 911 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 912 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 913 914 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A 915 916 <legal 0> 917 */ 918 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 919 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 920 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 921 922 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID 923 924 A ppdu counter value that PHY increments for every PPDU 925 received. The counter value wraps around 926 927 <legal all> 928 */ 929 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 930 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 931 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 932 933 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX 934 935 This field indicates the index of the AST entry 936 corresponding to this MPDU. It is provided by the GSE module 937 instantiated in RXPCU. 938 939 A value of 0xFFFF indicates an invalid AST index, 940 meaning that No AST entry was found or NO AST search was 941 performed 942 943 944 945 In case of ndp or phy_err, this field will be set to 946 0xFFFF 947 948 <legal all> 949 */ 950 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 951 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 952 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff 953 954 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID 955 956 In case of ndp or phy_err or AST_based_lookup_valid == 957 0, this field will be set to 0 958 959 960 961 This field indicates a unique peer identifier. It is set 962 equal to field 'sw_peer_id' from the AST entry 963 964 965 966 <legal all> 967 */ 968 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 969 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 970 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 971 972 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID 973 974 When set, the field Mpdu_Frame_control_field has valid 975 information 976 977 978 979 980 <legal all> 981 */ 982 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 983 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 984 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 985 986 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID 987 988 When set, the field Mpdu_duration_field has valid 989 information 990 991 992 993 994 <legal all> 995 */ 996 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c 997 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 998 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 999 1000 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID 1001 1002 When set, the fields mac_addr_ad1_..... have valid 1003 information 1004 1005 1006 1007 1008 <legal all> 1009 */ 1010 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 1011 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 1012 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 1013 1014 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID 1015 1016 When set, the fields mac_addr_ad2_..... have valid 1017 information 1018 1019 1020 1021 1022 1023 1024 1025 <legal all> 1026 */ 1027 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 1028 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 1029 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 1030 1031 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID 1032 1033 When set, the fields mac_addr_ad3_..... have valid 1034 information 1035 1036 1037 1038 1039 1040 1041 1042 <legal all> 1043 */ 1044 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 1045 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 1046 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 1047 1048 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID 1049 1050 When set, the fields mac_addr_ad4_..... have valid 1051 information 1052 1053 1054 1055 1056 1057 1058 1059 <legal all> 1060 */ 1061 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 1062 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 1063 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 1064 1065 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID 1066 1067 When set, the fields mpdu_sequence_control_field and 1068 mpdu_sequence_number have valid information as well as field 1069 1070 1071 1072 For MPDUs without a sequence control field, this field 1073 will not be set. 1074 1075 1076 1077 1078 <legal all> 1079 */ 1080 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 1081 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1082 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1083 1084 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID 1085 1086 When set, the field mpdu_qos_control_field has valid 1087 information 1088 1089 1090 1091 For MPDUs without a QoS control field, this field will 1092 not be set. 1093 1094 1095 1096 1097 <legal all> 1098 */ 1099 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 1100 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 1101 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1102 1103 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID 1104 1105 When set, the field mpdu_HT_control_field has valid 1106 information 1107 1108 1109 1110 For MPDUs without a HT control field, this field will 1111 not be set. 1112 1113 1114 1115 1116 <legal all> 1117 */ 1118 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 1119 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 1120 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1121 1122 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID 1123 1124 When set, the encryption related info fields, like IV 1125 and PN are valid 1126 1127 1128 1129 For MPDUs that are not encrypted, this will not be set. 1130 1131 1132 1133 1134 <legal all> 1135 */ 1136 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 1137 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1138 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1139 1140 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER 1141 1142 Field only valid when Mpdu_sequence_control_valid is set 1143 AND Fragment_flag is set 1144 1145 1146 1147 The fragment number from the 802.11 header 1148 1149 1150 1151 <legal all> 1152 */ 1153 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 1154 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 1155 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1156 1157 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG 1158 1159 The More Fragment bit setting from the MPDU header of 1160 the received frame 1161 1162 1163 1164 <legal all> 1165 */ 1166 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 1167 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 1168 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 1169 1170 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A 1171 1172 <legal 0> 1173 */ 1174 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c 1175 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 1176 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 1177 1178 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS 1179 1180 Field only valid when Mpdu_frame_control_valid is set 1181 1182 1183 1184 Set if the from DS bit is set in the frame control. 1185 1186 <legal all> 1187 */ 1188 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c 1189 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 1190 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 1191 1192 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS 1193 1194 Field only valid when Mpdu_frame_control_valid is set 1195 1196 1197 1198 Set if the to DS bit is set in the frame control. 1199 1200 <legal all> 1201 */ 1202 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c 1203 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 1204 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 1205 1206 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED 1207 1208 Field only valid when Mpdu_frame_control_valid is set. 1209 1210 1211 1212 Protected bit from the frame control. 1213 1214 <legal all> 1215 */ 1216 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c 1217 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 1218 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 1219 1220 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY 1221 1222 Field only valid when Mpdu_frame_control_valid is set. 1223 1224 1225 1226 Retry bit from the frame control. Only valid when 1227 first_msdu is set. 1228 1229 <legal all> 1230 */ 1231 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c 1232 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 1233 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 1234 1235 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 1236 1237 Field only valid when Mpdu_sequence_control_valid is 1238 set. 1239 1240 1241 1242 The sequence number from the 802.11 header. 1243 1244 <legal all> 1245 */ 1246 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 1247 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 1248 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1249 1250 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET 1251 1252 1253 1254 1255 The key ID octet from the IV. 1256 1257 1258 1259 In case of ndp or phy_err or AST_based_lookup_valid == 1260 0, this field will be set to 0 1261 1262 <legal all> 1263 */ 1264 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 1265 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1266 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff 1267 1268 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY 1269 1270 In case of ndp or phy_err or AST_based_lookup_valid == 1271 0, this field will be set to 0 1272 1273 1274 1275 Set if new RX_PEER_ENTRY TLV follows. If clear, 1276 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 1277 uses old peer entry or not decrypt. 1278 1279 <legal all> 1280 */ 1281 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 1282 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1283 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 1284 1285 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED 1286 1287 In case of ndp or phy_err or AST_based_lookup_valid == 1288 0, this field will be set to 0 1289 1290 1291 1292 Set if decryption is needed. 1293 1294 1295 1296 Note: 1297 1298 When RXPCU sets bit 'ast_index_not_found' and/or 1299 ast_index_timeout', RXPCU will also ensure that this bit is 1300 NOT set 1301 1302 CRYPTO for that reason only needs to evaluate this bit 1303 and non of the other ones. 1304 1305 <legal all> 1306 */ 1307 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 1308 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1309 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 1310 1311 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE 1312 1313 In case of ndp or phy_err or AST_based_lookup_valid == 1314 0, this field will be set to 0 1315 1316 1317 1318 Used by the OLE during decapsulation. 1319 1320 1321 1322 Indicates the decapsulation that HW will perform: 1323 1324 1325 1326 <enum 0 RAW> No encapsulation 1327 1328 <enum 1 Native_WiFi> 1329 1330 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 1331 SNAP/LLC) 1332 1333 <enum 3 802_3> Indicate Ethernet 1334 1335 1336 1337 <legal all> 1338 */ 1339 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 1340 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1341 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 1342 1343 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING 1344 1345 In case of ndp or phy_err or AST_based_lookup_valid == 1346 0, this field will be set to 0 1347 1348 1349 1350 Insert 4 byte of all zeros as VLAN tag if the rx payload 1351 does not have VLAN. Used during decapsulation. 1352 1353 <legal all> 1354 */ 1355 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1356 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1357 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1358 1359 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING 1360 1361 In case of ndp or phy_err or AST_based_lookup_valid == 1362 0, this field will be set to 0 1363 1364 1365 1366 Insert 4 byte of all zeros as double VLAN tag if the rx 1367 payload does not have VLAN. Used during 1368 1369 <legal all> 1370 */ 1371 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1372 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1373 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1374 1375 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP 1376 1377 In case of ndp or phy_err or AST_based_lookup_valid == 1378 0, this field will be set to 0 1379 1380 1381 1382 Strip the VLAN during decapsulation. Used by the OLE. 1383 1384 <legal all> 1385 */ 1386 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1387 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1388 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1389 1390 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP 1391 1392 In case of ndp or phy_err or AST_based_lookup_valid == 1393 0, this field will be set to 0 1394 1395 1396 1397 Strip the double VLAN during decapsulation. Used by 1398 the OLE. 1399 1400 <legal all> 1401 */ 1402 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1403 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1404 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1405 1406 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT 1407 1408 The number of delimiters before this MPDU. 1409 1410 1411 1412 Note that this number is cleared at PPDU start. 1413 1414 1415 1416 If this MPDU is the first received MPDU in the PPDU and 1417 this MPDU gets filtered-in, this field will indicate the 1418 number of delimiters located after the last MPDU in the 1419 previous PPDU. 1420 1421 1422 1423 If this MPDU is located after the first received MPDU in 1424 an PPDU, this field will indicate the number of delimiters 1425 located between the previous MPDU and this MPDU. 1426 1427 1428 1429 In case of ndp or phy_err, this field will indicate the 1430 number of delimiters located after the last MPDU in the 1431 previous PPDU. 1432 1433 <legal all> 1434 */ 1435 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 1436 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1437 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 1438 1439 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG 1440 1441 When set, received frame was part of an A-MPDU. 1442 1443 1444 1445 1446 <legal all> 1447 */ 1448 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 1449 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1450 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 1451 1452 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME 1453 1454 In case of ndp or phy_err or AST_based_lookup_valid == 1455 0, this field will be set to 0 1456 1457 1458 1459 When set, received frame is a BAR frame 1460 1461 <legal all> 1462 */ 1463 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 1464 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1465 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 1466 1467 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU 1468 1469 Consumer: SW 1470 1471 Producer: RXOLE 1472 1473 1474 1475 RXPCU sets this field to 0 and RXOLE overwrites it. 1476 1477 1478 1479 Set to 1 by RXOLE when it has not performed any 802.11 1480 to Ethernet/Natvie WiFi header conversion on this MPDU. 1481 1482 <legal all> 1483 */ 1484 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 1485 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 1486 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 1487 1488 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12 1489 1490 <legal 0> 1491 */ 1492 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 1493 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 1494 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 1495 1496 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH 1497 1498 In case of ndp or phy_err this field will be set to 0 1499 1500 1501 1502 MPDU length before decapsulation. 1503 1504 <legal all> 1505 */ 1506 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 1507 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 1508 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff 1509 1510 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU 1511 1512 See definition in RX attention descriptor 1513 1514 1515 1516 In case of ndp or phy_err, this field will be set. Note 1517 however that there will not actually be any data contents in 1518 the MPDU. 1519 1520 <legal all> 1521 */ 1522 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 1523 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 1524 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 1525 1526 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST 1527 1528 In case of ndp or phy_err or Phy_err_during_mpdu_header 1529 this field will be set to 0 1530 1531 1532 1533 See definition in RX attention descriptor 1534 1535 <legal all> 1536 */ 1537 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 1538 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 1539 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 1540 1541 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND 1542 1543 In case of ndp or phy_err or Phy_err_during_mpdu_header 1544 this field will be set to 0 1545 1546 1547 1548 See definition in RX attention descriptor 1549 1550 <legal all> 1551 */ 1552 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1553 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 1554 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 1555 1556 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT 1557 1558 In case of ndp or phy_err or Phy_err_during_mpdu_header 1559 this field will be set to 0 1560 1561 1562 1563 See definition in RX attention descriptor 1564 1565 <legal all> 1566 */ 1567 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1568 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 1569 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 1570 1571 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT 1572 1573 In case of ndp or phy_err or Phy_err_during_mpdu_header 1574 this field will be set to 0 1575 1576 1577 1578 See definition in RX attention descriptor 1579 1580 <legal all> 1581 */ 1582 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 1583 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 1584 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 1585 1586 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS 1587 1588 In case of ndp or phy_err or Phy_err_during_mpdu_header 1589 this field will be set to 1 1590 1591 1592 1593 See definition in RX attention descriptor 1594 1595 <legal all> 1596 */ 1597 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 1598 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 1599 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 1600 1601 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA 1602 1603 In case of ndp or phy_err or Phy_err_during_mpdu_header 1604 this field will be set to 0 1605 1606 1607 1608 See definition in RX attention descriptor 1609 1610 <legal all> 1611 */ 1612 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 1613 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 1614 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 1615 1616 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE 1617 1618 In case of ndp or phy_err or Phy_err_during_mpdu_header 1619 this field will be set to 0 1620 1621 1622 1623 See definition in RX attention descriptor 1624 1625 <legal all> 1626 */ 1627 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 1628 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 1629 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 1630 1631 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE 1632 1633 In case of ndp or phy_err or Phy_err_during_mpdu_header 1634 this field will be set to 0 1635 1636 1637 1638 See definition in RX attention descriptor 1639 1640 <legal all> 1641 */ 1642 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 1643 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 1644 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 1645 1646 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA 1647 1648 In case of ndp or phy_err or Phy_err_during_mpdu_header 1649 this field will be set to 0 1650 1651 1652 1653 See definition in RX attention descriptor 1654 1655 <legal all> 1656 */ 1657 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 1658 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 1659 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 1660 1661 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP 1662 1663 In case of ndp or phy_err or Phy_err_during_mpdu_header 1664 this field will be set to 0 1665 1666 1667 1668 See definition in RX attention descriptor 1669 1670 <legal all> 1671 */ 1672 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 1673 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 1674 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 1675 1676 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG 1677 1678 In case of ndp or phy_err or Phy_err_during_mpdu_header 1679 this field will be set to 0 1680 1681 1682 1683 See definition in RX attention descriptor 1684 1685 <legal all> 1686 */ 1687 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 1688 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 1689 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 1690 1691 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER 1692 1693 In case of ndp or phy_err or Phy_err_during_mpdu_header 1694 this field will be set to 0 1695 1696 1697 1698 See definition in RX attention descriptor 1699 1700 1701 1702 <legal all> 1703 */ 1704 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 1705 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 1706 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 1707 1708 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER 1709 1710 In case of ndp or phy_err or Phy_err_during_mpdu_header 1711 this field will be set to 0 1712 1713 1714 1715 See definition in RX attention descriptor 1716 1717 <legal all> 1718 */ 1719 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 1720 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 1721 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 1722 1723 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED 1724 1725 In case of ndp or phy_err or Phy_err_during_mpdu_header 1726 this field will be set to 0 1727 1728 1729 1730 See definition in RX attention descriptor 1731 1732 <legal all> 1733 */ 1734 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 1735 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 1736 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 1737 1738 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED 1739 1740 In case of ndp or phy_err or Phy_err_during_mpdu_header 1741 this field will be set to 0 1742 1743 1744 1745 See definition in RX attention descriptor 1746 1747 <legal all> 1748 */ 1749 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 1750 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 1751 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 1752 1753 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT 1754 1755 Field only valid when Mpdu_qos_control_valid is set 1756 1757 1758 1759 The 'amsdu_present' bit within the QoS control field of 1760 the MPDU 1761 1762 <legal all> 1763 */ 1764 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 1765 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 1766 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 1767 1768 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13 1769 1770 <legal 0> 1771 */ 1772 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 1773 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 1774 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 1775 1776 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD 1777 1778 Field only valid when Mpdu_frame_control_valid is set 1779 1780 1781 1782 The frame control field of this received MPDU. 1783 1784 1785 1786 Field only valid when Ndp_frame and phy_err are NOT set 1787 1788 1789 1790 Bytes 0 + 1 of the received MPDU 1791 1792 <legal all> 1793 */ 1794 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1795 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1796 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1797 1798 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD 1799 1800 Field only valid when Mpdu_duration_valid is set 1801 1802 1803 1804 The duration field of this received MPDU. 1805 1806 <legal all> 1807 */ 1808 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 1809 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1810 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 1811 1812 /* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0 1813 1814 Field only valid when mac_addr_ad1_valid is set 1815 1816 1817 1818 The Least Significant 4 bytes of the Received Frames MAC 1819 Address AD1 1820 1821 <legal all> 1822 */ 1823 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1824 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 1825 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1826 1827 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32 1828 1829 Field only valid when mac_addr_ad1_valid is set 1830 1831 1832 1833 The 2 most significant bytes of the Received Frames MAC 1834 Address AD1 1835 1836 <legal all> 1837 */ 1838 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1839 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1840 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1841 1842 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0 1843 1844 Field only valid when mac_addr_ad2_valid is set 1845 1846 1847 1848 The Least Significant 2 bytes of the Received Frames MAC 1849 Address AD2 1850 1851 <legal all> 1852 */ 1853 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1854 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1855 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1856 1857 /* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16 1858 1859 Field only valid when mac_addr_ad2_valid is set 1860 1861 1862 1863 The 4 most significant bytes of the Received Frames MAC 1864 Address AD2 1865 1866 <legal all> 1867 */ 1868 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1869 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 1870 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1871 1872 /* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0 1873 1874 Field only valid when mac_addr_ad3_valid is set 1875 1876 1877 1878 The Least Significant 4 bytes of the Received Frames MAC 1879 Address AD3 1880 1881 <legal all> 1882 */ 1883 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1884 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1885 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1886 1887 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32 1888 1889 Field only valid when mac_addr_ad3_valid is set 1890 1891 1892 1893 The 2 most significant bytes of the Received Frames MAC 1894 Address AD3 1895 1896 <legal all> 1897 */ 1898 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1899 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 1900 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1901 1902 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD 1903 1904 1905 1906 1907 The sequence control field of the MPDU 1908 1909 <legal all> 1910 */ 1911 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1912 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1913 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1914 1915 /* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0 1916 1917 Field only valid when mac_addr_ad4_valid is set 1918 1919 1920 1921 The Least Significant 4 bytes of the Received Frames MAC 1922 Address AD4 1923 1924 <legal all> 1925 */ 1926 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1927 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1928 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1929 1930 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32 1931 1932 Field only valid when mac_addr_ad4_valid is set 1933 1934 1935 1936 The 2 most significant bytes of the Received Frames MAC 1937 Address AD4 1938 1939 <legal all> 1940 */ 1941 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1942 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 1943 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1944 1945 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD 1946 1947 Field only valid when mpdu_qos_control_valid is set 1948 1949 1950 1951 The sequence control field of the MPDU 1952 1953 <legal all> 1954 */ 1955 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1956 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 1957 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1958 1959 /* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD 1960 1961 Field only valid when mpdu_qos_control_valid is set 1962 1963 1964 1965 The HT control field of the MPDU 1966 1967 <legal all> 1968 */ 1969 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1970 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 1971 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1972 1973 1974 #endif // _RX_MPDU_START_H_ 1975