1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TCL_GSE_CMD_H_ 18 #define _TCL_GSE_CMD_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 control_buffer_addr_31_0[31:0] 27 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20] 28 // 2 cmd_meta_data_31_0[31:0] 29 // 3 cmd_meta_data_63_32[31:0] 30 // 4 reserved_4a[31:0] 31 // 5 reserved_5a[31:0] 32 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 33 // 34 // ################ END SUMMARY ################# 35 36 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 37 38 struct tcl_gse_cmd { 39 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 40 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 41 gse_ctrl : 4, //[11:8] 42 gse_sel : 1, //[12] 43 status_destination_ring_id : 1, //[13] 44 swap : 1, //[14] 45 index_search_en : 1, //[15] 46 cache_set_num : 4, //[19:16] 47 reserved_1a : 12; //[31:20] 48 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 49 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 50 uint32_t reserved_4a : 32; //[31:0] 51 uint32_t reserved_5a : 32; //[31:0] 52 uint32_t reserved_6a : 20, //[19:0] 53 ring_id : 8, //[27:20] 54 looping_count : 4; //[31:28] 55 }; 56 57 /* 58 59 control_buffer_addr_31_0 60 61 Address (lower 32 bits) of a control buffer containing 62 additional info needed for this command execution. 63 64 <legal all> 65 66 control_buffer_addr_39_32 67 68 Address (upper 8 bits) of a control buffer containing 69 additional info needed for this command execution. 70 71 <legal all> 72 73 gse_ctrl 74 75 GSE control operations. This includes cache operations 76 and table entry statistics read/clear operation. 77 78 <enum 0 rd_stat> Report or Read statistics 79 80 <enum 1 srch_dis> Search disable. Report only Hash 81 82 <enum 2 Wr_bk_single> Write Back single entry 83 84 <enum 3 wr_bk_all> Write Back entire cache entry 85 86 <enum 4 inval_single> Invalidate single cache entry 87 88 <enum 5 inval_all> Invalidate entire cache 89 90 <enum 6 wr_bk_inval_single> Write back and Invalidate 91 single entry in cache 92 93 <enum 7 wr_bk_inval_all> write back and invalidate 94 entire cache 95 96 <enum 8 clr_stat_single> Clear statistics for single 97 entry 98 99 <legal 0-8> 100 101 Rest of the values reserved. 102 103 For all single entry control operations (write back, 104 Invalidate or both)Statistics will be reported 105 106 gse_sel 107 108 Bit to select the ASE or FSE to do the operation mention 109 by GSE_ctrl bit 110 111 0: FSE select 112 113 1: ASE select 114 115 status_destination_ring_id 116 117 The TCL status ring to which the GSE status needs to be 118 send. 119 120 121 122 <enum 0 tcl_status_0_ring> 123 124 <enum 1 tcl_status_1_ring> 125 126 127 128 <legal all> 129 130 swap 131 132 Bit to enable byte swapping of contents of buffer 133 134 <enum 0 Byte_swap_disable > 135 136 <enum 1 byte_swap_enable > 137 138 <legal all> 139 140 index_search_en 141 142 When this bit is set to 1 control_buffer_addr[19:0] will 143 be considered as index of the AST or Flow table and GSE 144 commands will be executed accordingly on the entry pointed 145 by the index. 146 147 This feature is disabled by setting this bit to 0. 148 149 <enum 0 index_based_cmd_disable> 150 151 <enum 1 index_based_cmd_enable> 152 153 154 155 <legal all> 156 157 cache_set_num 158 159 Cache set number that should be used to cache the index 160 based search results, for address and flow search. This 161 value should be equal to value of cache_set_num for the 162 index that is issued in TCL_DATA_CMD during search index 163 based ASE or FSE. This field is valid for index based GSE 164 commands 165 166 <legal all> 167 168 reserved_1a 169 170 <legal 0> 171 172 cmd_meta_data_31_0 173 174 Meta data to be returned in the status descriptor 175 176 <legal all> 177 178 cmd_meta_data_63_32 179 180 Meta data to be returned in the status descriptor 181 182 <legal all> 183 184 reserved_4a 185 186 <legal 0> 187 188 reserved_5a 189 190 <legal 0> 191 192 reserved_6a 193 194 <legal 0> 195 196 ring_id 197 198 Helps with debugging when dumping ring contents. 199 200 <legal all> 201 202 looping_count 203 204 A count value that indicates the number of times the 205 producer of entries into the Ring has looped around the 206 ring. 207 208 At initialization time, this value is set to 0. On the 209 first loop, this value is set to 1. After the max value is 210 reached allowed by the number of bits for this field, the 211 count value continues with 0 again. 212 213 214 215 In case SW is the consumer of the ring entries, it can 216 use this field to figure out up to where the producer of 217 entries has created new entries. This eliminates the need to 218 check where the head pointer' of the ring is located once 219 the SW starts processing an interrupt indicating that new 220 entries have been put into this ring... 221 222 223 224 Also note that SW if it wants only needs to look at the 225 LSB bit of this count value. 226 227 <legal all> 228 */ 229 230 231 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 232 233 Address (lower 32 bits) of a control buffer containing 234 additional info needed for this command execution. 235 236 <legal all> 237 */ 238 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 239 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 240 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 241 242 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 243 244 Address (upper 8 bits) of a control buffer containing 245 additional info needed for this command execution. 246 247 <legal all> 248 */ 249 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 250 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 251 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 252 253 /* Description TCL_GSE_CMD_1_GSE_CTRL 254 255 GSE control operations. This includes cache operations 256 and table entry statistics read/clear operation. 257 258 <enum 0 rd_stat> Report or Read statistics 259 260 <enum 1 srch_dis> Search disable. Report only Hash 261 262 <enum 2 Wr_bk_single> Write Back single entry 263 264 <enum 3 wr_bk_all> Write Back entire cache entry 265 266 <enum 4 inval_single> Invalidate single cache entry 267 268 <enum 5 inval_all> Invalidate entire cache 269 270 <enum 6 wr_bk_inval_single> Write back and Invalidate 271 single entry in cache 272 273 <enum 7 wr_bk_inval_all> write back and invalidate 274 entire cache 275 276 <enum 8 clr_stat_single> Clear statistics for single 277 entry 278 279 <legal 0-8> 280 281 Rest of the values reserved. 282 283 For all single entry control operations (write back, 284 Invalidate or both)Statistics will be reported 285 */ 286 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 287 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 288 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 289 290 /* Description TCL_GSE_CMD_1_GSE_SEL 291 292 Bit to select the ASE or FSE to do the operation mention 293 by GSE_ctrl bit 294 295 0: FSE select 296 297 1: ASE select 298 */ 299 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 300 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 301 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 302 303 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 304 305 The TCL status ring to which the GSE status needs to be 306 send. 307 308 309 310 <enum 0 tcl_status_0_ring> 311 312 <enum 1 tcl_status_1_ring> 313 314 315 316 <legal all> 317 */ 318 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 319 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 320 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 321 322 /* Description TCL_GSE_CMD_1_SWAP 323 324 Bit to enable byte swapping of contents of buffer 325 326 <enum 0 Byte_swap_disable > 327 328 <enum 1 byte_swap_enable > 329 330 <legal all> 331 */ 332 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 333 #define TCL_GSE_CMD_1_SWAP_LSB 14 334 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 335 336 /* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN 337 338 When this bit is set to 1 control_buffer_addr[19:0] will 339 be considered as index of the AST or Flow table and GSE 340 commands will be executed accordingly on the entry pointed 341 by the index. 342 343 This feature is disabled by setting this bit to 0. 344 345 <enum 0 index_based_cmd_disable> 346 347 <enum 1 index_based_cmd_enable> 348 349 350 351 <legal all> 352 */ 353 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 354 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 355 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 356 357 /* Description TCL_GSE_CMD_1_CACHE_SET_NUM 358 359 Cache set number that should be used to cache the index 360 based search results, for address and flow search. This 361 value should be equal to value of cache_set_num for the 362 index that is issued in TCL_DATA_CMD during search index 363 based ASE or FSE. This field is valid for index based GSE 364 commands 365 366 <legal all> 367 */ 368 #define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 369 #define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 370 #define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 371 372 /* Description TCL_GSE_CMD_1_RESERVED_1A 373 374 <legal 0> 375 */ 376 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 377 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 378 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 379 380 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 381 382 Meta data to be returned in the status descriptor 383 384 <legal all> 385 */ 386 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 387 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 388 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 389 390 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 391 392 Meta data to be returned in the status descriptor 393 394 <legal all> 395 */ 396 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 397 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 398 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 399 400 /* Description TCL_GSE_CMD_4_RESERVED_4A 401 402 <legal 0> 403 */ 404 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 405 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 406 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 407 408 /* Description TCL_GSE_CMD_5_RESERVED_5A 409 410 <legal 0> 411 */ 412 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 413 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 414 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 415 416 /* Description TCL_GSE_CMD_6_RESERVED_6A 417 418 <legal 0> 419 */ 420 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 421 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 422 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 423 424 /* Description TCL_GSE_CMD_6_RING_ID 425 426 Helps with debugging when dumping ring contents. 427 428 <legal all> 429 */ 430 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 431 #define TCL_GSE_CMD_6_RING_ID_LSB 20 432 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 433 434 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 435 436 A count value that indicates the number of times the 437 producer of entries into the Ring has looped around the 438 ring. 439 440 At initialization time, this value is set to 0. On the 441 first loop, this value is set to 1. After the max value is 442 reached allowed by the number of bits for this field, the 443 count value continues with 0 again. 444 445 446 447 In case SW is the consumer of the ring entries, it can 448 use this field to figure out up to where the producer of 449 entries has created new entries. This eliminates the need to 450 check where the head pointer' of the ring is located once 451 the SW starts processing an interrupt indicating that new 452 entries have been put into this ring... 453 454 455 456 Also note that SW if it wants only needs to look at the 457 LSB bit of this count value. 458 459 <legal all> 460 */ 461 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 462 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 463 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 464 465 466 #endif // _TCL_GSE_CMD_H_ 467