1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // 19 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020 20 // User Name:c_landav 21 // 22 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23 // 24 /////////////////////////////////////////////////////////////////////////////////////////////// 25 26 #ifndef __WCSS_SEQ_BASE_H__ 27 #define __WCSS_SEQ_BASE_H__ 28 29 #ifdef SCALE_INCLUDES 30 #include "HALhwio.h" 31 #else 32 #include "msmhwio.h" 33 #endif 34 35 36 /////////////////////////////////////////////////////////////////////////////////////////////// 37 // Instance Relative Offsets from Block wcss 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 40 #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 41 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 42 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 43 #define SEQ_WCSS_PHYA_OFFSET 0x00300000 44 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 45 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 46 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 47 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 48 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 49 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 50 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 51 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800 52 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 53 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00 54 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000 55 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 56 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 57 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 58 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 59 #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 60 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00400000 61 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 62 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 63 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET 0x004c0000 64 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x004d4000 65 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x004d4000 66 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x004d4240 67 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x004d42c0 68 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x004d42e0 69 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x004d4300 70 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x004d4400 71 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x004d4480 72 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x004d4800 73 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_DPLL_OFFSET 0x004d4c00 74 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x004d6000 75 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x004d6040 76 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x004d6100 77 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x004d6140 78 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x004d6180 79 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x004d61c0 80 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x004d6240 81 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x004d7c00 82 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x004da000 83 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x004da000 84 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x004dc000 85 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x004dc000 86 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_HLS_BT_REGFILE_OFFSET 0x004dc400 87 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x004dc800 88 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x004dc840 89 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x004dc880 90 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x004dc8c0 91 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x004e0000 92 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x004e0000 93 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x004e0400 94 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x004e0800 95 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x004e1000 96 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x004e1300 97 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x004e1600 98 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x004e1640 99 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x004e2000 100 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x004e4000 101 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x004e8000 102 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x004e8400 103 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x004e8800 104 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x004e9000 105 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x004e9300 106 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x004e9600 107 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x004e9640 108 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x004ea000 109 #define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x004ec000 110 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 111 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 112 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 113 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 114 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 115 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 116 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 117 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 118 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 119 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 120 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 121 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 122 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 123 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 124 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 125 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 126 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 127 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 128 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 129 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 130 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 131 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 132 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 133 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 134 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 135 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 136 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 137 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 138 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 139 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 140 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 141 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 142 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 143 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 144 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 145 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 146 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 147 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 148 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 149 #define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000 150 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 151 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80180 152 #define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190 153 #define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200 154 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0 155 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 156 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80428 157 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000 158 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81180 159 #define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00b81190 160 #define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00b81200 161 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b812c0 162 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400 163 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b81428 164 #define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000 165 #define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080 166 #define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0ac 167 #define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 168 #define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 169 #define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000 170 #define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100 171 #define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 172 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 173 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 174 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 175 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 176 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 177 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 178 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 179 #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 180 #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 181 #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 182 #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 183 #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 184 #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 185 #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 186 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 187 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 188 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 189 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 190 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 191 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 192 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 193 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 194 #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 195 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 196 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 197 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 198 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 199 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 200 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 201 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 202 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 203 #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 204 #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 205 #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 206 #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 207 #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 208 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_OFFSET 0x00be0000 209 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00be0000 210 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 211 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 212 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 213 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00be8000 214 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00be9000 215 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FPB_OFFSET 0x00bea000 216 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_SCS_OFFSET 0x00beb000 217 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ETM_OFFSET 0x00bec000 218 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 219 #define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 220 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 221 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 222 #define SEQ_WCSS_WCSS_ACMT_OFFSET 0x00c9f000 223 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 224 #define SEQ_WCSS_CC_OFFSET 0x00cb0000 225 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 226 #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 227 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 228 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 229 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 230 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 231 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 232 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 233 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 234 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 235 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 236 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 237 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 238 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 239 240 241 /////////////////////////////////////////////////////////////////////////////////////////////// 242 // Instance Relative Offsets from Block wfax_top 243 /////////////////////////////////////////////////////////////////////////////////////////////// 244 245 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 246 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 247 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 248 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 249 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 250 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 251 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 252 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 253 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 254 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00 255 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000 256 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 257 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 258 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 259 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 260 #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 261 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00100000 262 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 263 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 264 265 266 /////////////////////////////////////////////////////////////////////////////////////////////// 267 // Instance Relative Offsets from Block rfa_from_wsi 268 /////////////////////////////////////////////////////////////////////////////////////////////// 269 270 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 271 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 272 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 273 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 274 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142e0 275 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 276 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 277 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 278 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 279 #define SEQ_RFA_FROM_WSI_RFA_CMN_DPLL_OFFSET 0x00014c00 280 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 281 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 282 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 283 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 284 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 285 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 286 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016240 287 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 288 #define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000 289 #define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000 290 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 291 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000 292 #define SEQ_RFA_FROM_WSI_RFA_BT_HLS_BT_REGFILE_OFFSET 0x0001c400 293 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800 294 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840 295 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880 296 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0 297 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 298 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 299 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 300 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 301 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000 302 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300 303 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 304 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 305 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 306 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 307 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 308 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 309 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 310 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000 311 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300 312 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 313 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 314 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 315 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 316 317 318 /////////////////////////////////////////////////////////////////////////////////////////////// 319 // Instance Relative Offsets from Block rfa_cmn 320 /////////////////////////////////////////////////////////////////////////////////////////////// 321 322 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 323 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 324 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 325 #define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002e0 326 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 327 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 328 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 329 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 330 #define SEQ_RFA_CMN_DPLL_OFFSET 0x00000c00 331 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 332 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 333 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 334 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 335 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 336 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 337 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002240 338 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 339 340 341 /////////////////////////////////////////////////////////////////////////////////////////////// 342 // Instance Relative Offsets from Block rfa_pmu 343 /////////////////////////////////////////////////////////////////////////////////////////////// 344 345 #define SEQ_RFA_PMU_PMU_OFFSET 0x00000000 346 347 348 /////////////////////////////////////////////////////////////////////////////////////////////// 349 // Instance Relative Offsets from Block rfa_bt 350 /////////////////////////////////////////////////////////////////////////////////////////////// 351 352 #define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000 353 #define SEQ_RFA_BT_HLS_BT_REGFILE_OFFSET 0x00000400 354 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800 355 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840 356 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880 357 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0 358 359 360 /////////////////////////////////////////////////////////////////////////////////////////////// 361 // Instance Relative Offsets from Block rfa_wl 362 /////////////////////////////////////////////////////////////////////////////////////////////// 363 364 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 365 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 366 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 367 #define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000 368 #define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300 369 #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 370 #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 371 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 372 #define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 373 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 374 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 375 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 376 #define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000 377 #define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300 378 #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 379 #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 380 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 381 #define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 382 383 384 /////////////////////////////////////////////////////////////////////////////////////////////// 385 // Instance Relative Offsets from Block umac_top_reg 386 /////////////////////////////////////////////////////////////////////////////////////////////// 387 388 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 389 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 390 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 391 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 392 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 393 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 394 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 395 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 396 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 397 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 398 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 399 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 400 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 401 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 402 403 404 /////////////////////////////////////////////////////////////////////////////////////////////// 405 // Instance Relative Offsets from Block cxc_top_reg 406 /////////////////////////////////////////////////////////////////////////////////////////////// 407 408 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 409 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 410 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 411 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 412 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 413 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 414 415 416 /////////////////////////////////////////////////////////////////////////////////////////////// 417 // Instance Relative Offsets from Block wmac_top_reg 418 /////////////////////////////////////////////////////////////////////////////////////////////// 419 420 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 421 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 422 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 423 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 424 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 425 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 426 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 427 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 428 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 429 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 430 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 431 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 432 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 433 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 434 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 435 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 436 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 437 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 438 439 440 /////////////////////////////////////////////////////////////////////////////////////////////// 441 // Instance Relative Offsets from Block msip 442 /////////////////////////////////////////////////////////////////////////////////////////////// 443 444 #define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 445 #define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180 446 #define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190 447 #define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200 448 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0 449 #define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 450 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000428 451 #define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000 452 #define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001180 453 #define SEQ_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00001190 454 #define SEQ_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00001200 455 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000012c0 456 #define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400 457 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00001428 458 #define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000 459 #define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 460 #define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0ac 461 #define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 462 #define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 463 #define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 464 #define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100 465 #define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 466 467 468 /////////////////////////////////////////////////////////////////////////////////////////////// 469 // Instance Relative Offsets from Block wcssdbg 470 /////////////////////////////////////////////////////////////////////////////////////////////// 471 472 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 473 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 474 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 475 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 476 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 477 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 478 #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 479 #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 480 #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 481 #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 482 #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 483 #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 484 #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 485 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 486 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 487 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 488 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 489 #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 490 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 491 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 492 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 493 #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 494 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 495 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 496 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 497 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 498 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 499 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 500 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 501 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 502 #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 503 #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 504 #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 505 #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 506 #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 507 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_OFFSET 0x00050000 508 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00050000 509 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 510 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 511 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 512 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00058000 513 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00059000 514 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_FPB_OFFSET 0x0005a000 515 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_SCS_OFFSET 0x0005b000 516 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_ETM_OFFSET 0x0005c000 517 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 518 #define SEQ_WCSSDBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 519 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 520 521 522 /////////////////////////////////////////////////////////////////////////////////////////////// 523 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 524 /////////////////////////////////////////////////////////////////////////////////////////////// 525 526 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 527 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 528 529 530 /////////////////////////////////////////////////////////////////////////////////////////////// 531 // Instance Relative Offsets from Block tpdm_atb128_cmb64 532 /////////////////////////////////////////////////////////////////////////////////////////////// 533 534 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 535 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 536 537 538 /////////////////////////////////////////////////////////////////////////////////////////////// 539 // Instance Relative Offsets from Block phyb_dbg 540 /////////////////////////////////////////////////////////////////////////////////////////////// 541 542 #define SEQ_PHYB_DBG_PHYB_NOC_OFFSET 0x00000000 543 #define SEQ_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 544 #define SEQ_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 545 #define SEQ_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 546 #define SEQ_PHYB_DBG_ITM_OFFSET 0x00008000 547 #define SEQ_PHYB_DBG_DWT_OFFSET 0x00009000 548 #define SEQ_PHYB_DBG_FPB_OFFSET 0x0000a000 549 #define SEQ_PHYB_DBG_SCS_OFFSET 0x0000b000 550 #define SEQ_PHYB_DBG_ETM_OFFSET 0x0000c000 551 #define SEQ_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 552 #define SEQ_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 553 554 555 /////////////////////////////////////////////////////////////////////////////////////////////// 556 // Instance Relative Offsets from Block qdsp6v67ss_wlan 557 /////////////////////////////////////////////////////////////////////////////////////////////// 558 559 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000 560 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 561 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 562 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 563 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 564 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 565 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 566 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 567 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 568 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 569 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 570 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 571 572 573 /////////////////////////////////////////////////////////////////////////////////////////////// 574 // Instance Relative Offsets from Block qdsp6v67ss 575 /////////////////////////////////////////////////////////////////////////////////////////////// 576 577 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 578 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 579 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 580 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 581 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 582 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 583 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 584 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 585 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 586 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 587 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 588 589 590 /////////////////////////////////////////////////////////////////////////////////////////////// 591 // Instance Relative Offsets from Block qdsp6v67ss_public 592 /////////////////////////////////////////////////////////////////////////////////////////////// 593 594 #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 595 596 597 /////////////////////////////////////////////////////////////////////////////////////////////// 598 // Instance Relative Offsets from Block qdsp6v67ss_private 599 /////////////////////////////////////////////////////////////////////////////////////////////// 600 601 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 602 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 603 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 604 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 605 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 606 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 607 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 608 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 609 610 611 /////////////////////////////////////////////////////////////////////////////////////////////// 612 // Instance Relative Offsets from Block q6ss_rscc 613 /////////////////////////////////////////////////////////////////////////////////////////////// 614 615 #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 616 617 618 #endif 619 620