1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _BUFFER_ADDR_INFO_H_ 27 #define _BUFFER_ADDR_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 32 33 34 struct buffer_addr_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t buffer_addr_31_0 : 32; // [31:0] 37 uint32_t buffer_addr_39_32 : 8, // [7:0] 38 return_buffer_manager : 4, // [11:8] 39 sw_buffer_cookie : 20; // [31:12] 40 #else 41 uint32_t buffer_addr_31_0 : 32; // [31:0] 42 uint32_t sw_buffer_cookie : 20, // [31:12] 43 return_buffer_manager : 4, // [11:8] 44 buffer_addr_39_32 : 8; // [7:0] 45 #endif 46 }; 47 48 49 /* Description BUFFER_ADDR_31_0 50 51 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 52 descriptor OR Link Descriptor 53 54 In case of 'NULL' pointer, this field is set to 0 55 <legal all> 56 */ 57 58 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 59 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 60 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 61 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 62 63 64 /* Description BUFFER_ADDR_39_32 65 66 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 67 descriptor OR Link Descriptor 68 69 In case of 'NULL' pointer, this field is set to 0 70 <legal all> 71 */ 72 73 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 74 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 75 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 76 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 77 78 79 /* Description RETURN_BUFFER_MANAGER 80 81 Consumer: WBM 82 Producer: SW/FW 83 84 In case of 'NULL' pointer, this field is set to 0 85 86 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 87 descriptor OR link descriptor that is being pointed to 88 shall be returned after the frame has been processed. It 89 is used by WBM for routing purposes. 90 91 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 92 to the WMB buffer idle list 93 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 94 to the WBM idle link descriptor idle list, where the chip 95 0 WBM is chosen in case of a multi-chip config 96 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 97 to the chip 1 WBM idle link descriptor idle list 98 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 99 to the chip 2 WBM idle link descriptor idle list 100 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 101 returned to chip 3 WBM idle link descriptor idle list 102 <enum 4 FW_BM> This buffer shall be returned to the FW 103 <enum 5 SW0_BM> This buffer shall be returned to the SW, 104 ring 0 105 <enum 6 SW1_BM> This buffer shall be returned to the SW, 106 ring 1 107 <enum 7 SW2_BM> This buffer shall be returned to the SW, 108 ring 2 109 <enum 8 SW3_BM> This buffer shall be returned to the SW, 110 ring 3 111 <enum 9 SW4_BM> This buffer shall be returned to the SW, 112 ring 4 113 <enum 10 SW5_BM> This buffer shall be returned to the SW, 114 ring 5 115 <enum 11 SW6_BM> This buffer shall be returned to the SW, 116 ring 6 117 118 <legal 0-12> 119 */ 120 121 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 122 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 123 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 124 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 125 126 127 /* Description SW_BUFFER_COOKIE 128 129 Cookie field exclusively used by SW. 130 131 In case of 'NULL' pointer, this field is set to 0 132 133 HW ignores the contents, accept that it passes the programmed 134 value on to other descriptors together with the physical 135 address 136 137 Field can be used by SW to for example associate the buffers 138 physical address with the virtual address 139 The bit definitions as used by SW are within SW HLD specification 140 141 142 NOTE1: 143 The three most significant bits can have a special meaning 144 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 145 and field transmit_bw_restriction is set 146 147 In case of NON punctured transmission: 148 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 149 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 150 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 151 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 152 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 153 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 154 Sw_buffer_cookie[19:18] = 2'b11: reserved 155 156 In case of punctured transmission: 157 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 158 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 159 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 160 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 161 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 162 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 163 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 164 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 165 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 166 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 167 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 168 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 169 Sw_buffer_cookie[19:18] = 2'b11: reserved 170 171 Note: a punctured transmission is indicated by the presence 172 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 173 174 <legal all> 175 */ 176 177 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 178 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 179 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 180 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 181 182 183 184 #endif // BUFFER_ADDR_INFO 185