1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _HE_SIG_A_MU_UL_INFO_H_ 27 #define _HE_SIG_A_MU_UL_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 32 33 34 struct he_sig_a_mu_ul_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t format_indication : 1, // [0:0] 37 bss_color_id : 6, // [6:1] 38 spatial_reuse : 16, // [22:7] 39 reserved_0a : 1, // [23:23] 40 transmit_bw : 2, // [25:24] 41 reserved_0b : 6; // [31:26] 42 uint32_t txop_duration : 7, // [6:0] 43 reserved_1a : 9, // [15:7] 44 crc : 4, // [19:16] 45 tail : 6, // [25:20] 46 reserved_1b : 5, // [30:26] 47 rx_integrity_check_passed : 1; // [31:31] 48 #else 49 uint32_t reserved_0b : 6, // [31:26] 50 transmit_bw : 2, // [25:24] 51 reserved_0a : 1, // [23:23] 52 spatial_reuse : 16, // [22:7] 53 bss_color_id : 6, // [6:1] 54 format_indication : 1; // [0:0] 55 uint32_t rx_integrity_check_passed : 1, // [31:31] 56 reserved_1b : 5, // [30:26] 57 tail : 6, // [25:20] 58 crc : 4, // [19:16] 59 reserved_1a : 9, // [15:7] 60 txop_duration : 7; // [6:0] 61 #endif 62 }; 63 64 65 /* Description FORMAT_INDICATION 66 67 Indicates whether the transmission is SU PPDU or a trigger 68 based UL MU PDDU 69 <enum 0 HE_SIGA_FORMAT_HE_TRIG> 70 <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU> 71 <legal all> 72 */ 73 74 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 75 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 76 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 77 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 78 79 80 /* Description BSS_COLOR_ID 81 82 BSS color ID 83 <legal all> 84 */ 85 86 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 87 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 88 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 89 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e 90 91 92 /* Description SPATIAL_REUSE 93 94 Spatial reuse 95 96 <legal all> 97 */ 98 99 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 100 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 101 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 102 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 103 104 105 /* Description RESERVED_0A 106 107 Note: spec indicates this shall be set to 1 108 <legal 1> 109 */ 110 111 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 112 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 113 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 114 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 115 116 117 /* Description TRANSMIT_BW 118 119 Bandwidth of the PPDU. 120 121 <enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz 122 <enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz 123 <enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz 124 <enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz 125 126 On RX side, Field Used by MAC HW 127 <legal 0-3> 128 */ 129 130 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 131 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 132 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 133 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 134 135 136 /* Description RESERVED_0B 137 138 <legal 0> 139 */ 140 141 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 142 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 143 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 144 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 145 146 147 /* Description TXOP_DURATION 148 149 Indicates the remaining time in the current TXOP <legal 150 all> 151 */ 152 153 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 154 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 155 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 156 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f 157 158 159 /* Description RESERVED_1A 160 161 Set to value indicated in the trigger frame 162 <legal 255> 163 */ 164 165 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 166 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 167 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 168 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 169 170 171 /* Description CRC 172 173 CRC for HE-SIG-A contents. 174 This CRC may also cover some fields of L-SIG (TBD) 175 <legal all> 176 */ 177 178 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 179 #define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 180 #define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 181 #define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 182 183 184 /* Description TAIL 185 186 BCC encoding (similar to VHT-SIG-A) with 6 tail bits is 187 used 188 <legal 0> 189 */ 190 191 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 192 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 193 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 194 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 195 196 197 /* Description RESERVED_1B 198 199 <legal 0> 200 */ 201 202 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 203 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 204 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 205 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 206 207 208 /* Description RX_INTEGRITY_CHECK_PASSED 209 210 TX side: Set to 0 211 RX side: Set to 1 if PHY determines the HE-SIG-A CRC check 212 has passed, else set to 0 213 214 <legal all> 215 */ 216 217 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 218 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 219 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 220 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 221 222 223 224 #endif // HE_SIG_A_MU_UL_INFO 225