1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ 27*5113495bSYour Name #define _MACTX_EHT_SIG_USR_MU_MIMO_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #include "eht_sig_usr_mu_mimo_info.h" 32*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 33*5113495bSYour Name 34*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 35*5113495bSYour Name 36*5113495bSYour Name 37*5113495bSYour Name struct mactx_eht_sig_usr_mu_mimo { 38*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 40*5113495bSYour Name #else 41*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 42*5113495bSYour Name #endif 43*5113495bSYour Name }; 44*5113495bSYour Name 45*5113495bSYour Name 46*5113495bSYour Name /* Description MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS 47*5113495bSYour Name 48*5113495bSYour Name See detailed description of the STRUCT 49*5113495bSYour Name */ 50*5113495bSYour Name 51*5113495bSYour Name 52*5113495bSYour Name /* Description STA_ID 53*5113495bSYour Name 54*5113495bSYour Name Identifies the STA that is addressed. Details of STA ID 55*5113495bSYour Name are TBD 56*5113495bSYour Name */ 57*5113495bSYour Name 58*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 59*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 60*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 61*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff 62*5113495bSYour Name 63*5113495bSYour Name 64*5113495bSYour Name /* Description STA_MCS 65*5113495bSYour Name 66*5113495bSYour Name Indicates the data MCS 67*5113495bSYour Name 0 - 13: MCS 0 - 13 68*5113495bSYour Name 14: validate 69*5113495bSYour Name 15: MCS 0 with DCM 70*5113495bSYour Name <legal 0-13, 15> 71*5113495bSYour Name */ 72*5113495bSYour Name 73*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 74*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 75*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 76*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 77*5113495bSYour Name 78*5113495bSYour Name 79*5113495bSYour Name /* Description STA_CODING 80*5113495bSYour Name 81*5113495bSYour Name Distinguishes between BCC/LDPC 82*5113495bSYour Name 83*5113495bSYour Name 0: BCC 84*5113495bSYour Name 1: LDPC 85*5113495bSYour Name <legal all> 86*5113495bSYour Name */ 87*5113495bSYour Name 88*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 89*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 90*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 91*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 92*5113495bSYour Name 93*5113495bSYour Name 94*5113495bSYour Name /* Description STA_SPATIAL_CONFIG 95*5113495bSYour Name 96*5113495bSYour Name Number of assigned spatial streams and their corresponding 97*5113495bSYour Name index. 98*5113495bSYour Name Total number of spatial streams assigned for the MU-MIMO 99*5113495bSYour Name allocation is also signaled. 100*5113495bSYour Name */ 101*5113495bSYour Name 102*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 103*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 104*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 105*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name /* Description RESERVED_0A 109*5113495bSYour Name 110*5113495bSYour Name <legal 0> 111*5113495bSYour Name */ 112*5113495bSYour Name 113*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 114*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 115*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 116*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 117*5113495bSYour Name 118*5113495bSYour Name 119*5113495bSYour Name /* Description RX_INTEGRITY_CHECK_PASSED 120*5113495bSYour Name 121*5113495bSYour Name TX side: Set to 0 122*5113495bSYour Name RX side: Set to 1 if PHY determines the CRC check of the 123*5113495bSYour Name codeblock containing this EHT-SIG user info has passed, 124*5113495bSYour Name else set to 0 125*5113495bSYour Name 126*5113495bSYour Name <legal all> 127*5113495bSYour Name */ 128*5113495bSYour Name 129*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 130*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 131*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 132*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 133*5113495bSYour Name 134*5113495bSYour Name 135*5113495bSYour Name /* Description SUBBAND80_CC_MASK 136*5113495bSYour Name 137*5113495bSYour Name RX side: Set to 0 138*5113495bSYour Name TX side: Indicates what content channels of what 80 MHz 139*5113495bSYour Name subbands this User field can go to 140*5113495bSYour Name Bit 0: lowest 80 MHz content channel 0 141*5113495bSYour Name Bit 1: lowest 80 MHz content channel 1 142*5113495bSYour Name Bit 2: 2nd lowest 80 MHz content channel 0 143*5113495bSYour Name ... 144*5113495bSYour Name Bit 7: highest 80 MHz content channel 1 145*5113495bSYour Name <legal all> 146*5113495bSYour Name */ 147*5113495bSYour Name 148*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 149*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 150*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 151*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 152*5113495bSYour Name 153*5113495bSYour Name 154*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_0 155*5113495bSYour Name 156*5113495bSYour Name RX side: Set to 0 157*5113495bSYour Name TX side: Ordering index of the User field within the lowest 158*5113495bSYour Name 80 MHz 159*5113495bSYour Name Gaps between the ordering indices of User fields indicate 160*5113495bSYour Name that the microcode shall generate "unallocated RU" User 161*5113495bSYour Name fields (STAID=2046) to fill the gaps. 162*5113495bSYour Name <legal all> 163*5113495bSYour Name */ 164*5113495bSYour Name 165*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 166*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 167*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 168*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 169*5113495bSYour Name 170*5113495bSYour Name 171*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_1 172*5113495bSYour Name 173*5113495bSYour Name RX side: Set to 0 174*5113495bSYour Name TX side: Ordering index of the User field within the 2nd 175*5113495bSYour Name lowest 80 MHz 176*5113495bSYour Name See 'user_order_subband80_0.' 177*5113495bSYour Name <legal all> 178*5113495bSYour Name */ 179*5113495bSYour Name 180*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 181*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 182*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 183*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 184*5113495bSYour Name 185*5113495bSYour Name 186*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_2 187*5113495bSYour Name 188*5113495bSYour Name RX side: Set to 0 189*5113495bSYour Name TX side: Ordering index of the User field within the 2nd 190*5113495bSYour Name highest 80 MHz 191*5113495bSYour Name See 'user_order_subband80_0.' 192*5113495bSYour Name <legal all> 193*5113495bSYour Name */ 194*5113495bSYour Name 195*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 196*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 197*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 198*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 199*5113495bSYour Name 200*5113495bSYour Name 201*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_3 202*5113495bSYour Name 203*5113495bSYour Name RX side: Set to 0 204*5113495bSYour Name TX side: Ordering index of the User field within the highest 205*5113495bSYour Name 80 MHz 206*5113495bSYour Name See 'user_order_subband80_0.' 207*5113495bSYour Name <legal all> 208*5113495bSYour Name */ 209*5113495bSYour Name 210*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 211*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 212*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 213*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 214*5113495bSYour Name 215*5113495bSYour Name 216*5113495bSYour Name 217*5113495bSYour Name #endif // MACTX_EHT_SIG_USR_MU_MIMO 218