1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MACTX_HE_SIG_B1_MU_H_ 27 #define _MACTX_HE_SIG_B1_MU_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "he_sig_b1_mu_info.h" 32 #define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 33 34 #define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 35 36 37 struct mactx_he_sig_b1_mu { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 40 uint32_t tlv64_padding : 32; // [31:0] 41 #else 42 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 43 uint32_t tlv64_padding : 32; // [31:0] 44 #endif 45 }; 46 47 48 /* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS 49 50 See detailed description of the STRUCT 51 */ 52 53 54 /* Description RU_ALLOCATION 55 56 RU allocation for the user(s) following this common portion 57 of the SIG 58 59 For details, refer to RU_TYPE description 60 <legal all> 61 */ 62 63 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 64 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 65 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 66 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff 67 68 69 /* Description RESERVED_0 70 71 <legal 0> 72 */ 73 74 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 75 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 76 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 77 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 78 79 80 /* Description RX_INTEGRITY_CHECK_PASSED 81 82 TX side: Set to 0 83 RX side: Set to 1 if PHY determines the CRC check of the 84 codeblock containing the HE-SIG-B common info has passed, 85 else set to 0 86 87 <legal all> 88 */ 89 90 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 91 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 92 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 93 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 94 95 96 /* Description TLV64_PADDING 97 98 Automatic DWORD padding inserted while converting TLV32 99 to TLV64 for 64 bit ARCH 100 <legal 0> 101 */ 102 103 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 104 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 105 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 106 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 107 108 109 110 #endif // MACTX_HE_SIG_B1_MU 111