1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _MACTX_HE_SIG_B1_MU_H_ 27*5113495bSYour Name #define _MACTX_HE_SIG_B1_MU_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #include "he_sig_b1_mu_info.h" 32*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 33*5113495bSYour Name 34*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 35*5113495bSYour Name 36*5113495bSYour Name 37*5113495bSYour Name struct mactx_he_sig_b1_mu { 38*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39*5113495bSYour Name struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 40*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 41*5113495bSYour Name #else 42*5113495bSYour Name struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 43*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 44*5113495bSYour Name #endif 45*5113495bSYour Name }; 46*5113495bSYour Name 47*5113495bSYour Name 48*5113495bSYour Name /* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS 49*5113495bSYour Name 50*5113495bSYour Name See detailed description of the STRUCT 51*5113495bSYour Name */ 52*5113495bSYour Name 53*5113495bSYour Name 54*5113495bSYour Name /* Description RU_ALLOCATION 55*5113495bSYour Name 56*5113495bSYour Name RU allocation for the user(s) following this common portion 57*5113495bSYour Name of the SIG 58*5113495bSYour Name 59*5113495bSYour Name For details, refer to RU_TYPE description 60*5113495bSYour Name <legal all> 61*5113495bSYour Name */ 62*5113495bSYour Name 63*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 64*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 65*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 66*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff 67*5113495bSYour Name 68*5113495bSYour Name 69*5113495bSYour Name /* Description RESERVED_0 70*5113495bSYour Name 71*5113495bSYour Name <legal 0> 72*5113495bSYour Name */ 73*5113495bSYour Name 74*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 75*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 76*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 77*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 78*5113495bSYour Name 79*5113495bSYour Name 80*5113495bSYour Name /* Description RX_INTEGRITY_CHECK_PASSED 81*5113495bSYour Name 82*5113495bSYour Name TX side: Set to 0 83*5113495bSYour Name RX side: Set to 1 if PHY determines the CRC check of the 84*5113495bSYour Name codeblock containing the HE-SIG-B common info has passed, 85*5113495bSYour Name else set to 0 86*5113495bSYour Name 87*5113495bSYour Name <legal all> 88*5113495bSYour Name */ 89*5113495bSYour Name 90*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 91*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 92*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 93*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 94*5113495bSYour Name 95*5113495bSYour Name 96*5113495bSYour Name /* Description TLV64_PADDING 97*5113495bSYour Name 98*5113495bSYour Name Automatic DWORD padding inserted while converting TLV32 99*5113495bSYour Name to TLV64 for 64 bit ARCH 100*5113495bSYour Name <legal 0> 101*5113495bSYour Name */ 102*5113495bSYour Name 103*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 104*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 105*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 106*5113495bSYour Name #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 107*5113495bSYour Name 108*5113495bSYour Name 109*5113495bSYour Name 110*5113495bSYour Name #endif // MACTX_HE_SIG_B1_MU 111