1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MACTX_VHT_SIG_B_SU20_H_ 27 #define _MACTX_VHT_SIG_B_SU20_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "vht_sig_b_su20_info.h" 32 #define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 33 34 #define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 35 36 37 struct mactx_vht_sig_b_su20 { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; 40 uint32_t tlv64_padding : 32; // [31:0] 41 #else 42 struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; 43 uint32_t tlv64_padding : 32; // [31:0] 44 #endif 45 }; 46 47 48 /* Description MACTX_VHT_SIG_B_SU20_INFO_DETAILS 49 50 See detailed description of the STRUCT 51 */ 52 53 54 /* Description LENGTH 55 56 VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) 57 58 <legal all> 59 */ 60 61 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 62 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 63 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 64 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff 65 66 67 /* Description VHTB_RESERVED 68 69 Reserved: Set to all ones for non-NDP frames and ignored 70 on receive 71 <legal 2,7> 72 */ 73 74 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 75 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 76 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 77 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 78 79 80 /* Description TAIL 81 82 Used to terminate the trellis of the convolutional decoder. 83 84 Set to 0. <legal 0> 85 */ 86 87 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 88 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 89 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 90 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 91 92 93 /* Description RESERVED 94 95 Not part of VHT-SIG-B. 96 Reserved: Set to 0 and ignored on receive <legal 0> 97 */ 98 99 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 100 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 101 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 102 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 103 104 105 /* Description RX_NDP 106 107 Not part of VHT-SIG-B. 108 Used to identify received NDP frame 109 <legal 0,1> 110 */ 111 112 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 113 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 114 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 115 #define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 116 117 118 /* Description TLV64_PADDING 119 120 Automatic DWORD padding inserted while converting TLV32 121 to TLV64 for 64 bit ARCH 122 <legal 0> 123 */ 124 125 #define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 126 #define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 127 #define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 128 #define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 129 130 131 132 #endif // MACTX_VHT_SIG_B_SU20 133