1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_ABORT_REQUEST_INFO_H_ 27 #define _PHYRX_ABORT_REQUEST_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 32 33 34 struct phyrx_abort_request_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t phyrx_abort_reason : 8, // [7:0] 37 phy_enters_nap_state : 1, // [8:8] 38 phy_enters_defer_state : 1, // [9:9] 39 reserved_0 : 6, // [15:10] 40 receive_duration : 16; // [31:16] 41 #else 42 uint32_t receive_duration : 16, // [31:16] 43 reserved_0 : 6, // [15:10] 44 phy_enters_defer_state : 1, // [9:9] 45 phy_enters_nap_state : 1, // [8:8] 46 phyrx_abort_reason : 8; // [7:0] 47 #endif 48 }; 49 50 51 /* Description PHYRX_ABORT_REASON 52 53 <enum 0 phyrx_err_phy_off> Reception aborted due to receiving 54 a PHY_OFF TLV 55 <enum 1 phyrx_err_synth_off> 56 <enum 2 phyrx_err_ofdma_timing> 57 <enum 3 phyrx_err_ofdma_signal_parity> 58 <enum 4 phyrx_err_ofdma_rate_illegal> 59 <enum 5 phyrx_err_ofdma_length_illegal> 60 <enum 6 phyrx_err_ofdma_restart> 61 <enum 7 phyrx_err_ofdma_service> 62 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 63 64 <enum 9 phyrx_err_cck_blokker> 65 <enum 10 phyrx_err_cck_timing> 66 <enum 11 phyrx_err_cck_header_crc> 67 <enum 12 phyrx_err_cck_rate_illegal> 68 <enum 13 phyrx_err_cck_length_illegal> 69 <enum 14 phyrx_err_cck_restart> 70 <enum 15 phyrx_err_cck_service> 71 <enum 16 phyrx_err_cck_power_drop> 72 73 <enum 17 phyrx_err_ht_crc_err> 74 <enum 18 phyrx_err_ht_length_illegal> 75 <enum 19 phyrx_err_ht_rate_illegal> 76 <enum 20 phyrx_err_ht_zlf> 77 <enum 21 phyrx_err_false_radar_ext> 78 <enum 22 phyrx_err_green_field> 79 <enum 60 phyrx_err_ht_nsym_lt_zero> 80 81 <enum 23 phyrx_err_bw_gt_dyn_bw> 82 <enum 24 phyrx_err_leg_ht_mismatch> 83 <enum 25 phyrx_err_vht_crc_error> 84 <enum 26 phyrx_err_vht_siga_unsupported> 85 <enum 27 phyrx_err_vht_lsig_len_invalid> 86 <enum 28 phyrx_err_vht_ndp_or_zlf> 87 <enum 29 phyrx_err_vht_nsym_lt_zero> 88 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 89 <enum 31 phyrx_err_vht_rx_skip_group_id0> 90 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 91 <enum 33 phyrx_err_vht_rx_skip_group_id63> 92 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 93 <enum 35 phyrx_err_defer_nap> 94 95 <enum 61 phyrx_err_vht_lsig_rate_mismatch> 96 <enum 62 phyrx_err_vht_paid_gid_mismatch> 97 <enum 63 phyrx_err_vht_unsupported_bw> 98 <enum 64 phyrx_err_vht_gi_disam_mismatch> 99 100 <enum 36 phyrx_err_fdomain_timeout> 101 <enum 37 phyrx_err_lsig_rel_check> 102 <enum 38 phyrx_err_bt_collision> 103 <enum 39 phyrx_err_unsupported_mu_feedback> 104 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 105 <enum 41 phyrx_err_unsupported_cbf> 106 107 <enum 42 phyrx_err_other> Should not really be used. If 108 needed, ask for documentation update 109 110 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error 111 > <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported 112 > <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 113 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 114 phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported 115 > 116 <enum 54 phyrx_err_he_sigb_crc_error> 117 <enum 55 phyrx_err_he_ext_su_unsupported> 118 <enum 56 phyrx_err_he_trig_unsupported> 119 <enum 57 phyrx_err_he_lsig_len_invalid> 120 <enum 58 phyrx_err_he_lsig_rate_mismatch> 121 <enum 59 phyrx_err_ofdma_signal_reliability> 122 123 <enum 77 phyrx_err_wur_detection> 124 125 <enum 72 phyrx_err_u_sig_crc_error> 126 <enum 73 phyrx_err_u_sig_unsupported_mode> 127 <enum 74 phyrx_err_u_sig_rsvd_err> 128 <enum 75 phyrx_err_u_sig_mcs_error> 129 <enum 76 phyrx_err_u_sig_bw_error> 130 <enum 79 phyrx_err_u_sig_320_channel_mismatch> 131 <enum 71 phyrx_err_eht_sig_crc_error> 132 <enum 78 phyrx_err_eht_sig_unsupported_mode> 133 134 <enum 80 phyrx_err_ehtplus_er_detection> 135 136 <enum 52 phyrx_err_MU_UL_no_power_detected> 137 <enum 53 phyrx_err_MU_UL_not_for_me> 138 139 <enum 65 phyrx_err_rx_wdg_timeout> 140 <enum 66 phyrx_err_sizing_evt_unexpected> 141 <enum 67 phyrx_err_spectralscan> 142 <enum 68 phyrx_err_radar_misdetected_as_ofdm> 143 <enum 69 phyrx_err_rx_stuck> 144 <enum 70 phyrx_err_invalid_11b_state> 145 146 <legal 0 - 80> 147 */ 148 149 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 150 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 151 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 152 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff 153 154 155 /* Description PHY_ENTERS_NAP_STATE 156 157 When set, PHY enters PHY NAP state after sending this abort 158 159 160 Note that nap and defer state are mutually exclusive. 161 162 Field put pro-actively in place....usage still to be agreed 163 upon. 164 <legal all> 165 */ 166 167 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 168 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 169 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 170 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 171 172 173 /* Description PHY_ENTERS_DEFER_STATE 174 175 When set, PHY enters PHY defer state after sending this 176 abort 177 178 Note that nap and defer state are mutually exclusive. 179 180 Field put pro-actively in place....usage still to be agreed 181 upon. 182 <legal all> 183 */ 184 185 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 186 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 187 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 188 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 189 190 191 /* Description RESERVED_0 192 193 <legal 0> 194 */ 195 196 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 197 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 198 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 199 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 200 201 202 /* Description RECEIVE_DURATION 203 204 The remaining receive duration of this PPDU in the medium 205 (in us). When PHY does not know this duration when this 206 TLV is generated, the field will be set to 0. 207 The timing reference point is the reception by the MAC of 208 this TLV. The value shall be accurate to within 2us. 209 210 In case Phy_enters_nap_state and/or Phy_enters_defer_state 211 is set, there is a possibility that MAC PMM can also decide 212 to go into a low(er) power state. 213 <legal all> 214 */ 215 216 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 217 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 218 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 219 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 220 221 222 223 #endif // PHYRX_ABORT_REQUEST_INFO 224