1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_L_SIG_B_H_ 27 #define _PHYRX_L_SIG_B_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "l_sig_b_info.h" 32 #define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 33 34 #define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 35 36 37 struct phyrx_l_sig_b { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct l_sig_b_info phyrx_l_sig_b_info_details; 40 uint32_t tlv64_padding : 32; // [31:0] 41 #else 42 struct l_sig_b_info phyrx_l_sig_b_info_details; 43 uint32_t tlv64_padding : 32; // [31:0] 44 #endif 45 }; 46 47 48 /* Description PHYRX_L_SIG_B_INFO_DETAILS 49 50 See detailed description of the STRUCT 51 */ 52 53 54 /* Description RATE 55 56 <enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long 57 <enum 2 dsss_2_mbps_long> DSSS 2 Mbps long 58 <enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long 59 <enum 4 cck_11_mbps_long> CCK 11 Mbps long 60 <enum 5 dsss_2_mbps_short> DSSS 2 Mbps short 61 <enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short 62 <enum 7 cck_11_mbps_short> CCK 11 Mbps short 63 <legal 1-7> 64 */ 65 66 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 67 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 68 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 69 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f 70 71 72 /* Description LENGTH 73 74 The length indicates the number of octets in this MPDU. 75 <legal all> 76 */ 77 78 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 79 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 80 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 81 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 82 83 84 /* Description RESERVED 85 86 Reserved: Should be set to 0 by the transmitting MAC and 87 ignored by the PHY <legal 0> 88 */ 89 90 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 91 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 92 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 93 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 94 95 96 /* Description RX_INTEGRITY_CHECK_PASSED 97 98 TX side: Set to 0 99 RX side: Set to 1 if PHY determines the .11b PHY header 100 CRC check has passed, else set to 0 101 102 <legal all> 103 */ 104 105 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 106 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 107 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 108 #define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 109 110 111 /* Description TLV64_PADDING 112 113 Automatic DWORD padding inserted while converting TLV32 114 to TLV64 for 64 bit ARCH 115 <legal 0> 116 */ 117 118 #define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 119 #define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 120 #define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 121 #define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 122 123 124 125 #endif // PHYRX_L_SIG_B 126