1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 27 #define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 32 33 #define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 34 35 36 struct phyrx_other_receive_info_ru_details { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t ru_details_channel_0 : 32; // [31:0] 39 uint32_t ru_details_channel_1 : 32; // [31:0] 40 uint32_t spare : 32; // [31:0] 41 uint32_t tlv64_padding : 32; // [31:0] 42 #else 43 uint32_t ru_details_channel_0 : 32; // [31:0] 44 uint32_t ru_details_channel_1 : 32; // [31:0] 45 uint32_t spare : 32; // [31:0] 46 uint32_t tlv64_padding : 32; // [31:0] 47 #endif 48 }; 49 50 51 /* Description RU_DETAILS_CHANNEL_0 52 53 Ru_allocation from content channel 0 54 [7:0] for 20/40 MHz 55 [15:0] for 80 MHz 56 [31:0] for 160 MHz 57 <legal all> 58 */ 59 60 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 61 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 62 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 63 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff 64 65 66 /* Description RU_DETAILS_CHANNEL_1 67 68 Ru_allocation from content channel 1 69 [7:0] for 40 MHz 70 [15:0] for 80 MHz 71 [31:0] for 160 MHz 72 <legal all> 73 */ 74 75 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 76 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 77 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 78 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 79 80 81 /* Description SPARE 82 83 Extra spare bits added to convey additional information 84 <legal all> 85 */ 86 87 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 88 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 89 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 90 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff 91 92 93 /* Description TLV64_PADDING 94 95 Automatic DWORD padding inserted while converting TLV32 96 to TLV64 for 64 bit ARCH 97 <legal 0> 98 */ 99 100 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 101 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 102 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 103 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 104 105 106 107 #endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 108