1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_PKT_END_H_ 27 #define _PHYRX_PKT_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phyrx_pkt_end_info.h" 32 #define NUM_OF_DWORDS_PHYRX_PKT_END 24 33 34 #define NUM_OF_QWORDS_PHYRX_PKT_END 12 35 36 37 struct phyrx_pkt_end { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct phyrx_pkt_end_info rx_pkt_end_details; 40 #else 41 struct phyrx_pkt_end_info rx_pkt_end_details; 42 #endif 43 }; 44 45 46 /* Description RX_PKT_END_DETAILS 47 48 Overview of the final receive related parameters from the 49 PHY RX 50 */ 51 52 53 /* Description PHY_INTERNAL_NAP 54 55 When set, PHY RX entered an internal NAP state, as PHY determined 56 that this reception was not destined to this device 57 */ 58 59 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000 60 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 61 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0 62 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001 63 64 65 /* Description LOCATION_INFO_VALID 66 67 Indicates that the RX_LOCATION_INFO structure later on in 68 the TLV contains valid info 69 */ 70 71 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 72 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 73 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 74 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 75 76 77 /* Description TIMING_INFO_VALID 78 79 Indicates that the RX_TIMING_OFFSET_INFO structure later 80 on in the TLV contains valid info 81 */ 82 83 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 84 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 85 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 86 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 87 88 89 /* Description RSSI_INFO_VALID 90 91 Indicates that the RECEIVE_RSSI_INFO structure later on 92 in the TLV contains valid info 93 */ 94 95 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 96 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 97 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 98 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 99 100 101 /* Description RESERVED_0A 102 103 <legal 0> 104 */ 105 106 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 107 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 108 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 109 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 110 111 112 /* Description FRAMELESS_FRAME_RECEIVED 113 114 When set, PHY has received the 'frameless frame' . Can be 115 used in the 'MU-RTS -CTS exchange where CTS reception can 116 be problematic. 117 <legal all> 118 */ 119 120 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 121 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 122 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 123 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 124 125 126 /* Description RESERVED_0B 127 128 <legal 0> 129 */ 130 131 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 132 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 133 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 134 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 135 136 137 /* Description RSSI_COMB 138 139 Combined rssi of all chains. Based on primary channel RSSI. 140 141 142 This can be used by SW for cases, e.g. Ack/BlockAck responses, 143 where 'PHYRX_RSSI_LEGACY' is not available to SW. 144 145 RSSI is reported as 8b signed values. Nominally value is 146 in dB units above or below the noisefloor(minCCApwr). 147 148 The resolution can be: 149 1dB or 0.5dB. This is statically configured within the PHY 150 and MAC 151 152 In case of 1dB, the Range is: 153 -128dB to 127dB 154 155 In case of 0.5dB, the Range is: 156 -64dB to 63.5dB 157 158 <legal all> 159 */ 160 161 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 162 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 163 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 164 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 165 166 167 /* Description RESERVED_0C 168 169 <legal 0> 170 */ 171 172 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 173 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 174 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 175 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 176 177 178 /* Description PHY_TIMESTAMP_1_LOWER_32 179 180 TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI 181 of the first rising edge of rx_clear_pri after TX_PHY_DESC. . 182 This field should set to 0 by the PHY and should be updated 183 by the AMPI before being forwarded to the rest of the MAC. 184 This field indicates the lower 32 bits of the timestamp 185 */ 186 187 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 188 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 189 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 190 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 191 192 193 /* Description PHY_TIMESTAMP_1_UPPER_32 194 195 TODO PHY: cleanup description 196 The PHY timestamp in the AMPI of the first rising edge of 197 rx_clear_pri after TX_PHY_DESC. This field should set 198 to 0 by the PHY and should be updated by the AMPI before 199 being forwarded to the rest of the MAC. This field indicates 200 the upper 32 bits of the timestamp 201 */ 202 203 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 204 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 205 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 206 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff 207 208 209 /* Description PHY_TIMESTAMP_2_LOWER_32 210 211 TODO PHY: cleanup description 212 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 213 after RX_RSSI_LEGACY. This field should set to 0 by the 214 PHY and should be updated by the AMPI before being forwarded 215 to the rest of the MAC. This field indicates the lower 216 32 bits of the timestamp 217 */ 218 219 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 220 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 221 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 222 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 223 224 225 /* Description PHY_TIMESTAMP_2_UPPER_32 226 227 TODO PHY: cleanup description 228 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 229 after RX_RSSI_LEGACY. This field should set to 0 by the 230 PHY and should be updated by the AMPI before being forwarded 231 to the rest of the MAC. This field indicates the upper 232 32 bits of the timestamp 233 */ 234 235 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 236 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 237 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 238 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff 239 240 241 /* Description RX_TIMING_OFFSET_INFO_DETAILS 242 243 Overview of timing offset related info 244 */ 245 246 247 /* Description RESIDUAL_PHASE_OFFSET 248 249 Cumulative reference frequency error at end of RX packet, 250 expressed as the phase offset measured over 0.8us. 251 <legal all> 252 */ 253 254 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 255 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 256 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 257 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 258 259 260 /* Description RESERVED 261 262 <legal 0> 263 */ 264 265 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 266 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 267 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 268 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 269 270 271 /* Description POST_RSSI_INFO_DETAILS 272 273 Overview of the post-RSSI values. 274 */ 275 276 277 /* Description RSSI_PRI20_CHAIN0 278 279 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 280 281 Value of 0x80 indicates invalid. 282 */ 283 284 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 285 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 286 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 287 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 288 289 290 /* Description RSSI_EXT20_CHAIN0 291 292 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 293 294 Value of 0x80 indicates invalid. 295 */ 296 297 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 298 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 299 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 300 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 301 302 303 /* Description RSSI_EXT40_LOW20_CHAIN0 304 305 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 306 307 Value of 0x80 indicates invalid. 308 */ 309 310 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 311 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 312 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 313 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 314 315 316 /* Description RSSI_EXT40_HIGH20_CHAIN0 317 318 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 319 bandwidth. 320 Value of 0x80 indicates invalid. 321 */ 322 323 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 324 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 325 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 326 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 327 328 329 /* Description RSSI_EXT80_LOW20_CHAIN0 330 331 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 332 333 Value of 0x80 indicates invalid. 334 */ 335 336 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 337 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 338 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 339 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 340 341 342 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 343 344 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 345 MHz bandwidth. 346 Value of 0x80 indicates invalid. 347 */ 348 349 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 350 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 351 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 352 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 353 354 355 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 356 357 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 358 MHz bandwidth. 359 Value of 0x80 indicates invalid. 360 */ 361 362 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 363 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 364 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 365 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 366 367 368 /* Description RSSI_EXT80_HIGH20_CHAIN0 369 370 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 371 bandwidth. 372 Value of 0x80 indicates invalid. 373 */ 374 375 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 376 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 377 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 378 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 379 380 381 /* Description RSSI_EXT160_0_CHAIN0 382 383 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 384 bandwidth. 385 Value of 0x80 indicates invalid. 386 */ 387 388 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 389 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 390 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 391 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 392 393 394 /* Description RSSI_EXT160_1_CHAIN0 395 396 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 397 bandwidth. 398 Value of 0x80 indicates invalid. 399 */ 400 401 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 402 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 403 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 404 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 405 406 407 /* Description RSSI_EXT160_2_CHAIN0 408 409 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 410 bandwidth. 411 Value of 0x80 indicates invalid. 412 */ 413 414 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 415 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 416 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 417 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 418 419 420 /* Description RSSI_EXT160_3_CHAIN0 421 422 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 423 bandwidth. 424 Value of 0x80 indicates invalid. 425 */ 426 427 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 428 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 429 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 430 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 431 432 433 /* Description RSSI_EXT160_4_CHAIN0 434 435 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 436 bandwidth. 437 Value of 0x80 indicates invalid. 438 */ 439 440 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 441 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 442 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 443 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 444 445 446 /* Description RSSI_EXT160_5_CHAIN0 447 448 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 449 bandwidth. 450 Value of 0x80 indicates invalid. 451 */ 452 453 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 454 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 455 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 456 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 457 458 459 /* Description RSSI_EXT160_6_CHAIN0 460 461 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 462 bandwidth. 463 Value of 0x80 indicates invalid. 464 */ 465 466 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 467 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 468 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 469 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 470 471 472 /* Description RSSI_EXT160_7_CHAIN0 473 474 RSSI of RX PPDU on chain 0 of extension 160, highest 20 475 MHz bandwidth. 476 Value of 0x80 indicates invalid. 477 */ 478 479 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 480 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 481 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 482 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 483 484 485 /* Description RSSI_PRI20_CHAIN1 486 487 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 488 489 Value of 0x80 indicates invalid. 490 */ 491 492 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 493 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 494 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 495 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 496 497 498 /* Description RSSI_EXT20_CHAIN1 499 500 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 501 502 Value of 0x80 indicates invalid. 503 */ 504 505 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 506 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 507 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 508 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 509 510 511 /* Description RSSI_EXT40_LOW20_CHAIN1 512 513 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 514 515 Value of 0x80 indicates invalid. 516 */ 517 518 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 519 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 520 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 521 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 522 523 524 /* Description RSSI_EXT40_HIGH20_CHAIN1 525 526 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 527 bandwidth. 528 Value of 0x80 indicates invalid. 529 */ 530 531 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 532 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 533 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 534 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 535 536 537 /* Description RSSI_EXT80_LOW20_CHAIN1 538 539 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 540 541 Value of 0x80 indicates invalid. 542 */ 543 544 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 545 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 546 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 547 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 548 549 550 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 551 552 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 553 MHz bandwidth. 554 Value of 0x80 indicates invalid. 555 */ 556 557 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 558 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 559 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 560 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 561 562 563 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 564 565 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 566 MHz bandwidth. 567 Value of 0x80 indicates invalid. 568 */ 569 570 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 571 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 572 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 573 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 574 575 576 /* Description RSSI_EXT80_HIGH20_CHAIN1 577 578 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 579 bandwidth. 580 Value of 0x80 indicates invalid. 581 */ 582 583 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 584 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 585 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 586 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 587 588 589 /* Description RSSI_EXT160_0_CHAIN1 590 591 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 592 bandwidth. 593 Value of 0x80 indicates invalid. 594 */ 595 596 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 597 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 598 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 599 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 600 601 602 /* Description RSSI_EXT160_1_CHAIN1 603 604 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 605 bandwidth. 606 Value of 0x80 indicates invalid. 607 */ 608 609 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 610 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 611 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 612 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 613 614 615 /* Description RSSI_EXT160_2_CHAIN1 616 617 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 618 bandwidth. 619 Value of 0x80 indicates invalid. 620 */ 621 622 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 623 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 624 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 625 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 626 627 628 /* Description RSSI_EXT160_3_CHAIN1 629 630 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 631 bandwidth. 632 Value of 0x80 indicates invalid. 633 */ 634 635 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 636 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 637 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 638 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 639 640 641 /* Description RSSI_EXT160_4_CHAIN1 642 643 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 644 bandwidth. 645 Value of 0x80 indicates invalid. 646 */ 647 648 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 649 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 650 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 651 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 652 653 654 /* Description RSSI_EXT160_5_CHAIN1 655 656 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 657 bandwidth. 658 Value of 0x80 indicates invalid. 659 */ 660 661 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 662 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 663 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 664 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 665 666 667 /* Description RSSI_EXT160_6_CHAIN1 668 669 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 670 bandwidth. 671 Value of 0x80 indicates invalid. 672 */ 673 674 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 675 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 676 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 677 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 678 679 680 /* Description RSSI_EXT160_7_CHAIN1 681 682 RSSI of RX PPDU on chain 1 of extension 160, highest 20 683 MHz bandwidth. 684 Value of 0x80 indicates invalid. 685 */ 686 687 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 688 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 689 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 690 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 691 692 693 /* Description RSSI_PRI20_CHAIN2 694 695 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 696 697 Value of 0x80 indicates invalid. 698 */ 699 700 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 701 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 702 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 703 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 704 705 706 /* Description RSSI_EXT20_CHAIN2 707 708 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 709 710 Value of 0x80 indicates invalid. 711 */ 712 713 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 714 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 715 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 716 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 717 718 719 /* Description RSSI_EXT40_LOW20_CHAIN2 720 721 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 722 723 Value of 0x80 indicates invalid. 724 */ 725 726 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 727 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 728 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 729 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 730 731 732 /* Description RSSI_EXT40_HIGH20_CHAIN2 733 734 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 735 bandwidth. 736 Value of 0x80 indicates invalid. 737 */ 738 739 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 740 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 741 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 742 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 743 744 745 /* Description RSSI_EXT80_LOW20_CHAIN2 746 747 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 748 749 Value of 0x80 indicates invalid. 750 */ 751 752 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 753 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 754 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 755 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 756 757 758 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 759 760 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 761 MHz bandwidth. 762 Value of 0x80 indicates invalid. 763 */ 764 765 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 766 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 767 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 768 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 769 770 771 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 772 773 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 774 MHz bandwidth. 775 Value of 0x80 indicates invalid. 776 */ 777 778 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 779 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 780 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 781 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 782 783 784 /* Description RSSI_EXT80_HIGH20_CHAIN2 785 786 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 787 bandwidth. 788 Value of 0x80 indicates invalid. 789 */ 790 791 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 792 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 793 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 794 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 795 796 797 /* Description RSSI_EXT160_0_CHAIN2 798 799 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 800 bandwidth. 801 Value of 0x80 indicates invalid. 802 */ 803 804 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 805 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 806 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 807 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 808 809 810 /* Description RSSI_EXT160_1_CHAIN2 811 812 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 813 bandwidth. 814 Value of 0x80 indicates invalid. 815 */ 816 817 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 818 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 819 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 820 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 821 822 823 /* Description RSSI_EXT160_2_CHAIN2 824 825 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 826 bandwidth. 827 Value of 0x80 indicates invalid. 828 */ 829 830 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 831 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 832 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 833 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 834 835 836 /* Description RSSI_EXT160_3_CHAIN2 837 838 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 839 bandwidth. 840 Value of 0x80 indicates invalid. 841 */ 842 843 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 844 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 845 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 846 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 847 848 849 /* Description RSSI_EXT160_4_CHAIN2 850 851 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 852 bandwidth. 853 Value of 0x80 indicates invalid. 854 */ 855 856 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 857 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 858 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 859 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 860 861 862 /* Description RSSI_EXT160_5_CHAIN2 863 864 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 865 bandwidth. 866 Value of 0x80 indicates invalid. 867 */ 868 869 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 870 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 871 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 872 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 873 874 875 /* Description RSSI_EXT160_6_CHAIN2 876 877 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 878 bandwidth. 879 Value of 0x80 indicates invalid. 880 */ 881 882 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 883 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 884 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 885 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 886 887 888 /* Description RSSI_EXT160_7_CHAIN2 889 890 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 891 bandwidth. 892 Value of 0x80 indicates invalid. 893 */ 894 895 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 896 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 897 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 898 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 899 900 901 /* Description RSSI_PRI20_CHAIN3 902 903 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 904 905 Value of 0x80 indicates invalid. 906 */ 907 908 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 909 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 910 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 911 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 912 913 914 /* Description RSSI_EXT20_CHAIN3 915 916 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 917 918 Value of 0x80 indicates invalid. 919 */ 920 921 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 922 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 923 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 924 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 925 926 927 /* Description RSSI_EXT40_LOW20_CHAIN3 928 929 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 930 931 Value of 0x80 indicates invalid. 932 */ 933 934 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 935 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 936 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 937 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 938 939 940 /* Description RSSI_EXT40_HIGH20_CHAIN3 941 942 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 943 bandwidth. 944 Value of 0x80 indicates invalid. 945 */ 946 947 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 948 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 949 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 950 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 951 952 953 /* Description RSSI_EXT80_LOW20_CHAIN3 954 955 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 956 957 Value of 0x80 indicates invalid. 958 */ 959 960 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 961 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 962 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 963 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 964 965 966 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 967 968 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 969 MHz bandwidth. 970 Value of 0x80 indicates invalid. 971 */ 972 973 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 974 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 975 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 976 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 977 978 979 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 980 981 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 982 MHz bandwidth. 983 Value of 0x80 indicates invalid. 984 */ 985 986 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 987 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 988 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 989 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 990 991 992 /* Description RSSI_EXT80_HIGH20_CHAIN3 993 994 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 995 bandwidth. 996 Value of 0x80 indicates invalid. 997 */ 998 999 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 1000 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 1001 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 1002 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 1003 1004 1005 /* Description RSSI_EXT160_0_CHAIN3 1006 1007 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1008 bandwidth. 1009 Value of 0x80 indicates invalid. 1010 */ 1011 1012 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 1013 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1014 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1015 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1016 1017 1018 /* Description RSSI_EXT160_1_CHAIN3 1019 1020 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1021 bandwidth. 1022 Value of 0x80 indicates invalid. 1023 */ 1024 1025 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 1026 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1027 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1028 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1029 1030 1031 /* Description RSSI_EXT160_2_CHAIN3 1032 1033 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1034 bandwidth. 1035 Value of 0x80 indicates invalid. 1036 */ 1037 1038 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 1039 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1040 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1041 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1042 1043 1044 /* Description RSSI_EXT160_3_CHAIN3 1045 1046 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1047 bandwidth. 1048 Value of 0x80 indicates invalid. 1049 */ 1050 1051 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 1052 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1053 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1054 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1055 1056 1057 /* Description RSSI_EXT160_4_CHAIN3 1058 1059 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1060 bandwidth. 1061 Value of 0x80 indicates invalid. 1062 */ 1063 1064 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 1065 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1066 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1067 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1068 1069 1070 /* Description RSSI_EXT160_5_CHAIN3 1071 1072 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1073 bandwidth. 1074 Value of 0x80 indicates invalid. 1075 */ 1076 1077 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 1078 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1079 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1080 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1081 1082 1083 /* Description RSSI_EXT160_6_CHAIN3 1084 1085 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1086 bandwidth. 1087 Value of 0x80 indicates invalid. 1088 */ 1089 1090 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 1091 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1092 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1093 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 1094 1095 1096 /* Description RSSI_EXT160_7_CHAIN3 1097 1098 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1099 MHz bandwidth. 1100 Value of 0x80 indicates invalid. 1101 */ 1102 1103 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 1104 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 1105 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 1106 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 1107 1108 1109 /* Description PHY_SW_STATUS_31_0 1110 1111 Some PHY micro code status that can be put in here. Details 1112 of definition within SW specification 1113 This field can be used for debugging, FW - SW message exchange, 1114 etc. 1115 It could for example be a pointer to a DDR memory location 1116 where PHY FW put some debug info. 1117 <legal all> 1118 */ 1119 1120 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 1121 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 1122 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 1123 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff 1124 1125 1126 /* Description PHY_SW_STATUS_63_32 1127 1128 Some PHY micro code status that can be put in here. Details 1129 of definition within SW specification 1130 This field can be used for debugging, FW - SW message exchange, 1131 etc. 1132 It could for example be a pointer to a DDR memory location 1133 where PHY FW put some debug info. 1134 <legal all> 1135 */ 1136 1137 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 1138 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 1139 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 1140 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 1141 1142 1143 1144 #endif // PHYRX_PKT_END 1145