1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_RSSI_LEGACY_H_ 27 #define _PHYRX_RSSI_LEGACY_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "receive_rssi_info.h" 32 #define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 33 34 #define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 35 36 37 struct phyrx_rssi_legacy { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t reception_type : 4, // [3:0] 40 rx_chain_mask_type : 1, // [4:4] 41 receive_bandwidth : 3, // [7:5] 42 rx_chain_mask : 8, // [15:8] 43 phy_ppdu_id : 16; // [31:16] 44 uint32_t sw_phy_meta_data : 32; // [31:0] 45 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 46 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 47 uint32_t reserved_4a : 32; // [31:0] 48 uint32_t preamble_time_to_rxframe : 8, // [7:0] 49 standalone_snifer_mode : 1, // [8:8] 50 reserved_5a : 23; // [31:9] 51 uint32_t reserved_6a : 32; // [31:0] 52 uint32_t reserved_7a : 32; // [31:0] 53 struct receive_rssi_info pre_rssi_info_details; 54 struct receive_rssi_info preamble_rssi_info_details; 55 uint32_t pre_rssi_comb : 8, // [7:0] 56 rssi_comb : 8, // [15:8] 57 normalized_pre_rssi_comb : 8, // [23:16] 58 normalized_rssi_comb : 8; // [31:24] 59 uint32_t rssi_comb_ppdu : 8, // [7:0] 60 rssi_db_to_dbm_offset : 8, // [15:8] 61 rssi_for_spatial_reuse : 8, // [23:16] 62 rssi_for_trigger_resp : 8; // [31:24] 63 #else 64 uint32_t phy_ppdu_id : 16, // [31:16] 65 rx_chain_mask : 8, // [15:8] 66 receive_bandwidth : 3, // [7:5] 67 rx_chain_mask_type : 1, // [4:4] 68 reception_type : 4; // [3:0] 69 uint32_t sw_phy_meta_data : 32; // [31:0] 70 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 71 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 72 uint32_t reserved_4a : 32; // [31:0] 73 uint32_t reserved_5a : 23, // [31:9] 74 standalone_snifer_mode : 1, // [8:8] 75 preamble_time_to_rxframe : 8; // [7:0] 76 uint32_t reserved_6a : 32; // [31:0] 77 uint32_t reserved_7a : 32; // [31:0] 78 struct receive_rssi_info pre_rssi_info_details; 79 struct receive_rssi_info preamble_rssi_info_details; 80 uint32_t normalized_rssi_comb : 8, // [31:24] 81 normalized_pre_rssi_comb : 8, // [23:16] 82 rssi_comb : 8, // [15:8] 83 pre_rssi_comb : 8; // [7:0] 84 uint32_t rssi_for_trigger_resp : 8, // [31:24] 85 rssi_for_spatial_reuse : 8, // [23:16] 86 rssi_db_to_dbm_offset : 8, // [15:8] 87 rssi_comb_ppdu : 8; // [7:0] 88 #endif 89 }; 90 91 92 /* Description RECEPTION_TYPE 93 94 This field helps MAC SW determine which field in this (and 95 following TLVs) will contain valid information. For example 96 some RSSI info not valid in case of uplink_ofdma.. 97 98 In case of UL MU OFDMA or UL MU-MIMO reception pre-announced 99 by MAC during trigger Tx, e-nums 0 or 1 should be used. 100 101 102 In case of UL MU OFDMA+MIMO reception, or in case of UL 103 MU reception when PHY has not been pre-informed, e-num 2 104 should be used. 105 If this happens, the UL MU frame in the medium is by definition 106 not for this device. 107 As reference, see doc: 108 Lithium_mac_phy_interface_hld.docx 109 Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when 110 this device is not targeted. 111 112 <enum 0 reception_is_uplink_ofdma> 113 <enum 1 reception_is_uplink_mimo> 114 <enum 2 reception_is_other> 115 <enum 3 reception_is_frameless> PHY RX has been instructed 116 in advance that the upcoming reception is frameless. This 117 implieas that in advance it is known that all frames will 118 collide in the medium, and nothing can be properly decoded... 119 This can happen during the CTS reception in response to 120 the triggered MU-RTS transmission. 121 MAC takes no action when seeing this e_num. For the frameless 122 reception the indication in pkt_end is the final one evaluated 123 by the MAC 124 125 For the relationship between pkt_type and this field, see 126 the table at the end of this TLV description. 127 <legal 0-3> 128 */ 129 130 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 131 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 132 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 133 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f 134 135 136 /* Description RX_CHAIN_MASK_TYPE 137 138 Indicates if the field rx_chain_mask represents the mask 139 at start of reception (on which the Rssi_comb value is 140 based), or the setting used during the remainder of the 141 reception 142 143 1'b0: rxtd.listen_pri80_mask 144 1'b1: Final receive mask 145 146 <legal all> 147 */ 148 149 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 150 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 151 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 152 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 153 154 155 /* Description RECEIVE_BANDWIDTH 156 157 Full receive Bandwidth 158 159 <enum 0 20_mhz>20 Mhz BW 160 <enum 1 40_mhz>40 Mhz BW 161 <enum 2 80_mhz>80 Mhz BW 162 <enum 3 160_mhz>160 Mhz BW 163 <enum 4 320_mhz>320 Mhz BW 164 <enum 5 240_mhz>240 Mhz BW 165 */ 166 167 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 168 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 169 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 170 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 171 172 173 /* Description RX_CHAIN_MASK 174 175 The chain mask at the start of the reception of this frame. 176 177 178 each bit is one antenna 179 0: the chain is NOT used 180 1: the chain is used 181 182 Supports up to 8 chains 183 184 Used in 11ax TPC calculations for UL OFDMA/MIMO and has 185 to be in sync with the rssi_comb value as this is also used 186 by the MAC for the TPC calculations. 187 <legal all> 188 */ 189 190 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 191 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 192 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 193 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 194 195 196 /* Description PHY_PPDU_ID 197 198 A ppdu counter value that PHY increments for every PPDU 199 received. The counter value wraps around 200 <legal all> 201 */ 202 203 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 204 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 205 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 206 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 207 208 209 /* Description SW_PHY_META_DATA 210 211 32 bit Meta data that SW can program in a 32 bit PHY register 212 and PHY will insert the value in every RX_RSSI_LEGACY TLV 213 that it generates. 214 SW uses this field to embed among other things some SW channel 215 info. 216 */ 217 218 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 219 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 220 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 221 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 222 223 224 /* Description PPDU_START_TIMESTAMP_31_0 225 226 Timestamp that indicates when the PPDU that contained this 227 MPDU started on the medium, lower 32 bits 228 229 Note that PHY will detect the start later, and will have 230 to derive out of the preamble info when the frame actually 231 appeared on the medium. 232 */ 233 234 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 235 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 236 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 237 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 238 239 240 /* Description PPDU_START_TIMESTAMP_63_32 241 242 Timestamp that indicates when the PPDU that contained this 243 MPDU started on the medium, upper 32 bits 244 245 Note that PHY will detect the start later, and will have 246 to derive out of the preamble info when the frame actually 247 appeared on the medium. 248 */ 249 250 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 251 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 252 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 253 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 254 255 256 /* Description RESERVED_4A 257 258 NOTE: DO not assign a field... Internally used in RXPCU 259 to store 'RX_PPDU_START::Rxframe_assert_timestamp.' 260 <legal 0> 261 */ 262 263 #define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 264 #define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 265 #define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 266 #define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff 267 268 269 /* Description PREAMBLE_TIME_TO_RXFRAME 270 271 The time taken (in us) from the frame starting on the medium 272 and PHY raising 'rx_frame' 273 <legal all> 274 */ 275 276 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 277 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 278 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 279 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 280 281 282 /* Description STANDALONE_SNIFER_MODE 283 284 When set to 1, PHY has been configured to operate in the 285 stand alone sniffer mode. 286 When 0, PHY is operating in the "normal" mission mode. 287 <legal all> 288 */ 289 290 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 291 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 292 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 293 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 294 295 296 /* Description RESERVED_5A 297 298 <legal 0> 299 */ 300 301 #define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 302 #define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 303 #define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 304 #define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 305 306 307 /* Description RESERVED_6A 308 309 NOTE: DO not assign a field... Internally used in RXPCU 310 to construct 'RX_PPDU_START.' 311 <legal 0> 312 */ 313 314 #define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 315 #define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 316 #define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 317 #define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff 318 319 320 /* Description RESERVED_7A 321 322 NOTE: DO not assign a field... Internally used in RXPCU 323 to construct 'RX_PPDU_START.' 324 <legal 0> 325 */ 326 327 #define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 328 #define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 329 #define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 330 #define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 331 332 333 /* Description PRE_RSSI_INFO_DETAILS 334 335 This field is not valid when reception_is_uplink_ofdma 336 337 Overview of the pre-RSSI values. That is RSSI values measured 338 on the medium before this reception started. 339 */ 340 341 342 /* Description RSSI_PRI20_CHAIN0 343 344 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 345 346 Value of 0x80 indicates invalid. 347 */ 348 349 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 350 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 351 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 352 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 353 354 355 /* Description RSSI_EXT20_CHAIN0 356 357 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 358 359 Value of 0x80 indicates invalid. 360 */ 361 362 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 363 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 364 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 365 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 366 367 368 /* Description RSSI_EXT40_LOW20_CHAIN0 369 370 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 371 372 Value of 0x80 indicates invalid. 373 */ 374 375 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 376 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 377 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 378 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 379 380 381 /* Description RSSI_EXT40_HIGH20_CHAIN0 382 383 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 384 bandwidth. 385 Value of 0x80 indicates invalid. 386 */ 387 388 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 389 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 390 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 391 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 392 393 394 /* Description RSSI_EXT80_LOW20_CHAIN0 395 396 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 397 398 Value of 0x80 indicates invalid. 399 */ 400 401 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 402 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 403 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 404 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 405 406 407 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 408 409 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 410 MHz bandwidth. 411 Value of 0x80 indicates invalid. 412 */ 413 414 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 415 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 416 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 417 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 418 419 420 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 421 422 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 423 MHz bandwidth. 424 Value of 0x80 indicates invalid. 425 */ 426 427 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 428 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 429 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 430 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 431 432 433 /* Description RSSI_EXT80_HIGH20_CHAIN0 434 435 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 436 bandwidth. 437 Value of 0x80 indicates invalid. 438 */ 439 440 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 441 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 442 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 443 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 444 445 446 /* Description RSSI_EXT160_0_CHAIN0 447 448 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 449 bandwidth. 450 Value of 0x80 indicates invalid. 451 */ 452 453 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 454 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 455 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 456 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 457 458 459 /* Description RSSI_EXT160_1_CHAIN0 460 461 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 462 bandwidth. 463 Value of 0x80 indicates invalid. 464 */ 465 466 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 467 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 468 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 469 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 470 471 472 /* Description RSSI_EXT160_2_CHAIN0 473 474 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 475 bandwidth. 476 Value of 0x80 indicates invalid. 477 */ 478 479 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 480 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 481 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 482 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 483 484 485 /* Description RSSI_EXT160_3_CHAIN0 486 487 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 488 bandwidth. 489 Value of 0x80 indicates invalid. 490 */ 491 492 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 493 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 494 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 495 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 496 497 498 /* Description RSSI_EXT160_4_CHAIN0 499 500 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 501 bandwidth. 502 Value of 0x80 indicates invalid. 503 */ 504 505 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 506 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 507 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 508 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 509 510 511 /* Description RSSI_EXT160_5_CHAIN0 512 513 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 514 bandwidth. 515 Value of 0x80 indicates invalid. 516 */ 517 518 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 519 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 520 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 521 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 522 523 524 /* Description RSSI_EXT160_6_CHAIN0 525 526 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 527 bandwidth. 528 Value of 0x80 indicates invalid. 529 */ 530 531 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 532 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 533 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 534 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 535 536 537 /* Description RSSI_EXT160_7_CHAIN0 538 539 RSSI of RX PPDU on chain 0 of extension 160, highest 20 540 MHz bandwidth. 541 Value of 0x80 indicates invalid. 542 */ 543 544 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 545 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 546 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 547 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 548 549 550 /* Description RSSI_PRI20_CHAIN1 551 552 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 553 554 Value of 0x80 indicates invalid. 555 */ 556 557 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 558 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 559 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 560 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 561 562 563 /* Description RSSI_EXT20_CHAIN1 564 565 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 566 567 Value of 0x80 indicates invalid. 568 */ 569 570 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 571 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 572 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 573 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 574 575 576 /* Description RSSI_EXT40_LOW20_CHAIN1 577 578 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 579 580 Value of 0x80 indicates invalid. 581 */ 582 583 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 584 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 585 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 586 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 587 588 589 /* Description RSSI_EXT40_HIGH20_CHAIN1 590 591 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 592 bandwidth. 593 Value of 0x80 indicates invalid. 594 */ 595 596 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 597 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 598 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 599 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 600 601 602 /* Description RSSI_EXT80_LOW20_CHAIN1 603 604 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 605 606 Value of 0x80 indicates invalid. 607 */ 608 609 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 610 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 611 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 612 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 613 614 615 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 616 617 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 618 MHz bandwidth. 619 Value of 0x80 indicates invalid. 620 */ 621 622 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 623 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 624 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 625 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 626 627 628 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 629 630 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 631 MHz bandwidth. 632 Value of 0x80 indicates invalid. 633 */ 634 635 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 636 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 637 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 638 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 639 640 641 /* Description RSSI_EXT80_HIGH20_CHAIN1 642 643 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 644 bandwidth. 645 Value of 0x80 indicates invalid. 646 */ 647 648 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 649 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 650 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 651 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 652 653 654 /* Description RSSI_EXT160_0_CHAIN1 655 656 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 657 bandwidth. 658 Value of 0x80 indicates invalid. 659 */ 660 661 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 662 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 663 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 664 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 665 666 667 /* Description RSSI_EXT160_1_CHAIN1 668 669 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 670 bandwidth. 671 Value of 0x80 indicates invalid. 672 */ 673 674 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 675 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 676 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 677 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 678 679 680 /* Description RSSI_EXT160_2_CHAIN1 681 682 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 683 bandwidth. 684 Value of 0x80 indicates invalid. 685 */ 686 687 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 688 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 689 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 690 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 691 692 693 /* Description RSSI_EXT160_3_CHAIN1 694 695 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 696 bandwidth. 697 Value of 0x80 indicates invalid. 698 */ 699 700 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 701 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 702 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 703 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 704 705 706 /* Description RSSI_EXT160_4_CHAIN1 707 708 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 709 bandwidth. 710 Value of 0x80 indicates invalid. 711 */ 712 713 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 714 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 715 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 716 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 717 718 719 /* Description RSSI_EXT160_5_CHAIN1 720 721 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 722 bandwidth. 723 Value of 0x80 indicates invalid. 724 */ 725 726 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 727 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 728 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 729 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 730 731 732 /* Description RSSI_EXT160_6_CHAIN1 733 734 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 735 bandwidth. 736 Value of 0x80 indicates invalid. 737 */ 738 739 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 740 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 741 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 742 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 743 744 745 /* Description RSSI_EXT160_7_CHAIN1 746 747 RSSI of RX PPDU on chain 1 of extension 160, highest 20 748 MHz bandwidth. 749 Value of 0x80 indicates invalid. 750 */ 751 752 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 753 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 754 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 755 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 756 757 758 /* Description RSSI_PRI20_CHAIN2 759 760 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 761 762 Value of 0x80 indicates invalid. 763 */ 764 765 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 766 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 767 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 768 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 769 770 771 /* Description RSSI_EXT20_CHAIN2 772 773 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 774 775 Value of 0x80 indicates invalid. 776 */ 777 778 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 779 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 780 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 781 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 782 783 784 /* Description RSSI_EXT40_LOW20_CHAIN2 785 786 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 787 788 Value of 0x80 indicates invalid. 789 */ 790 791 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 792 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 793 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 794 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 795 796 797 /* Description RSSI_EXT40_HIGH20_CHAIN2 798 799 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 800 bandwidth. 801 Value of 0x80 indicates invalid. 802 */ 803 804 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 805 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 806 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 807 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 808 809 810 /* Description RSSI_EXT80_LOW20_CHAIN2 811 812 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 813 814 Value of 0x80 indicates invalid. 815 */ 816 817 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 818 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 819 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 820 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 821 822 823 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 824 825 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 826 MHz bandwidth. 827 Value of 0x80 indicates invalid. 828 */ 829 830 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 831 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 832 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 833 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 834 835 836 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 837 838 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 839 MHz bandwidth. 840 Value of 0x80 indicates invalid. 841 */ 842 843 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 844 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 845 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 846 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 847 848 849 /* Description RSSI_EXT80_HIGH20_CHAIN2 850 851 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 852 bandwidth. 853 Value of 0x80 indicates invalid. 854 */ 855 856 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 857 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 858 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 859 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 860 861 862 /* Description RSSI_EXT160_0_CHAIN2 863 864 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 865 bandwidth. 866 Value of 0x80 indicates invalid. 867 */ 868 869 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 870 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 871 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 872 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 873 874 875 /* Description RSSI_EXT160_1_CHAIN2 876 877 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 878 bandwidth. 879 Value of 0x80 indicates invalid. 880 */ 881 882 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 883 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 884 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 885 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 886 887 888 /* Description RSSI_EXT160_2_CHAIN2 889 890 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 891 bandwidth. 892 Value of 0x80 indicates invalid. 893 */ 894 895 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 896 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 897 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 898 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 899 900 901 /* Description RSSI_EXT160_3_CHAIN2 902 903 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 904 bandwidth. 905 Value of 0x80 indicates invalid. 906 */ 907 908 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 909 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 910 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 911 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 912 913 914 /* Description RSSI_EXT160_4_CHAIN2 915 916 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 917 bandwidth. 918 Value of 0x80 indicates invalid. 919 */ 920 921 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 922 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 923 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 924 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 925 926 927 /* Description RSSI_EXT160_5_CHAIN2 928 929 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 930 bandwidth. 931 Value of 0x80 indicates invalid. 932 */ 933 934 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 935 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 936 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 937 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 938 939 940 /* Description RSSI_EXT160_6_CHAIN2 941 942 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 943 bandwidth. 944 Value of 0x80 indicates invalid. 945 */ 946 947 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 948 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 949 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 950 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 951 952 953 /* Description RSSI_EXT160_7_CHAIN2 954 955 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 956 bandwidth. 957 Value of 0x80 indicates invalid. 958 */ 959 960 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 961 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 962 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 963 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 964 965 966 /* Description RSSI_PRI20_CHAIN3 967 968 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 969 970 Value of 0x80 indicates invalid. 971 */ 972 973 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 974 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 975 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 976 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 977 978 979 /* Description RSSI_EXT20_CHAIN3 980 981 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 982 983 Value of 0x80 indicates invalid. 984 */ 985 986 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 987 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 988 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 989 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 990 991 992 /* Description RSSI_EXT40_LOW20_CHAIN3 993 994 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 995 996 Value of 0x80 indicates invalid. 997 */ 998 999 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 1000 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1001 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 1002 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 1003 1004 1005 /* Description RSSI_EXT40_HIGH20_CHAIN3 1006 1007 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1008 bandwidth. 1009 Value of 0x80 indicates invalid. 1010 */ 1011 1012 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1013 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1014 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 1015 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 1016 1017 1018 /* Description RSSI_EXT80_LOW20_CHAIN3 1019 1020 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 1021 1022 Value of 0x80 indicates invalid. 1023 */ 1024 1025 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 1026 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 1027 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 1028 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 1029 1030 1031 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 1032 1033 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1034 MHz bandwidth. 1035 Value of 0x80 indicates invalid. 1036 */ 1037 1038 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1039 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 1040 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 1041 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 1042 1043 1044 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 1045 1046 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1047 MHz bandwidth. 1048 Value of 0x80 indicates invalid. 1049 */ 1050 1051 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 1052 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 1053 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 1054 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 1055 1056 1057 /* Description RSSI_EXT80_HIGH20_CHAIN3 1058 1059 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1060 bandwidth. 1061 Value of 0x80 indicates invalid. 1062 */ 1063 1064 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1065 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 1066 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 1067 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 1068 1069 1070 /* Description RSSI_EXT160_0_CHAIN3 1071 1072 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1073 bandwidth. 1074 Value of 0x80 indicates invalid. 1075 */ 1076 1077 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 1078 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1079 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1080 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1081 1082 1083 /* Description RSSI_EXT160_1_CHAIN3 1084 1085 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1086 bandwidth. 1087 Value of 0x80 indicates invalid. 1088 */ 1089 1090 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 1091 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1092 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1093 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1094 1095 1096 /* Description RSSI_EXT160_2_CHAIN3 1097 1098 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1099 bandwidth. 1100 Value of 0x80 indicates invalid. 1101 */ 1102 1103 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 1104 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1105 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1106 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1107 1108 1109 /* Description RSSI_EXT160_3_CHAIN3 1110 1111 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1112 bandwidth. 1113 Value of 0x80 indicates invalid. 1114 */ 1115 1116 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 1117 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1118 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1119 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1120 1121 1122 /* Description RSSI_EXT160_4_CHAIN3 1123 1124 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1125 bandwidth. 1126 Value of 0x80 indicates invalid. 1127 */ 1128 1129 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 1130 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1131 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1132 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1133 1134 1135 /* Description RSSI_EXT160_5_CHAIN3 1136 1137 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1138 bandwidth. 1139 Value of 0x80 indicates invalid. 1140 */ 1141 1142 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 1143 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1144 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1145 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1146 1147 1148 /* Description RSSI_EXT160_6_CHAIN3 1149 1150 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1151 bandwidth. 1152 Value of 0x80 indicates invalid. 1153 */ 1154 1155 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 1156 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1157 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1158 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 1159 1160 1161 /* Description RSSI_EXT160_7_CHAIN3 1162 1163 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1164 MHz bandwidth. 1165 Value of 0x80 indicates invalid. 1166 */ 1167 1168 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 1169 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 1170 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 1171 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 1172 1173 1174 /* Description PREAMBLE_RSSI_INFO_DETAILS 1175 1176 This field is not valid when reception_is_uplink_ofdma 1177 1178 Overview of the RSSI values measured during the pre-amble 1179 phase of this reception 1180 */ 1181 1182 1183 /* Description RSSI_PRI20_CHAIN0 1184 1185 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1186 1187 Value of 0x80 indicates invalid. 1188 */ 1189 1190 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 1191 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1192 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 1193 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 1194 1195 1196 /* Description RSSI_EXT20_CHAIN0 1197 1198 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 1199 1200 Value of 0x80 indicates invalid. 1201 */ 1202 1203 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 1204 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1205 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 1206 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 1207 1208 1209 /* Description RSSI_EXT40_LOW20_CHAIN0 1210 1211 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 1212 1213 Value of 0x80 indicates invalid. 1214 */ 1215 1216 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 1217 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1218 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 1219 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 1220 1221 1222 /* Description RSSI_EXT40_HIGH20_CHAIN0 1223 1224 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1225 bandwidth. 1226 Value of 0x80 indicates invalid. 1227 */ 1228 1229 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1230 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1231 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 1232 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 1233 1234 1235 /* Description RSSI_EXT80_LOW20_CHAIN0 1236 1237 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 1238 1239 Value of 0x80 indicates invalid. 1240 */ 1241 1242 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 1243 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 1244 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 1245 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 1246 1247 1248 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 1249 1250 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1251 MHz bandwidth. 1252 Value of 0x80 indicates invalid. 1253 */ 1254 1255 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1256 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 1257 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 1258 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 1259 1260 1261 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 1262 1263 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1264 MHz bandwidth. 1265 Value of 0x80 indicates invalid. 1266 */ 1267 1268 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 1269 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 1270 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 1271 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 1272 1273 1274 /* Description RSSI_EXT80_HIGH20_CHAIN0 1275 1276 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1277 bandwidth. 1278 Value of 0x80 indicates invalid. 1279 */ 1280 1281 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1282 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 1283 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 1284 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 1285 1286 1287 /* Description RSSI_EXT160_0_CHAIN0 1288 1289 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 1290 bandwidth. 1291 Value of 0x80 indicates invalid. 1292 */ 1293 1294 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 1295 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 1296 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 1297 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 1298 1299 1300 /* Description RSSI_EXT160_1_CHAIN0 1301 1302 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1303 bandwidth. 1304 Value of 0x80 indicates invalid. 1305 */ 1306 1307 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 1308 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 1309 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 1310 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 1311 1312 1313 /* Description RSSI_EXT160_2_CHAIN0 1314 1315 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1316 bandwidth. 1317 Value of 0x80 indicates invalid. 1318 */ 1319 1320 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 1321 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 1322 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 1323 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 1324 1325 1326 /* Description RSSI_EXT160_3_CHAIN0 1327 1328 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1329 bandwidth. 1330 Value of 0x80 indicates invalid. 1331 */ 1332 1333 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 1334 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 1335 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 1336 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 1337 1338 1339 /* Description RSSI_EXT160_4_CHAIN0 1340 1341 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1342 bandwidth. 1343 Value of 0x80 indicates invalid. 1344 */ 1345 1346 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 1347 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 1348 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 1349 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 1350 1351 1352 /* Description RSSI_EXT160_5_CHAIN0 1353 1354 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1355 bandwidth. 1356 Value of 0x80 indicates invalid. 1357 */ 1358 1359 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 1360 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 1361 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 1362 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 1363 1364 1365 /* Description RSSI_EXT160_6_CHAIN0 1366 1367 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1368 bandwidth. 1369 Value of 0x80 indicates invalid. 1370 */ 1371 1372 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 1373 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 1374 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 1375 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 1376 1377 1378 /* Description RSSI_EXT160_7_CHAIN0 1379 1380 RSSI of RX PPDU on chain 0 of extension 160, highest 20 1381 MHz bandwidth. 1382 Value of 0x80 indicates invalid. 1383 */ 1384 1385 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 1386 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 1387 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 1388 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 1389 1390 1391 /* Description RSSI_PRI20_CHAIN1 1392 1393 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1394 1395 Value of 0x80 indicates invalid. 1396 */ 1397 1398 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 1399 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1400 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 1401 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 1402 1403 1404 /* Description RSSI_EXT20_CHAIN1 1405 1406 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 1407 1408 Value of 0x80 indicates invalid. 1409 */ 1410 1411 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 1412 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1413 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 1414 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 1415 1416 1417 /* Description RSSI_EXT40_LOW20_CHAIN1 1418 1419 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 1420 1421 Value of 0x80 indicates invalid. 1422 */ 1423 1424 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 1425 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1426 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 1427 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 1428 1429 1430 /* Description RSSI_EXT40_HIGH20_CHAIN1 1431 1432 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1433 bandwidth. 1434 Value of 0x80 indicates invalid. 1435 */ 1436 1437 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1438 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1439 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 1440 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 1441 1442 1443 /* Description RSSI_EXT80_LOW20_CHAIN1 1444 1445 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 1446 1447 Value of 0x80 indicates invalid. 1448 */ 1449 1450 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 1451 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 1452 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 1453 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 1454 1455 1456 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 1457 1458 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1459 MHz bandwidth. 1460 Value of 0x80 indicates invalid. 1461 */ 1462 1463 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1464 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 1465 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 1466 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 1467 1468 1469 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 1470 1471 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1472 MHz bandwidth. 1473 Value of 0x80 indicates invalid. 1474 */ 1475 1476 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 1477 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 1478 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 1479 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 1480 1481 1482 /* Description RSSI_EXT80_HIGH20_CHAIN1 1483 1484 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1485 bandwidth. 1486 Value of 0x80 indicates invalid. 1487 */ 1488 1489 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1490 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 1491 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 1492 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 1493 1494 1495 /* Description RSSI_EXT160_0_CHAIN1 1496 1497 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 1498 bandwidth. 1499 Value of 0x80 indicates invalid. 1500 */ 1501 1502 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 1503 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 1504 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 1505 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 1506 1507 1508 /* Description RSSI_EXT160_1_CHAIN1 1509 1510 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1511 bandwidth. 1512 Value of 0x80 indicates invalid. 1513 */ 1514 1515 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 1516 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 1517 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 1518 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 1519 1520 1521 /* Description RSSI_EXT160_2_CHAIN1 1522 1523 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1524 bandwidth. 1525 Value of 0x80 indicates invalid. 1526 */ 1527 1528 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 1529 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 1530 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 1531 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 1532 1533 1534 /* Description RSSI_EXT160_3_CHAIN1 1535 1536 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1537 bandwidth. 1538 Value of 0x80 indicates invalid. 1539 */ 1540 1541 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 1542 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 1543 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 1544 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 1545 1546 1547 /* Description RSSI_EXT160_4_CHAIN1 1548 1549 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1550 bandwidth. 1551 Value of 0x80 indicates invalid. 1552 */ 1553 1554 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 1555 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 1556 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 1557 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 1558 1559 1560 /* Description RSSI_EXT160_5_CHAIN1 1561 1562 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1563 bandwidth. 1564 Value of 0x80 indicates invalid. 1565 */ 1566 1567 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 1568 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 1569 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 1570 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 1571 1572 1573 /* Description RSSI_EXT160_6_CHAIN1 1574 1575 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1576 bandwidth. 1577 Value of 0x80 indicates invalid. 1578 */ 1579 1580 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 1581 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 1582 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 1583 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 1584 1585 1586 /* Description RSSI_EXT160_7_CHAIN1 1587 1588 RSSI of RX PPDU on chain 1 of extension 160, highest 20 1589 MHz bandwidth. 1590 Value of 0x80 indicates invalid. 1591 */ 1592 1593 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 1594 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 1595 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 1596 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 1597 1598 1599 /* Description RSSI_PRI20_CHAIN2 1600 1601 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1602 1603 Value of 0x80 indicates invalid. 1604 */ 1605 1606 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 1607 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1608 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 1609 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 1610 1611 1612 /* Description RSSI_EXT20_CHAIN2 1613 1614 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 1615 1616 Value of 0x80 indicates invalid. 1617 */ 1618 1619 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 1620 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1621 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 1622 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 1623 1624 1625 /* Description RSSI_EXT40_LOW20_CHAIN2 1626 1627 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 1628 1629 Value of 0x80 indicates invalid. 1630 */ 1631 1632 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 1633 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1634 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 1635 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 1636 1637 1638 /* Description RSSI_EXT40_HIGH20_CHAIN2 1639 1640 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1641 bandwidth. 1642 Value of 0x80 indicates invalid. 1643 */ 1644 1645 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1646 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1647 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 1648 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 1649 1650 1651 /* Description RSSI_EXT80_LOW20_CHAIN2 1652 1653 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 1654 1655 Value of 0x80 indicates invalid. 1656 */ 1657 1658 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 1659 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 1660 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 1661 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 1662 1663 1664 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 1665 1666 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1667 MHz bandwidth. 1668 Value of 0x80 indicates invalid. 1669 */ 1670 1671 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1672 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 1673 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 1674 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 1675 1676 1677 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 1678 1679 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1680 MHz bandwidth. 1681 Value of 0x80 indicates invalid. 1682 */ 1683 1684 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 1685 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 1686 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 1687 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 1688 1689 1690 /* Description RSSI_EXT80_HIGH20_CHAIN2 1691 1692 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1693 bandwidth. 1694 Value of 0x80 indicates invalid. 1695 */ 1696 1697 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1698 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 1699 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 1700 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 1701 1702 1703 /* Description RSSI_EXT160_0_CHAIN2 1704 1705 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 1706 bandwidth. 1707 Value of 0x80 indicates invalid. 1708 */ 1709 1710 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 1711 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 1712 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 1713 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 1714 1715 1716 /* Description RSSI_EXT160_1_CHAIN2 1717 1718 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1719 bandwidth. 1720 Value of 0x80 indicates invalid. 1721 */ 1722 1723 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 1724 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 1725 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 1726 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 1727 1728 1729 /* Description RSSI_EXT160_2_CHAIN2 1730 1731 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1732 bandwidth. 1733 Value of 0x80 indicates invalid. 1734 */ 1735 1736 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 1737 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 1738 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 1739 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 1740 1741 1742 /* Description RSSI_EXT160_3_CHAIN2 1743 1744 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1745 bandwidth. 1746 Value of 0x80 indicates invalid. 1747 */ 1748 1749 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 1750 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 1751 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 1752 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 1753 1754 1755 /* Description RSSI_EXT160_4_CHAIN2 1756 1757 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1758 bandwidth. 1759 Value of 0x80 indicates invalid. 1760 */ 1761 1762 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 1763 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 1764 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 1765 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 1766 1767 1768 /* Description RSSI_EXT160_5_CHAIN2 1769 1770 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1771 bandwidth. 1772 Value of 0x80 indicates invalid. 1773 */ 1774 1775 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 1776 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 1777 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 1778 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 1779 1780 1781 /* Description RSSI_EXT160_6_CHAIN2 1782 1783 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1784 bandwidth. 1785 Value of 0x80 indicates invalid. 1786 */ 1787 1788 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 1789 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 1790 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 1791 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 1792 1793 1794 /* Description RSSI_EXT160_7_CHAIN2 1795 1796 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 1797 bandwidth. 1798 Value of 0x80 indicates invalid. 1799 */ 1800 1801 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 1802 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 1803 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 1804 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 1805 1806 1807 /* Description RSSI_PRI20_CHAIN3 1808 1809 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1810 1811 Value of 0x80 indicates invalid. 1812 */ 1813 1814 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 1815 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1816 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 1817 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 1818 1819 1820 /* Description RSSI_EXT20_CHAIN3 1821 1822 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 1823 1824 Value of 0x80 indicates invalid. 1825 */ 1826 1827 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 1828 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1829 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 1830 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 1831 1832 1833 /* Description RSSI_EXT40_LOW20_CHAIN3 1834 1835 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 1836 1837 Value of 0x80 indicates invalid. 1838 */ 1839 1840 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 1841 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1842 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 1843 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 1844 1845 1846 /* Description RSSI_EXT40_HIGH20_CHAIN3 1847 1848 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1849 bandwidth. 1850 Value of 0x80 indicates invalid. 1851 */ 1852 1853 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1854 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1855 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 1856 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 1857 1858 1859 /* Description RSSI_EXT80_LOW20_CHAIN3 1860 1861 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 1862 1863 Value of 0x80 indicates invalid. 1864 */ 1865 1866 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 1867 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 1868 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 1869 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 1870 1871 1872 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 1873 1874 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1875 MHz bandwidth. 1876 Value of 0x80 indicates invalid. 1877 */ 1878 1879 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1880 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 1881 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 1882 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 1883 1884 1885 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 1886 1887 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1888 MHz bandwidth. 1889 Value of 0x80 indicates invalid. 1890 */ 1891 1892 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 1893 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 1894 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 1895 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 1896 1897 1898 /* Description RSSI_EXT80_HIGH20_CHAIN3 1899 1900 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1901 bandwidth. 1902 Value of 0x80 indicates invalid. 1903 */ 1904 1905 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1906 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 1907 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 1908 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 1909 1910 1911 /* Description RSSI_EXT160_0_CHAIN3 1912 1913 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1914 bandwidth. 1915 Value of 0x80 indicates invalid. 1916 */ 1917 1918 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 1919 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1920 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1921 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1922 1923 1924 /* Description RSSI_EXT160_1_CHAIN3 1925 1926 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1927 bandwidth. 1928 Value of 0x80 indicates invalid. 1929 */ 1930 1931 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 1932 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1933 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1934 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1935 1936 1937 /* Description RSSI_EXT160_2_CHAIN3 1938 1939 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1940 bandwidth. 1941 Value of 0x80 indicates invalid. 1942 */ 1943 1944 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 1945 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1946 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1947 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1948 1949 1950 /* Description RSSI_EXT160_3_CHAIN3 1951 1952 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1953 bandwidth. 1954 Value of 0x80 indicates invalid. 1955 */ 1956 1957 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 1958 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1959 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1960 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1961 1962 1963 /* Description RSSI_EXT160_4_CHAIN3 1964 1965 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1966 bandwidth. 1967 Value of 0x80 indicates invalid. 1968 */ 1969 1970 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 1971 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1972 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1973 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1974 1975 1976 /* Description RSSI_EXT160_5_CHAIN3 1977 1978 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1979 bandwidth. 1980 Value of 0x80 indicates invalid. 1981 */ 1982 1983 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 1984 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1985 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1986 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1987 1988 1989 /* Description RSSI_EXT160_6_CHAIN3 1990 1991 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1992 bandwidth. 1993 Value of 0x80 indicates invalid. 1994 */ 1995 1996 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 1997 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1998 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1999 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 2000 2001 2002 /* Description RSSI_EXT160_7_CHAIN3 2003 2004 RSSI of RX PPDU on chain 3 of extension 160, highest 20 2005 MHz bandwidth. 2006 Value of 0x80 indicates invalid. 2007 */ 2008 2009 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 2010 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 2011 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 2012 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 2013 2014 2015 /* Description PRE_RSSI_COMB 2016 2017 Combined pre_rssi of all chains. Based on primary channel 2018 RSSI. 2019 2020 RSSI is reported as 8b signed values. Nominally value is 2021 in dB units above or below the noisefloor(minCCApwr). 2022 2023 The resolution can be: 2024 1dB or 0.5dB. This is statically configured within the PHY 2025 and MAC 2026 2027 In case of 1dB, the Range is: 2028 -128dB to 127dB 2029 2030 In case of 0.5dB, the Range is: 2031 -64dB to 63.5dB 2032 2033 <legal all> 2034 */ 2035 2036 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 2037 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 2038 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 2039 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff 2040 2041 2042 /* Description RSSI_COMB 2043 2044 Combined rssi of all chains. Based on primary channel RSSI. 2045 2046 2047 RSSI is reported as 8b signed values. Nominally value is 2048 in dB units above or below the noisefloor(minCCApwr). 2049 2050 The resolution can be: 2051 1dB or 0.5dB. This is statically configured within the PHY 2052 and MAC 2053 2054 In case of 1dB, the Range is: 2055 -128dB to 127dB 2056 2057 In case of 0.5dB, the Range is: 2058 -64dB to 63.5dB 2059 2060 <legal all> 2061 */ 2062 2063 #define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 2064 #define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 2065 #define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 2066 #define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 2067 2068 2069 /* Description NORMALIZED_PRE_RSSI_COMB 2070 2071 Combined pre_rssi of all chains, but "normalized" back to 2072 a single chain. This avoids PDG from having to evaluate 2073 this in combination with receive chain mask and perform 2074 all kinds of pre-processing algorithms. 2075 2076 Based on primary channel RSSI. 2077 2078 RSSI is reported as 8b signed values. Nominally value is 2079 in dB units above or below the noisefloor(minCCApwr). 2080 2081 The resolution can be: 2082 1dB or 0.5dB. This is statically configured within the PHY 2083 and MAC 2084 2085 In case of 1dB, the Range is: 2086 -128dB to 127dB 2087 2088 In case of 0.5dB, the Range is: 2089 -64dB to 63.5dB 2090 2091 <legal all> 2092 */ 2093 2094 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 2095 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 2096 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 2097 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 2098 2099 2100 /* Description NORMALIZED_RSSI_COMB 2101 2102 Combined rssi of all chains, but "normalized" back to a 2103 single chain. This avoids PDG from having to evaluate this 2104 in combination with receive chain mask and perform all 2105 kinds of pre-processing algorithms. 2106 2107 Based on primary channel RSSI. 2108 2109 RSSI is reported as 8b signed values. Nominally value is 2110 in dB units above or below the noisefloor(minCCApwr). 2111 2112 The resolution can be: 2113 1dB or 0.5dB. This is statically configured within the PHY 2114 and MAC 2115 In case of 1dB, the Range is: 2116 -128dB to 127dB 2117 2118 In case of 0.5dB, the Range is: 2119 -64dB to 63.5dB 2120 2121 <legal all> 2122 */ 2123 2124 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 2125 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 2126 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 2127 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 2128 2129 2130 /* Description RSSI_COMB_PPDU 2131 2132 Combined rssi of all chains, based on active RUs/subchannels, 2133 a.k.a. rssi_pkt_bw_mac 2134 2135 RSSI is reported as 8b signed values. Nominally value is 2136 in dB units above or below the noisefloor(minCCApwr). 2137 2138 The resolution can be: 2139 1dB or 0.5dB. This is statically configured within the PHY 2140 and MAC 2141 2142 In case of 1dB, the Range is: 2143 -128dB to 127dB 2144 2145 In case of 0.5dB, the Range is: 2146 -64dB to 63.5dB 2147 2148 When packet BW is 20 MHz, 2149 rssi_comb_ppdu = rssi_comb. 2150 2151 When packet BW > 20 MHz, 2152 rssi_comb < rssi_comb_ppdu because rssi_comb only includes 2153 power of primary 20 MHz while rssi_comb_ppdu includes power 2154 of active RUs/subchannels. 2155 2156 <legal all> 2157 */ 2158 2159 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 2160 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 2161 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 2162 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 2163 2164 2165 /* Description RSSI_DB_TO_DBM_OFFSET 2166 2167 Offset between 'dB' and 'dBm' values. SW can use this value 2168 to convert RSSI 'dBm' values back to 'dB,' and report both 2169 the values. 2170 2171 When rssi_db_to_dbm_offset = 0, 2172 all rssi_xxx fields are defined in dB. 2173 2174 When rssi_db_to_dbm_offset is a large negative value, all 2175 rssi_xxx fields are defined in dBm. 2176 2177 <legal all> 2178 */ 2179 2180 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 2181 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 2182 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 2183 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 2184 2185 2186 /* Description RSSI_FOR_SPATIAL_REUSE 2187 2188 RSSI to be used by HWSCH for transmit (power) selection 2189 during an SR opportunity, reported as an 8-bit signed value 2190 2191 2192 The resolution can be: 2193 1dB or 0.5dB. This is statically configured within the PHY 2194 and MAC 2195 2196 In case of 1dB, the Range is: 2197 -128dB to 127dB 2198 2199 In case of 0.5dB, the Range is: 2200 -64dB to 63.5dB 2201 2202 As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for 2203 OBSS PD spatial reuse, the received signal strength level 2204 should be measured from the L-STF or L-LTF (but not L-SIG), 2205 just as measured to indicate CCA. 2206 2207 Also, as per 802.11ax draft 3.3, for OBSS PD spatial reuse, 2208 MAC should compare this value with its programmed OBSS_PDlevel 2209 scaled from 20 MHz to the Rx PPDU bandwidth. Since MAC 2210 does not do this scaling, PHY is instead expected to normalize 2211 the reported RSSI to 20 MHz. 2212 2213 Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, for 2214 SRP spatial reuse, the received power level should be measured 2215 from the L-STF or L-LTF (but not L-SIG) and normalized 2216 to 20 MHz. 2217 <legal all> 2218 */ 2219 2220 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 2221 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 2222 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 2223 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 2224 2225 2226 /* Description RSSI_FOR_TRIGGER_RESP 2227 2228 RSSI to be used by PDG for transmit (power) selection during 2229 trigger response, reported as an 8-bit signed value 2230 2231 The resolution can be: 2232 1dB or 0.5dB. This is statically configured within the PHY 2233 and MAC 2234 2235 In case of 1dB, the Range is: 2236 -128dB to 127dB 2237 2238 In case of 0.5dB, the Range is: 2239 -64dB to 63.5dB 2240 2241 As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for trigger 2242 response, the received power should be measured from the 2243 non-HE portion of the preamble of the PPDU containing the 2244 trigger, normalized to 20 MHz, averaged over the antennas 2245 over which the average pathloss is being computed. 2246 <legal all> 2247 */ 2248 2249 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 2250 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 2251 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 2252 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 2253 2254 2255 2256 #endif // PHYRX_RSSI_LEGACY 2257