1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ 27*5113495bSYour Name #define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 32*5113495bSYour Name 33*5113495bSYour Name #define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct phytx_ppdu_header_info_request { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name uint16_t request_type : 5, // [4:0] 39*5113495bSYour Name reserved : 11; // [15:5] 40*5113495bSYour Name uint16_t tlv32_padding : 16; // [15:0] 41*5113495bSYour Name #else 42*5113495bSYour Name uint16_t reserved : 11, // [15:5] 43*5113495bSYour Name request_type : 5; // [4:0] 44*5113495bSYour Name uint16_t tlv32_padding : 16; // [15:0] 45*5113495bSYour Name #endif 46*5113495bSYour Name }; 47*5113495bSYour Name 48*5113495bSYour Name 49*5113495bSYour Name /* Description REQUEST_TYPE 50*5113495bSYour Name 51*5113495bSYour Name Reason for the request by PHY 52*5113495bSYour Name <enum 0 request_L_SIG_B> 53*5113495bSYour Name <enum 1 request_L_SIG_A> 54*5113495bSYour Name <enum 2 request_USER_DESC> 55*5113495bSYour Name <enum 3 request_HT_SIG> 56*5113495bSYour Name <enum 4 request_VHT_SIG_A> 57*5113495bSYour Name <enum 5 request_VHT_SIG_B > 58*5113495bSYour Name <enum 6 request_TX_SERVICE> 59*5113495bSYour Name <enum 7 request_HE_SIG_A> 60*5113495bSYour Name <enum 8 request_HE_SIG_B> 61*5113495bSYour Name <enum 9 request_U_SIG> 62*5113495bSYour Name <enum 10 request_EHT_SIG> 63*5113495bSYour Name 64*5113495bSYour Name <legal 0-10> 65*5113495bSYour Name */ 66*5113495bSYour Name 67*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 68*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 69*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 70*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f 71*5113495bSYour Name 72*5113495bSYour Name 73*5113495bSYour Name /* Description RESERVED 74*5113495bSYour Name 75*5113495bSYour Name <legal 0> 76*5113495bSYour Name */ 77*5113495bSYour Name 78*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 79*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 80*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 81*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name /* Description TLV32_PADDING 85*5113495bSYour Name 86*5113495bSYour Name Automatic WORD padding inserted while converting TLV16 to 87*5113495bSYour Name TLV32 for 64 bit ARCH 88*5113495bSYour Name <legal 0> 89*5113495bSYour Name */ 90*5113495bSYour Name 91*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 92*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 93*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 94*5113495bSYour Name #define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff 95*5113495bSYour Name 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name #endif // PHYTX_PPDU_HEADER_INFO_REQUEST 99