xref: /wlan-driver/fw-api/hw/qca5332/received_response_user_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _RECEIVED_RESPONSE_USER_INFO_H_
27 #define _RECEIVED_RESPONSE_USER_INFO_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
32 
33 
34 struct received_response_user_info {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t mpdu_fcs_pass_count                                     : 12, // [11:0]
37                       mpdu_fcs_fail_count                                     : 12, // [23:12]
38                       qosnull_frame_count                                     :  4, // [27:24]
39                       reserved_0a                                             :  3, // [30:28]
40                       user_info_valid                                         :  1; // [31:31]
41              uint32_t null_delimiter_count                                    : 22, // [21:0]
42                       reserved_1a                                             :  9, // [30:22]
43                       ht_control_valid                                        :  1; // [31:31]
44              uint32_t ht_control                                              : 32; // [31:0]
45              uint32_t qos_control_valid                                       : 16, // [15:0]
46                       eosp                                                    : 16; // [31:16]
47              uint32_t qos_control_15_8_tid_0                                  :  8, // [7:0]
48                       qos_control_15_8_tid_1                                  :  8, // [15:8]
49                       qos_control_15_8_tid_2                                  :  8, // [23:16]
50                       qos_control_15_8_tid_3                                  :  8; // [31:24]
51              uint32_t qos_control_15_8_tid_4                                  :  8, // [7:0]
52                       qos_control_15_8_tid_5                                  :  8, // [15:8]
53                       qos_control_15_8_tid_6                                  :  8, // [23:16]
54                       qos_control_15_8_tid_7                                  :  8; // [31:24]
55              uint32_t qos_control_15_8_tid_8                                  :  8, // [7:0]
56                       qos_control_15_8_tid_9                                  :  8, // [15:8]
57                       qos_control_15_8_tid_10                                 :  8, // [23:16]
58                       qos_control_15_8_tid_11                                 :  8; // [31:24]
59              uint32_t qos_control_15_8_tid_12                                 :  8, // [7:0]
60                       qos_control_15_8_tid_13                                 :  8, // [15:8]
61                       qos_control_15_8_tid_14                                 :  8, // [23:16]
62                       qos_control_15_8_tid_15                                 :  8; // [31:24]
63 #else
64              uint32_t user_info_valid                                         :  1, // [31:31]
65                       reserved_0a                                             :  3, // [30:28]
66                       qosnull_frame_count                                     :  4, // [27:24]
67                       mpdu_fcs_fail_count                                     : 12, // [23:12]
68                       mpdu_fcs_pass_count                                     : 12; // [11:0]
69              uint32_t ht_control_valid                                        :  1, // [31:31]
70                       reserved_1a                                             :  9, // [30:22]
71                       null_delimiter_count                                    : 22; // [21:0]
72              uint32_t ht_control                                              : 32; // [31:0]
73              uint32_t eosp                                                    : 16, // [31:16]
74                       qos_control_valid                                       : 16; // [15:0]
75              uint32_t qos_control_15_8_tid_3                                  :  8, // [31:24]
76                       qos_control_15_8_tid_2                                  :  8, // [23:16]
77                       qos_control_15_8_tid_1                                  :  8, // [15:8]
78                       qos_control_15_8_tid_0                                  :  8; // [7:0]
79              uint32_t qos_control_15_8_tid_7                                  :  8, // [31:24]
80                       qos_control_15_8_tid_6                                  :  8, // [23:16]
81                       qos_control_15_8_tid_5                                  :  8, // [15:8]
82                       qos_control_15_8_tid_4                                  :  8; // [7:0]
83              uint32_t qos_control_15_8_tid_11                                 :  8, // [31:24]
84                       qos_control_15_8_tid_10                                 :  8, // [23:16]
85                       qos_control_15_8_tid_9                                  :  8, // [15:8]
86                       qos_control_15_8_tid_8                                  :  8; // [7:0]
87              uint32_t qos_control_15_8_tid_15                                 :  8, // [31:24]
88                       qos_control_15_8_tid_14                                 :  8, // [23:16]
89                       qos_control_15_8_tid_13                                 :  8, // [15:8]
90                       qos_control_15_8_tid_12                                 :  8; // [7:0]
91 #endif
92 };
93 
94 
95 /* Description		MPDU_FCS_PASS_COUNT
96 
97 			The number of MPDUs received with correct FCS.
98 			Hamilton v1 used bits [15:8] to report 'mpdu_fcs_fail_count.'
99 
100 			<legal all>
101 */
102 
103 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
104 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
105 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
106 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
107 
108 
109 /* Description		MPDU_FCS_FAIL_COUNT
110 
111 			The number of MPDUs received with wrong FCS.
112 			Hamilton v1 used bits [15:8] for this and bits [23:16] to
113 			 report the number of data frames with correct FCS.
114 			<legal all>
115 */
116 
117 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
118 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
119 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
120 #define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
121 
122 
123 /* Description		QOSNULL_FRAME_COUNT
124 
125 			The number of QoSNULL frames received with correct FCS.
126 			<legal all>
127 */
128 
129 #define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
130 #define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
131 #define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
132 #define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
133 
134 
135 /* Description		RESERVED_0A
136 
137 			<legal 0>
138 */
139 
140 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
141 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
142 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
143 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
144 
145 
146 /* Description		USER_INFO_VALID
147 
148 			When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains
149 			 valid information.
150 			<legal all>
151 */
152 
153 #define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
154 #define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
155 #define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
156 #define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
157 
158 
159 /* Description		NULL_DELIMITER_COUNT
160 
161 			The number of valid, properly formed NULL delimiters received
162 
163 			<legal all>
164 */
165 
166 #define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
167 #define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
168 #define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
169 #define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
170 
171 
172 /* Description		RESERVED_1A
173 
174 			<legal 0>
175 */
176 
177 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
178 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
179 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
180 #define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
181 
182 
183 /* Description		HT_CONTROL_VALID
184 
185 			When set, indicates that the received MPDUs included an
186 			HT Control field
187 			<legal all>
188 */
189 
190 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
191 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
192 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
193 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
194 
195 
196 /* Description		HT_CONTROL
197 
198 			Field only valid if HT_Control_valid is set
199 			Received HT Control value
200 
201 			Hamilton v1 did not include this (and any subsequent) word.
202 
203 			<legal all>
204 */
205 
206 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
207 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
208 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
209 #define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
210 
211 
212 /* Description		QOS_CONTROL_VALID
213 
214 			Each bit when set, indicates that the received MPDUs included
215 			 that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*'
216 			field are valid.
217 			Bit 0: TID 0
218 			...
219 			Bit 15: TID 15
220 			<legal all>
221 */
222 
223 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
224 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
225 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
226 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
227 
228 
229 /* Description		EOSP
230 
231 			Each bit only valid if the corresponding bit of QoS_Control_valid
232 			 is set.
233 
234 			Received EOSP bit for each TID
235 			Bit 0: TID 0
236 			...
237 			Bit 15: TID 15
238 			<legal all>
239 */
240 
241 #define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
242 #define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
243 #define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
244 #define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
245 
246 
247 /* Description		QOS_CONTROL_15_8_TID_0
248 
249 			Field only valid if QoS_Control_valid[0] is set.
250 
251 			Received bits [15:8] of QoS Control for TID 0
252 			<legal all>
253 */
254 
255 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
256 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
257 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
258 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
259 
260 
261 /* Description		QOS_CONTROL_15_8_TID_1
262 
263 			Field only valid if QoS_Control_valid[1] is set.
264 
265 			Received bits [15:8] of QoS Control for TID 1
266 			<legal all>
267 */
268 
269 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
270 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
271 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
272 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
273 
274 
275 /* Description		QOS_CONTROL_15_8_TID_2
276 
277 			Field only valid if QoS_Control_valid[2] is set.
278 
279 			Received bits [15:8] of QoS Control for TID 2
280 			<legal all>
281 */
282 
283 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
284 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
285 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
286 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
287 
288 
289 /* Description		QOS_CONTROL_15_8_TID_3
290 
291 			Field only valid if QoS_Control_valid[3] is set.
292 
293 			Received bits [15:8] of QoS Control for TID 3
294 			<legal all>
295 */
296 
297 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
298 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
299 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
300 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
301 
302 
303 /* Description		QOS_CONTROL_15_8_TID_4
304 
305 			Field only valid if QoS_Control_valid[4] is set.
306 
307 			Received bits [15:8] of QoS Control for TID 4
308 			<legal all>
309 */
310 
311 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
312 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
313 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
314 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
315 
316 
317 /* Description		QOS_CONTROL_15_8_TID_5
318 
319 			Field only valid if QoS_Control_valid[5] is set.
320 
321 			Received bits [15:8] of QoS Control for TID 5
322 			<legal all>
323 */
324 
325 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
326 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
327 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
328 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
329 
330 
331 /* Description		QOS_CONTROL_15_8_TID_6
332 
333 			Field only valid if QoS_Control_valid[6] is set.
334 
335 			Received bits [15:8] of QoS Control for TID 6
336 			<legal all>
337 */
338 
339 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
340 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
341 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
342 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
343 
344 
345 /* Description		QOS_CONTROL_15_8_TID_7
346 
347 			Field only valid if QoS_Control_valid[7] is set.
348 
349 			Received bits [15:8] of QoS Control for TID 7
350 			<legal all>
351 */
352 
353 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
354 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
355 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
356 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
357 
358 
359 /* Description		QOS_CONTROL_15_8_TID_8
360 
361 			Field only valid if QoS_Control_valid[8] is set.
362 
363 			Received bits [15:8] of QoS Control for TID 8
364 			<legal all>
365 */
366 
367 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
368 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
369 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
370 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
371 
372 
373 /* Description		QOS_CONTROL_15_8_TID_9
374 
375 			Field only valid if QoS_Control_valid[9] is set.
376 
377 			Received bits [15:8] of QoS Control for TID 9
378 			<legal all>
379 */
380 
381 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
382 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
383 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
384 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
385 
386 
387 /* Description		QOS_CONTROL_15_8_TID_10
388 
389 			Field only valid if QoS_Control_valid[10] is set.
390 
391 			Received bits [15:8] of QoS Control for TID 10
392 			<legal all>
393 */
394 
395 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
396 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
397 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
398 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
399 
400 
401 /* Description		QOS_CONTROL_15_8_TID_11
402 
403 			Field only valid if QoS_Control_valid[11] is set.
404 
405 			Received bits [15:8] of QoS Control for TID 11
406 			<legal all>
407 */
408 
409 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
410 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
411 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
412 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
413 
414 
415 /* Description		QOS_CONTROL_15_8_TID_12
416 
417 			Field only valid if QoS_Control_valid[12] is set.
418 
419 			Received bits [15:8] of QoS Control for TID 12
420 			<legal all>
421 */
422 
423 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
424 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
425 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
426 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
427 
428 
429 /* Description		QOS_CONTROL_15_8_TID_13
430 
431 			Field only valid if QoS_Control_valid[13] is set.
432 
433 			Received bits [15:8] of QoS Control for TID 13
434 			<legal all>
435 */
436 
437 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
438 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
439 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
440 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
441 
442 
443 /* Description		QOS_CONTROL_15_8_TID_14
444 
445 			Field only valid if QoS_Control_valid[14] is set.
446 
447 			Received bits [15:8] of QoS Control for TID 14
448 			<legal all>
449 */
450 
451 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
452 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
453 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
454 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
455 
456 
457 /* Description		QOS_CONTROL_15_8_TID_15
458 
459 			Field only valid if QoS_Control_valid[15] is set.
460 
461 			Received bits [15:8] of QoS Control for TID 15
462 			<legal all>
463 */
464 
465 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
466 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
467 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
468 #define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
469 
470 
471 
472 #endif   // RECEIVED_RESPONSE_USER_INFO
473