1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_DESTINATION_RING_H_ 27 #define _REO_DESTINATION_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_msdu_desc_info.h" 32 #include "rx_mpdu_desc_info.h" 33 #include "buffer_addr_info.h" 34 #define NUM_OF_DWORDS_REO_DESTINATION_RING 8 35 36 37 struct reo_destination_ring { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct buffer_addr_info buf_or_link_desc_addr_info; 40 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 41 struct rx_msdu_desc_info rx_msdu_desc_info_details; 42 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 43 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 44 uint32_t reo_dest_buffer_type : 1, // [0:0] 45 reo_push_reason : 2, // [2:1] 46 reo_error_code : 5, // [7:3] 47 captured_msdu_data_size : 4, // [11:8] 48 sw_exception : 1, // [12:12] 49 src_link_id : 3, // [15:13] 50 reo_destination_struct_signature : 4, // [19:16] 51 ring_id : 8, // [27:20] 52 looping_count : 4; // [31:28] 53 #else 54 struct buffer_addr_info buf_or_link_desc_addr_info; 55 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 56 struct rx_msdu_desc_info rx_msdu_desc_info_details; 57 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 58 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 59 uint32_t looping_count : 4, // [31:28] 60 ring_id : 8, // [27:20] 61 reo_destination_struct_signature : 4, // [19:16] 62 src_link_id : 3, // [15:13] 63 sw_exception : 1, // [12:12] 64 captured_msdu_data_size : 4, // [11:8] 65 reo_error_code : 5, // [7:3] 66 reo_push_reason : 2, // [2:1] 67 reo_dest_buffer_type : 1; // [0:0] 68 #endif 69 }; 70 71 72 /* Description BUF_OR_LINK_DESC_ADDR_INFO 73 74 Consumer: REO/SW/FW 75 Producer: RXDMA 76 77 Details of the physical address of the a buffer or MSDU 78 link descriptor 79 */ 80 81 82 /* Description BUFFER_ADDR_31_0 83 84 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 85 descriptor OR Link Descriptor 86 87 In case of 'NULL' pointer, this field is set to 0 88 <legal all> 89 */ 90 91 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 92 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 93 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 94 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 95 96 97 /* Description BUFFER_ADDR_39_32 98 99 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 100 descriptor OR Link Descriptor 101 102 In case of 'NULL' pointer, this field is set to 0 103 <legal all> 104 */ 105 106 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 107 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 108 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 109 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 110 111 112 /* Description RETURN_BUFFER_MANAGER 113 114 Consumer: WBM 115 Producer: SW/FW 116 117 In case of 'NULL' pointer, this field is set to 0 118 119 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 120 descriptor OR link descriptor that is being pointed to 121 shall be returned after the frame has been processed. It 122 is used by WBM for routing purposes. 123 124 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 125 to the WMB buffer idle list 126 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 127 to the WBM idle link descriptor idle list, where the chip 128 0 WBM is chosen in case of a multi-chip config 129 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 130 to the chip 1 WBM idle link descriptor idle list 131 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 132 to the chip 2 WBM idle link descriptor idle list 133 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 134 returned to chip 3 WBM idle link descriptor idle list 135 <enum 4 FW_BM> This buffer shall be returned to the FW 136 <enum 5 SW0_BM> This buffer shall be returned to the SW, 137 ring 0 138 <enum 6 SW1_BM> This buffer shall be returned to the SW, 139 ring 1 140 <enum 7 SW2_BM> This buffer shall be returned to the SW, 141 ring 2 142 <enum 8 SW3_BM> This buffer shall be returned to the SW, 143 ring 3 144 <enum 9 SW4_BM> This buffer shall be returned to the SW, 145 ring 4 146 <enum 10 SW5_BM> This buffer shall be returned to the SW, 147 ring 5 148 <enum 11 SW6_BM> This buffer shall be returned to the SW, 149 ring 6 150 151 <legal 0-12> 152 */ 153 154 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 155 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 156 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 157 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 158 159 160 /* Description SW_BUFFER_COOKIE 161 162 Cookie field exclusively used by SW. 163 164 In case of 'NULL' pointer, this field is set to 0 165 166 HW ignores the contents, accept that it passes the programmed 167 value on to other descriptors together with the physical 168 address 169 170 Field can be used by SW to for example associate the buffers 171 physical address with the virtual address 172 The bit definitions as used by SW are within SW HLD specification 173 174 175 NOTE1: 176 The three most significant bits can have a special meaning 177 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 178 and field transmit_bw_restriction is set 179 180 In case of NON punctured transmission: 181 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 182 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 183 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 184 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 185 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 186 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 187 Sw_buffer_cookie[19:18] = 2'b11: reserved 188 189 In case of punctured transmission: 190 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 191 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 192 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 193 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 194 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 195 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 196 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 197 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 198 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 199 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 200 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 201 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 202 Sw_buffer_cookie[19:18] = 2'b11: reserved 203 204 Note: a punctured transmission is indicated by the presence 205 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 206 207 <legal all> 208 */ 209 210 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 211 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 212 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 213 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 214 215 216 /* Description RX_MPDU_DESC_INFO_DETAILS 217 218 Consumer: REO/SW/FW 219 Producer: RXDMA 220 221 General information related to the MPDU that is passed on 222 from REO entrance ring to the REO destination ring 223 224 When enabled in REO, REO will overwrite this structure to 225 have only the 'Msdu_count' field and 56 bits of the previous 226 PN from 'RX_REO_QUEUE' (Hamilton FR62456) 227 */ 228 229 230 /* Description MSDU_COUNT 231 232 Consumer: REO/SW/FW 233 Producer: RXDMA 234 235 The number of MSDUs within the MPDU 236 <legal all> 237 */ 238 239 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 240 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 241 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 242 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 243 244 245 /* Description FRAGMENT_FLAG 246 247 Consumer: REO/SW/FW 248 Producer: RXDMA 249 250 When set, this MPDU is a fragment and REO should forward 251 this fragment MPDU to the REO destination ring without 252 any reorder checks, pn checks or bitmap update. This implies 253 that REO is forwarding the pointer to the MSDU link descriptor. 254 The destination ring is coming from a programmable register 255 setting in REO 256 257 <legal all> 258 */ 259 260 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 261 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 262 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 263 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 264 265 266 /* Description MPDU_RETRY_BIT 267 268 Consumer: REO/SW/FW 269 Producer: RXDMA 270 271 The retry bit setting from the MPDU header of the received 272 frame 273 <legal all> 274 */ 275 276 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 277 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 278 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 279 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 280 281 282 /* Description AMPDU_FLAG 283 284 Consumer: REO/SW/FW 285 Producer: RXDMA 286 287 When set, the MPDU was received as part of an A-MPDU. 288 <legal all> 289 */ 290 291 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 292 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 293 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 294 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 295 296 297 /* Description BAR_FRAME 298 299 Consumer: REO/SW/FW 300 Producer: RXDMA 301 302 When set, the received frame is a BAR frame. After processing, 303 this frame shall be pushed to SW or deleted. 304 <legal all> 305 */ 306 307 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 308 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 309 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 310 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 311 312 313 /* Description PN_FIELDS_CONTAIN_VALID_INFO 314 315 Consumer: REO/SW/FW 316 Producer: RXDMA 317 318 Copied here by RXDMA from RX_MPDU_END 319 When not set, REO will Not perform a PN sequence number 320 check 321 */ 322 323 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 324 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 325 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 326 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 327 328 329 /* Description RAW_MPDU 330 331 Field only valid when first_msdu_in_mpdu_flag is set. 332 333 When set, the contents in the MSDU buffer contains a 'RAW' 334 MPDU. This 'RAW' MPDU might be spread out over multiple 335 MSDU buffers. 336 <legal all> 337 */ 338 339 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 340 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 341 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 342 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 343 344 345 /* Description MORE_FRAGMENT_FLAG 346 347 The More Fragment bit setting from the MPDU header of the 348 received frame 349 350 <legal all> 351 */ 352 353 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 354 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 355 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 356 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 357 358 359 /* Description SRC_INFO 360 361 Source (virtual) device/interface info. associated with 362 this peer 363 364 This field gets passed on by REO to PPE in the EDMA descriptor 365 ('REO_TO_PPE_RING'). 366 367 Hamilton v1 used this for 'vdev_id' instead. 368 <legal all> 369 */ 370 371 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 372 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 373 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 374 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 375 376 377 /* Description MPDU_QOS_CONTROL_VALID 378 379 When set, the MPDU has a QoS control field. 380 381 In case of ndp or phy_err, this field will never be set. 382 383 <legal all> 384 */ 385 386 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 387 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 388 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 389 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 390 391 392 /* Description TID 393 394 Field only valid when mpdu_qos_control_valid is set 395 396 The TID field in the QoS control field 397 <legal all> 398 */ 399 400 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 401 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 402 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 403 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 404 405 406 /* Description PEER_META_DATA 407 408 Meta data that SW has programmed in the Peer table entry 409 of the transmitting STA. 410 <legal all> 411 */ 412 413 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 414 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 415 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 416 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 417 418 419 /* Description RX_MSDU_DESC_INFO_DETAILS 420 421 General information related to the MSDU that is passed on 422 from RXDMA all the way to to the REO destination ring. 423 */ 424 425 426 /* Description FIRST_MSDU_IN_MPDU_FLAG 427 428 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 429 multiple buffers, this field will be valid in the Last 430 buffer used by the MSDU 431 432 <enum 0 Not_first_msdu> This is not the first MSDU in the 433 MPDU. 434 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 435 436 437 <legal all> 438 */ 439 440 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 441 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 442 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 443 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 444 445 446 /* Description LAST_MSDU_IN_MPDU_FLAG 447 448 Consumer: WBM/REO/SW/FW 449 Producer: RXDMA 450 451 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 452 multiple buffers, this field will be valid in the Last 453 buffer used by the MSDU 454 455 <enum 0 Not_last_msdu> There are more MSDUs linked to this 456 MSDU that belongs to this MPDU 457 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 458 This setting is only allowed in combination with 'Msdu_continuation' 459 set to 0. This implies that when an msdu is spread out over 460 multiple buffers and thus msdu_continuation is set, only 461 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 462 be set. 463 464 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 465 are set, the MPDU that this MSDU belongs to only contains 466 a single MSDU. 467 468 469 <legal all> 470 */ 471 472 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 473 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 474 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 475 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 476 477 478 /* Description MSDU_CONTINUATION 479 480 When set, this MSDU buffer was not able to hold the entire 481 MSDU. The next buffer will therefor contain additional 482 information related to this MSDU. 483 484 <legal all> 485 */ 486 487 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 488 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 489 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 490 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 491 492 493 /* Description MSDU_LENGTH 494 495 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 496 multiple buffers, this field will be valid in the First 497 buffer used by MSDU. 498 499 Full MSDU length in bytes after decapsulation. 500 501 This field is still valid for MPDU frames without A-MSDU. 502 It still represents MSDU length after decapsulation 503 504 Or in case of RAW MPDUs, it indicates the length of the 505 entire MPDU (without FCS field) 506 <legal all> 507 */ 508 509 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 510 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 511 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 512 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 513 514 515 /* Description MSDU_DROP 516 517 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 518 multiple buffers, this field will be valid in the Last 519 buffer used by the MSDU 520 521 When set, REO shall drop this MSDU and not forward it to 522 any other ring... 523 <legal all> 524 */ 525 526 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 527 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 528 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 529 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 530 531 532 /* Description SA_IS_VALID 533 534 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 535 multiple buffers, this field will be valid in the Last 536 buffer used by the MSDU 537 538 Indicates that OLE found a valid SA entry for this MSDU 539 <legal all> 540 */ 541 542 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 543 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 544 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 545 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 546 547 548 /* Description DA_IS_VALID 549 550 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 551 multiple buffers, this field will be valid in the Last 552 buffer used by the MSDU 553 554 Indicates that OLE found a valid DA entry for this MSDU 555 <legal all> 556 */ 557 558 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 559 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 560 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 561 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 562 563 564 /* Description DA_IS_MCBC 565 566 Field Only valid if "da_is_valid" is set 567 568 Indicates the DA address was a Multicast of Broadcast address 569 for this MSDU 570 <legal all> 571 */ 572 573 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 574 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 575 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 576 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 577 578 579 /* Description L3_HEADER_PADDING_MSB 580 581 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 582 as the LSB is always zero) 583 Number of bytes padded to make sure that the L3 header will 584 always start of a Dword boundary 585 <legal all> 586 */ 587 588 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 589 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 590 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 591 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 592 593 594 /* Description TCP_UDP_CHKSUM_FAIL 595 596 Passed on from 'RX_ATTENTION' TLV 597 Indicates that the computed checksum did not match the checksum 598 in the TCP/UDP header. 599 <legal all> 600 */ 601 602 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 603 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 604 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 605 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 606 607 608 /* Description IP_CHKSUM_FAIL 609 610 Passed on from 'RX_ATTENTION' TLV 611 Indicates that the computed checksum did not match the checksum 612 in the IP header. 613 <legal all> 614 */ 615 616 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 617 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 618 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 619 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 620 621 622 /* Description FR_DS 623 624 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 625 TLV 626 Set if the 'from DS' bit is set in the frame control. 627 <legal all> 628 */ 629 630 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 631 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 632 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 633 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 634 635 636 /* Description TO_DS 637 638 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 639 TLV 640 Set if the 'to DS' bit is set in the frame control. 641 <legal all> 642 */ 643 644 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 645 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 646 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 647 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 648 649 650 /* Description INTRA_BSS 651 652 This packet needs intra-BSS routing by SW as the 'vdev_id' 653 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 654 that this MSDU was got in. 655 656 <legal all> 657 */ 658 659 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 660 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 661 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 662 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 663 664 665 /* Description DEST_CHIP_ID 666 667 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 668 to support intra-BSS routing with multi-chip multi-link 669 operation. 670 671 This indicates into which chip's TCL the packet should be 672 queued. 673 674 <legal all> 675 */ 676 677 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 678 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 679 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 680 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 681 682 683 /* Description DECAP_FORMAT 684 685 Indicates the format after decapsulation: 686 687 <enum 0 RAW> No encapsulation 688 <enum 1 Native_WiFi> 689 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 690 691 <enum 3 802_3> Indicate Ethernet 692 693 <legal all> 694 */ 695 696 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 697 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 698 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 699 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 700 701 702 /* Description DEST_CHIP_PMAC_ID 703 704 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 705 to support intra-BSS routing with multi-chip multi-link 706 operation. 707 708 This indicates into which link/'vdev' the packet should 709 be queued in TCL. 710 711 <legal all> 712 */ 713 714 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000010 715 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 716 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 717 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 718 719 720 /* Description BUFFER_VIRT_ADDR_31_0 721 722 Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 723 724 725 Lower 32 bits of the 64-bit virtual address corresponding 726 to Buf_or_link_desc_addr_info 727 <legal all> 728 */ 729 730 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 731 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 732 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 733 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 734 735 736 /* Description BUFFER_VIRT_ADDR_63_32 737 738 Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 739 740 741 Upper 32 bits of the 64-bit virtual address corresponding 742 to Buf_or_link_desc_addr_info 743 <legal all> 744 */ 745 746 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 747 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 748 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 749 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 750 751 752 /* Description REO_DEST_BUFFER_TYPE 753 754 Indicates the type of address provided in the 'Buf_or_link_desc_addr_info' 755 756 757 <enum 0 MSDU_buf_address> The address of an MSDU buffer 758 <enum 1 MSDU_link_desc_address> The address of the MSDU 759 link descriptor. 760 761 <legal all> 762 */ 763 764 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 765 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 766 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 767 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 768 769 770 /* Description REO_PUSH_REASON 771 772 Indicates why REO pushed the frame to this exit ring 773 774 <enum 0 reo_error_detected> Reo detected an error an pushed 775 this frame to this queue 776 <enum 1 reo_routing_instruction> Reo pushed the frame to 777 this queue per received routing instructions. No error 778 within REO was detected 779 780 781 <legal 0 - 1> 782 */ 783 784 #define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c 785 #define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 786 #define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 787 #define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 788 789 790 /* Description REO_ERROR_CODE 791 792 Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 793 794 795 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 796 in the REO_ENTRANCE ring is set to 0 797 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 798 bit is NOT set 799 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 800 session having been setup. 801 <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 802 Retry bit set: duplicate frame 803 <enum 4 ba_duplicate> BA session, duplicate frame 804 <enum 5 regular_frame_2k_jump> A normal (management/data 805 frame) received with 2K jump in SN 806 <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 807 SSN 808 <enum 7 regular_frame_OOR> A normal (management/data frame) 809 received with SN falling within the OOR window 810 <enum 8 bar_frame_OOR> A bar received with SSN falling within 811 the OOR window 812 <enum 9 bar_frame_no_ba_session> A bar received without 813 a BA session 814 <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 815 equal to SN 816 <enum 11 pn_check_failed> PN Check Failed packet. 817 <enum 12 2k_error_handling_flag_set> Frame is forwarded 818 as a result of the 'Seq_2k_error_detected_flag' been set 819 in the REO Queue descriptor 820 <enum 13 pn_error_handling_flag_set> Frame is forwarded 821 as a result of the 'pn_error_detected_flag' been set in 822 the REO Queue descriptor 823 <enum 14 queue_descriptor_blocked_set> Frame is forwarded 824 as a result of the queue descriptor(address) being blocked 825 as SW/FW seems to be currently in the process of making 826 updates to this descriptor... 827 828 <legal 0-14> 829 */ 830 831 #define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c 832 #define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 833 #define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 834 #define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 835 836 837 /* Description CAPTURED_MSDU_DATA_SIZE 838 839 The number of following REO_DESTINATION STRUCTs that have 840 been replaced with msdu_data extracted from the msdu_buffer 841 and copied into the ring for easy FW/SW access. 842 Note that it is possible that these STRUCTs wrap around 843 the end of the ring. 844 Feature supported only in HastingsPrime 845 <legal 0-4> 846 */ 847 848 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c 849 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 850 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 851 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 852 853 854 /* Description SW_EXCEPTION 855 856 This field has the same setting as the SW_exception field 857 in the corresponding REO_entrance_ring descriptor. 858 When set, the REO entrance descriptor is generated by FW, 859 and the MPDU was processed in the following way: 860 - NO re-order function is needed. 861 - MPDU delinking is determined by the setting of Entrance 862 ring field: SW_excection_mpdu_delink 863 - Destination ring selection is based on the setting of 864 the Entrance ring field SW_exception_destination _ring_valid 865 866 Feature supported only in HastingsPrime 867 <legal all> 868 */ 869 870 #define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c 871 #define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 872 #define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 873 #define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 874 875 876 /* Description SRC_LINK_ID 877 878 Consumer: SW 879 Producer: RXDMA 880 881 Set to the link ID of the PMAC that received the frame 882 <legal all> 883 */ 884 885 #define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c 886 #define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 887 #define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 888 #define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 889 890 891 /* Description REO_DESTINATION_STRUCT_SIGNATURE 892 893 Set to value 0x8 when msdu capture mode is enabled for this 894 ring <legal 0, 8 > 895 */ 896 897 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c 898 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 899 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 900 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 901 902 903 /* Description RING_ID 904 905 The buffer pointer ring ID. 906 0 refers to the IDLE ring 907 1 - N refers to other rings 908 909 Helps with debugging when dumping ring contents. 910 911 This can be used in conjunction with the Reo_destination_struct_signature. 912 913 <legal all> 914 */ 915 916 #define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c 917 #define REO_DESTINATION_RING_RING_ID_LSB 20 918 #define REO_DESTINATION_RING_RING_ID_MSB 27 919 #define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 920 921 922 /* Description LOOPING_COUNT 923 924 A count value that indicates the number of times the producer 925 of entries into this Ring has looped around the ring. 926 At initialization time, this value is set to 0. On the first 927 loop, this value is set to 1. After the max value is reached 928 allowed by the number of bits for this field, the count 929 value continues with 0 again. 930 In case SW is the consumer of the ring entries, it can use 931 this field to figure out up to where the producer of entries 932 has created new entries. This eliminates the need to check 933 where the "head pointer' of the ring is located once the 934 SW starts processing an interrupt indicating that new entries 935 have been put into this ring... 936 937 Also note that SW if it wants only needs to look at the 938 LSB bit of this count value. 939 <legal all> 940 */ 941 942 #define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c 943 #define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 944 #define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 945 #define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 946 947 948 949 #endif // REO_DESTINATION_RING 950