1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_ENTRANCE_RING_H_ 27 #define _REO_ENTRANCE_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_mpdu_details.h" 32 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 33 34 35 struct reo_entrance_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct rx_mpdu_details reo_level_mpdu_frame_info; 38 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 39 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 40 rounded_mpdu_byte_count : 14, // [21:8] 41 reo_destination_indication : 5, // [26:22] 42 frameless_bar : 1, // [27:27] 43 reserved_5a : 4; // [31:28] 44 uint32_t rxdma_push_reason : 2, // [1:0] 45 rxdma_error_code : 5, // [6:2] 46 mpdu_fragment_number : 4, // [10:7] 47 sw_exception : 1, // [11:11] 48 sw_exception_mpdu_delink : 1, // [12:12] 49 sw_exception_destination_ring_valid : 1, // [13:13] 50 sw_exception_destination_ring : 5, // [18:14] 51 mpdu_sequence_number : 12, // [30:19] 52 reserved_6a : 1; // [31:31] 53 uint32_t phy_ppdu_id : 16, // [15:0] 54 src_link_id : 3, // [18:16] 55 reserved_7a : 1, // [19:19] 56 ring_id : 8, // [27:20] 57 looping_count : 4; // [31:28] 58 #else 59 struct rx_mpdu_details reo_level_mpdu_frame_info; 60 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 61 uint32_t reserved_5a : 4, // [31:28] 62 frameless_bar : 1, // [27:27] 63 reo_destination_indication : 5, // [26:22] 64 rounded_mpdu_byte_count : 14, // [21:8] 65 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 66 uint32_t reserved_6a : 1, // [31:31] 67 mpdu_sequence_number : 12, // [30:19] 68 sw_exception_destination_ring : 5, // [18:14] 69 sw_exception_destination_ring_valid : 1, // [13:13] 70 sw_exception_mpdu_delink : 1, // [12:12] 71 sw_exception : 1, // [11:11] 72 mpdu_fragment_number : 4, // [10:7] 73 rxdma_error_code : 5, // [6:2] 74 rxdma_push_reason : 2; // [1:0] 75 uint32_t looping_count : 4, // [31:28] 76 ring_id : 8, // [27:20] 77 reserved_7a : 1, // [19:19] 78 src_link_id : 3, // [18:16] 79 phy_ppdu_id : 16; // [15:0] 80 #endif 81 }; 82 83 84 /* Description REO_LEVEL_MPDU_FRAME_INFO 85 86 Consumer: REO 87 Producer: RXDMA 88 89 Details related to the MPDU being pushed into the REO 90 */ 91 92 93 /* Description MSDU_LINK_DESC_ADDR_INFO 94 95 Consumer: REO/SW/FW 96 Producer: RXDMA 97 98 Details of the physical address of the MSDU link descriptor 99 that contains pointers to MSDUs related to this MPDU 100 */ 101 102 103 /* Description BUFFER_ADDR_31_0 104 105 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 106 descriptor OR Link Descriptor 107 108 In case of 'NULL' pointer, this field is set to 0 109 <legal all> 110 */ 111 112 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 113 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 114 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 115 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 116 117 118 /* Description BUFFER_ADDR_39_32 119 120 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 121 descriptor OR Link Descriptor 122 123 In case of 'NULL' pointer, this field is set to 0 124 <legal all> 125 */ 126 127 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 128 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 129 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 130 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 131 132 133 /* Description RETURN_BUFFER_MANAGER 134 135 Consumer: WBM 136 Producer: SW/FW 137 138 In case of 'NULL' pointer, this field is set to 0 139 140 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 141 descriptor OR link descriptor that is being pointed to 142 shall be returned after the frame has been processed. It 143 is used by WBM for routing purposes. 144 145 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 146 to the WMB buffer idle list 147 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 148 to the WBM idle link descriptor idle list, where the chip 149 0 WBM is chosen in case of a multi-chip config 150 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 151 to the chip 1 WBM idle link descriptor idle list 152 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 153 to the chip 2 WBM idle link descriptor idle list 154 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 155 returned to chip 3 WBM idle link descriptor idle list 156 <enum 4 FW_BM> This buffer shall be returned to the FW 157 <enum 5 SW0_BM> This buffer shall be returned to the SW, 158 ring 0 159 <enum 6 SW1_BM> This buffer shall be returned to the SW, 160 ring 1 161 <enum 7 SW2_BM> This buffer shall be returned to the SW, 162 ring 2 163 <enum 8 SW3_BM> This buffer shall be returned to the SW, 164 ring 3 165 <enum 9 SW4_BM> This buffer shall be returned to the SW, 166 ring 4 167 <enum 10 SW5_BM> This buffer shall be returned to the SW, 168 ring 5 169 <enum 11 SW6_BM> This buffer shall be returned to the SW, 170 ring 6 171 172 <legal 0-12> 173 */ 174 175 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 176 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 177 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 178 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 179 180 181 /* Description SW_BUFFER_COOKIE 182 183 Cookie field exclusively used by SW. 184 185 In case of 'NULL' pointer, this field is set to 0 186 187 HW ignores the contents, accept that it passes the programmed 188 value on to other descriptors together with the physical 189 address 190 191 Field can be used by SW to for example associate the buffers 192 physical address with the virtual address 193 The bit definitions as used by SW are within SW HLD specification 194 195 196 NOTE1: 197 The three most significant bits can have a special meaning 198 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 199 and field transmit_bw_restriction is set 200 201 In case of NON punctured transmission: 202 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 203 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 204 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 205 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 206 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 207 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 208 Sw_buffer_cookie[19:18] = 2'b11: reserved 209 210 In case of punctured transmission: 211 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 212 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 213 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 214 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 215 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 216 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 217 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 218 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 219 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 220 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 221 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 222 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 223 Sw_buffer_cookie[19:18] = 2'b11: reserved 224 225 Note: a punctured transmission is indicated by the presence 226 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 227 228 <legal all> 229 */ 230 231 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 232 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 233 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 234 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 235 236 237 /* Description RX_MPDU_DESC_INFO_DETAILS 238 239 Consumer: REO/SW/FW 240 Producer: RXDMA 241 242 General information related to the MPDU that should be passed 243 on from REO entrance ring to the REO destination ring 244 */ 245 246 247 /* Description MSDU_COUNT 248 249 Consumer: REO/SW/FW 250 Producer: RXDMA 251 252 The number of MSDUs within the MPDU 253 <legal all> 254 */ 255 256 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 257 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 258 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 259 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 260 261 262 /* Description FRAGMENT_FLAG 263 264 Consumer: REO/SW/FW 265 Producer: RXDMA 266 267 When set, this MPDU is a fragment and REO should forward 268 this fragment MPDU to the REO destination ring without 269 any reorder checks, pn checks or bitmap update. This implies 270 that REO is forwarding the pointer to the MSDU link descriptor. 271 The destination ring is coming from a programmable register 272 setting in REO 273 274 <legal all> 275 */ 276 277 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 278 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 279 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 280 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 281 282 283 /* Description MPDU_RETRY_BIT 284 285 Consumer: REO/SW/FW 286 Producer: RXDMA 287 288 The retry bit setting from the MPDU header of the received 289 frame 290 <legal all> 291 */ 292 293 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 294 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 295 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 296 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 297 298 299 /* Description AMPDU_FLAG 300 301 Consumer: REO/SW/FW 302 Producer: RXDMA 303 304 When set, the MPDU was received as part of an A-MPDU. 305 <legal all> 306 */ 307 308 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 309 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 310 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 311 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 312 313 314 /* Description BAR_FRAME 315 316 Consumer: REO/SW/FW 317 Producer: RXDMA 318 319 When set, the received frame is a BAR frame. After processing, 320 this frame shall be pushed to SW or deleted. 321 <legal all> 322 */ 323 324 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 325 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 326 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 327 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 328 329 330 /* Description PN_FIELDS_CONTAIN_VALID_INFO 331 332 Consumer: REO/SW/FW 333 Producer: RXDMA 334 335 Copied here by RXDMA from RX_MPDU_END 336 When not set, REO will Not perform a PN sequence number 337 check 338 */ 339 340 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 341 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 342 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 343 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 344 345 346 /* Description RAW_MPDU 347 348 Field only valid when first_msdu_in_mpdu_flag is set. 349 350 When set, the contents in the MSDU buffer contains a 'RAW' 351 MPDU. This 'RAW' MPDU might be spread out over multiple 352 MSDU buffers. 353 <legal all> 354 */ 355 356 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 357 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 358 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 359 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 360 361 362 /* Description MORE_FRAGMENT_FLAG 363 364 The More Fragment bit setting from the MPDU header of the 365 received frame 366 367 <legal all> 368 */ 369 370 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 371 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 372 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 373 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 374 375 376 /* Description SRC_INFO 377 378 Source (virtual) device/interface info. associated with 379 this peer 380 381 This field gets passed on by REO to PPE in the EDMA descriptor 382 ('REO_TO_PPE_RING'). 383 384 Hamilton v1 used this for 'vdev_id' instead. 385 <legal all> 386 */ 387 388 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 389 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 390 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 391 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 392 393 394 /* Description MPDU_QOS_CONTROL_VALID 395 396 When set, the MPDU has a QoS control field. 397 398 In case of ndp or phy_err, this field will never be set. 399 400 <legal all> 401 */ 402 403 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 404 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 405 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 406 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 407 408 409 /* Description TID 410 411 Field only valid when mpdu_qos_control_valid is set 412 413 The TID field in the QoS control field 414 <legal all> 415 */ 416 417 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 418 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 419 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 420 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 421 422 423 /* Description PEER_META_DATA 424 425 Meta data that SW has programmed in the Peer table entry 426 of the transmitting STA. 427 <legal all> 428 */ 429 430 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 431 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 432 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 433 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 434 435 436 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 437 438 Consumer: REO 439 Producer: RXDMA 440 441 Address (lower 32 bits) of the REO queue descriptor 442 443 Alternatively, as per FR63739, REO internally looks up the 444 queue descriptor address from 'Sw_peer_id' and 'Tid.' In 445 this mode, RXDMA fills 'Sw_peer_id' from 'RX_MPDU_START' 446 in the LSB 16 bits. 'Tid' is available in 'RX_MPDU_DETAILS.' 447 448 <legal all> 449 */ 450 451 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 452 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 453 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 454 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 455 456 457 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 458 459 Consumer: REO 460 Producer: RXDMA 461 462 Address (upper 8 bits) of the REO queue descriptor 463 Alternatively, as per FR63739, REO internally looks up the 464 queue descriptor address from 'Sw_peer_id' and 'Tid.' In 465 this mode, this field is unused. 466 <legal all> 467 */ 468 469 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 470 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 471 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 472 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 473 474 475 /* Description ROUNDED_MPDU_BYTE_COUNT 476 477 An approximation of the number of bytes received in this 478 MPDU. 479 Used to keeps stats on the amount of data flowing through 480 a queue. 481 <legal all> 482 */ 483 484 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 485 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 486 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 487 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 488 489 490 /* Description REO_DESTINATION_INDICATION 491 492 RXDMA copy the MPDU's first MSDU's destination indication 493 field here. This is used for REO to be able to re-route 494 the packet to a different SW destination ring if the packet 495 is detected as error in REO. 496 497 The ID of the REO exit ring where the MSDU frame shall push 498 after (MPDU level) reordering has finished. 499 500 <enum 0 reo_destination_sw0> Reo will push the frame into 501 the REO2SW0 ring 502 <enum 1 reo_destination_sw1> Reo will push the frame into 503 the REO2SW1 ring 504 <enum 2 reo_destination_sw2> Reo will push the frame into 505 the REO2SW2 ring 506 <enum 3 reo_destination_sw3> Reo will push the frame into 507 the REO2SW3 ring 508 <enum 4 reo_destination_sw4> Reo will push the frame into 509 the REO2SW4 ring 510 <enum 5 reo_destination_release> Reo will push the frame 511 into the REO_release ring 512 <enum 6 reo_destination_fw> Reo will push the frame into 513 the REO2FW ring 514 <enum 7 reo_destination_sw5> Reo will push the frame into 515 the REO2SW5 ring (REO remaps this in chips without REO2SW5 516 ring, e.g. Pine) 517 <enum 8 reo_destination_sw6> Reo will push the frame into 518 the REO2SW6 ring (REO remaps this in chips without REO2SW6 519 ring, e.g. Pine) 520 <enum 9 reo_destination_sw7> Reo will push the frame into 521 the REO2SW7 ring (REO remaps this in chips without REO2SW7 522 ring) 523 <enum 10 reo_destination_sw8> Reo will push the frame into 524 the REO2SW8 ring (REO remaps this in chips without REO2SW8 525 ring) 526 <enum 11 reo_destination_11> REO remaps this 527 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 528 REO remaps this 529 <enum 14 reo_destination_14> REO remaps this 530 <enum 15 reo_destination_15> REO remaps this 531 <enum 16 reo_destination_16> REO remaps this 532 <enum 17 reo_destination_17> REO remaps this 533 <enum 18 reo_destination_18> REO remaps this 534 <enum 19 reo_destination_19> REO remaps this 535 <enum 20 reo_destination_20> REO remaps this 536 <enum 21 reo_destination_21> REO remaps this 537 <enum 22 reo_destination_22> REO remaps this 538 <enum 23 reo_destination_23> REO remaps this 539 <enum 24 reo_destination_24> REO remaps this 540 <enum 25 reo_destination_25> REO remaps this 541 <enum 26 reo_destination_26> REO remaps this 542 <enum 27 reo_destination_27> REO remaps this 543 <enum 28 reo_destination_28> REO remaps this 544 <enum 29 reo_destination_29> REO remaps this 545 <enum 30 reo_destination_30> REO remaps this 546 <enum 31 reo_destination_31> REO remaps this 547 548 <legal all> 549 */ 550 551 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 552 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 553 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 554 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 555 556 557 /* Description FRAMELESS_BAR 558 559 When set, this REO entrance ring struct contains BAR info 560 from a multi TID BAR frame. The original multi TID BAR 561 frame itself contained all the REO info for the first TID, 562 but all the subsequent TID info and their linkage to the 563 REO descriptors is passed down as 'frameless' BAR info. 564 565 566 The only fields valid in this descriptor when this bit is 567 set are: 568 Rx_reo_queue_desc_addr_31_0 569 RX_reo_queue_desc_addr_39_32 570 571 And within the 572 Reo_level_mpdu_frame_info: 573 Within Rx_mpdu_desc_info_details: 574 Mpdu_Sequence_number 575 BAR_frame 576 Peer_meta_data 577 All other fields shall be set to 0 578 579 <legal all> 580 */ 581 582 #define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 583 #define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 584 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 585 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 586 587 588 /* Description RESERVED_5A 589 590 <legal 0> 591 */ 592 593 #define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 594 #define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 595 #define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 596 #define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 597 598 599 /* Description RXDMA_PUSH_REASON 600 601 Indicates why rxdma pushed the frame to this ring 602 603 This field is ignored by REO. 604 605 <enum 0 rxdma_error_detected> RXDMA detected an error an 606 pushed this frame to this queue 607 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 608 to this queue per received routing instructions. No error 609 within RXDMA was detected 610 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 611 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 612 set, but instead WBM might just see a NULL pointer in the 613 MSDU link descriptor. This is to be considered a normal 614 condition for this scenario. 615 616 <legal 0 - 2> 617 */ 618 619 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 620 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 621 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 622 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 623 624 625 /* Description RXDMA_ERROR_CODE 626 627 Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. 628 629 630 This field is ignored by REO. 631 632 <enum 0 rxdma_overflow_err>MPDU frame is not complete due 633 to a FIFO overflow error in RXPCU. 634 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 635 due to receiving incomplete MPDU from the PHY 636 <enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed 637 638 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error 639 or CRYPTO received an encrypted frame, but did not get 640 a valid corresponding key id in the peer entry. 641 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error 642 643 <enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted 644 frame error when encrypted was expected 645 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length 646 error 647 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max number 648 of MSDUs allowed in an MPDU got exceeded 649 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error 650 651 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 652 parsing error 653 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 654 during SA search 655 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 656 during DA search 657 <enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout 658 during flow search 659 <enum 13 rxdma_flush_request>RXDMA received a flush request 660 661 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 662 present as well as a fragmented MPDU. A-MSDU defragmentation 663 is not supported in Lithium SW so this is treated as an 664 error. 665 <enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast 666 echo 667 <enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an 668 A-MSDU with either 'from DS = 0' with an SA mismatching 669 TA or 'to DS = 0' with a DA mismatching RA. 670 <enum 17 rxdma_unauthorized_wds_err>RX PCU reported that 671 Rx peer entry did not indicate 'authorized_to_send_WDS' 672 and also indicated 'from DS = to DS = 1.' 673 <enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported 674 a broadcast or multicast RA as well as either A-MSDU present 675 or 'from DS = to DS = 1.' 676 */ 677 678 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 679 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 680 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 681 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 682 683 684 /* Description MPDU_FRAGMENT_NUMBER 685 686 Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag 687 is set. 688 689 The fragment number from the 802.11 header. 690 691 Note that the sequence number is embedded in the field: 692 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number 693 694 695 <legal all> 696 */ 697 698 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 699 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 700 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 701 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 702 703 704 /* Description SW_EXCEPTION 705 706 When not set, REO is performing all its default MPDU processing 707 operations, 708 When set, this REO entrance descriptor is generated by FW, 709 and should be processed as an exception. This implies: 710 NO re-order function is needed. 711 MPDU delinking is determined by the setting of field SW_excection_mpdu_delink 712 713 Destination ring selection is based on the setting of the 714 field SW_exception_destination_ring_valid 715 In the destination ring descriptor set bit: SW_exception_entry 716 717 Feature supported only in HastingsPrime 718 <legal all> 719 */ 720 721 #define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 722 #define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 723 #define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 724 #define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 725 726 727 /* Description SW_EXCEPTION_MPDU_DELINK 728 729 Field only valid when SW_exception is set. 730 1'b0: REO should NOT delink the MPDU, and thus pass this 731 MPDU on to the destination ring as is. This implies that 732 in the REO_DESTINATION_RING struct field Buf_or_link_desc_addr_info 733 should point to an MSDU link descriptor 734 1'b1: REO should perform the normal MPDU delink into MSDU 735 operations. 736 Feature supported only in HastingsPrime 737 <legal all> 738 */ 739 740 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 741 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 742 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 743 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 744 745 746 /* Description SW_EXCEPTION_DESTINATION_RING_VALID 747 748 Field only valid when SW_exception is set. 749 1'b0: REO shall push the MPDU (or delinked MPDU based on 750 the setting of SW_exception_mpdu_delink) to the destination 751 ring according to field reo_destination_indication. 752 1'b1: REO shall push the MPDU (or delinked MPDU based on 753 the setting of SW_exception_mpdu_delink) to the destination 754 ring according to field SW_exception_destination_ring. 755 Feature supported only in HastingsPrime 756 <legal all> 757 */ 758 759 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 760 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 761 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 762 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 763 764 765 /* Description SW_EXCEPTION_DESTINATION_RING 766 767 Field only valid when fields SW_exception and SW_exception_destination_ring_valid 768 are set. 769 The ID of the ring where REO shall push this frame. 770 <enum 0 reo_destination_sw0> Reo will push the frame into 771 the REO2SW0 ring 772 <enum 1 reo_destination_sw1> Reo will push the frame into 773 the REO2SW1 ring 774 <enum 2 reo_destination_sw2> Reo will push the frame into 775 the REO2SW1 ring 776 <enum 3 reo_destination_sw3> Reo will push the frame into 777 the REO2SW1 ring 778 <enum 4 reo_destination_sw4> Reo will push the frame into 779 the REO2SW1 ring 780 <enum 5 reo_destination_release> Reo will push the frame 781 into the REO_release ring 782 <enum 6 reo_destination_fw> Reo will push the frame into 783 the REO2FW ring 784 <enum 7 reo_destination_sw5> REO remaps this 785 <enum 8 reo_destination_sw6> REO remaps this 786 <enum 9 reo_destination_sw7> REO remaps this 787 <enum 10 reo_destination_sw8> REO remaps this 788 <enum 11 reo_destination_11> REO remaps this 789 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 790 REO remaps this 791 <enum 14 reo_destination_14> REO remaps this 792 <enum 15 reo_destination_15> REO remaps this 793 <enum 16 reo_destination_16> REO remaps this 794 <enum 17 reo_destination_17> REO remaps this 795 <enum 18 reo_destination_18> REO remaps this 796 <enum 19 reo_destination_19> REO remaps this 797 <enum 20 reo_destination_20> REO remaps this 798 <enum 21 reo_destination_21> REO remaps this 799 <enum 22 reo_destination_22> REO remaps this 800 <enum 23 reo_destination_23> REO remaps this 801 <enum 24 reo_destination_24> REO remaps this 802 <enum 25 reo_destination_25> REO remaps this 803 <enum 26 reo_destination_26> REO remaps this 804 <enum 27 reo_destination_27> REO remaps this 805 <enum 28 reo_destination_28> REO remaps this 806 <enum 29 reo_destination_29> REO remaps this 807 <enum 30 reo_destination_30> REO remaps this 808 <enum 31 reo_destination_31> REO remaps this 809 810 Feature supported only in HastingsPrime 811 <legal all> 812 */ 813 814 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 815 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 816 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 817 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 818 819 820 /* Description MPDU_SEQUENCE_NUMBER 821 822 Consumer: REO/SW/FW 823 Producer: RXDMA 824 825 The field can have two different meanings based on the setting 826 of sub-field Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.BAR_frame: 827 828 829 'BAR_frame' is NOT set: 830 The MPDU sequence number of the received frame. 831 832 'BAR_frame' is set. 833 The MPDU Start sequence number from the BAR frame 834 <legal all> 835 */ 836 837 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 838 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 839 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 840 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 841 842 843 /* Description RESERVED_6A 844 845 Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 846 Mpdu_qos_control_valid is set 847 848 This indicates whether the 'Ack policy' field within the 849 QoS control field of the MPDU indicates 'no-Ack.' 850 <legal all> 851 */ 852 853 #define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 854 #define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 855 #define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 856 #define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 857 858 859 /* Description PHY_PPDU_ID 860 861 A PPDU counter value that PHY increments for every PPDU 862 received 863 The counter value wraps around. Pine RXDMA can be configured 864 to copy this from the RX_PPDU_START TLV for every output 865 descriptor. 866 867 This field is ignored by REO. 868 869 Feature supported only in Pine 870 <legal all> 871 */ 872 873 #define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c 874 #define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 875 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 876 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff 877 878 879 /* Description SRC_LINK_ID 880 881 Consumer: SW 882 Producer: RXDMA 883 884 Set to the link ID of the PMAC that received the frame 885 <legal all> 886 */ 887 888 #define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c 889 #define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 890 #define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 891 #define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 892 893 894 /* Description RESERVED_7A 895 896 Hamilton v1 filled the link ID of the PMAC that received 897 the frame here. 898 <legal 0> 899 */ 900 901 #define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c 902 #define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 903 #define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 904 #define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 905 906 907 /* Description RING_ID 908 909 Consumer: SW/REO/DEBUG 910 Producer: SRNG (of RXDMA) 911 912 For debugging. 913 This field is filled in by the SRNG module. 914 It help to identify the ring that is being looked <legal 915 all> 916 */ 917 918 #define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c 919 #define REO_ENTRANCE_RING_RING_ID_LSB 20 920 #define REO_ENTRANCE_RING_RING_ID_MSB 27 921 #define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 922 923 924 /* Description LOOPING_COUNT 925 926 Consumer: SW/REO/DEBUG 927 Producer: SRNG (of RXDMA) 928 929 For debugging. 930 This field is filled in by the SRNG module. 931 932 A count value that indicates the number of times the producer 933 of entries into this Ring has looped around the ring. 934 At initialization time, this value is set to 0. On the first 935 loop, this value is set to 1. After the max value is reached 936 allowed by the number of bits for this field, the count 937 value continues with 0 again. 938 939 In case SW is the consumer of the ring entries, it can use 940 this field to figure out up to where the producer of entries 941 has created new entries. This eliminates the need to check 942 where the "head pointer' of the ring is located once the 943 SW starts processing an interrupt indicating that new entries 944 have been put into this ring... 945 946 Also note that SW if it wants only needs to look at the 947 LSB bit of this count value. 948 <legal all> 949 */ 950 951 #define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c 952 #define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 953 #define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 954 #define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 955 956 957 958 #endif // REO_ENTRANCE_RING 959