1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_CACHE_H_ 27 #define _REO_FLUSH_CACHE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 33 34 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 35 36 37 struct reo_flush_cache { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t flush_addr_31_0 : 32; // [31:0] 41 uint32_t flush_addr_39_32 : 8, // [7:0] 42 forward_all_mpdus_in_queue : 1, // [8:8] 43 release_cache_block_index : 1, // [9:9] 44 cache_block_resource_index : 2, // [11:10] 45 flush_without_invalidate : 1, // [12:12] 46 block_cache_usage_after_flush : 1, // [13:13] 47 flush_entire_cache : 1, // [14:14] 48 flush_queue_1k_desc : 1, // [15:15] 49 reserved_2b : 16; // [31:16] 50 uint32_t reserved_3a : 32; // [31:0] 51 uint32_t reserved_4a : 32; // [31:0] 52 uint32_t reserved_5a : 32; // [31:0] 53 uint32_t reserved_6a : 32; // [31:0] 54 uint32_t reserved_7a : 32; // [31:0] 55 uint32_t reserved_8a : 32; // [31:0] 56 uint32_t tlv64_padding : 32; // [31:0] 57 #else 58 struct uniform_reo_cmd_header cmd_header; 59 uint32_t flush_addr_31_0 : 32; // [31:0] 60 uint32_t reserved_2b : 16, // [31:16] 61 flush_queue_1k_desc : 1, // [15:15] 62 flush_entire_cache : 1, // [14:14] 63 block_cache_usage_after_flush : 1, // [13:13] 64 flush_without_invalidate : 1, // [12:12] 65 cache_block_resource_index : 2, // [11:10] 66 release_cache_block_index : 1, // [9:9] 67 forward_all_mpdus_in_queue : 1, // [8:8] 68 flush_addr_39_32 : 8; // [7:0] 69 uint32_t reserved_3a : 32; // [31:0] 70 uint32_t reserved_4a : 32; // [31:0] 71 uint32_t reserved_5a : 32; // [31:0] 72 uint32_t reserved_6a : 32; // [31:0] 73 uint32_t reserved_7a : 32; // [31:0] 74 uint32_t reserved_8a : 32; // [31:0] 75 uint32_t tlv64_padding : 32; // [31:0] 76 #endif 77 }; 78 79 80 /* Description CMD_HEADER 81 82 Consumer: REO 83 Producer: SW 84 85 Details for command execution tracking purposes. 86 */ 87 88 89 /* Description REO_CMD_NUMBER 90 91 Consumer: REO/SW/DEBUG 92 Producer: SW 93 94 This number can be used by SW to track, identify and link 95 the created commands with the command statusses 96 97 98 <legal all> 99 */ 100 101 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 102 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 103 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 104 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 105 106 107 /* Description REO_STATUS_REQUIRED 108 109 Consumer: REO 110 Producer: SW 111 112 <enum 0 NoStatus> REO does not need to generate a status 113 TLV for the execution of this command 114 <enum 1 StatusRequired> REO shall generate a status TLV 115 for the execution of this command 116 117 <legal all> 118 */ 119 120 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 121 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 122 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 123 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 124 125 126 /* Description RESERVED_0A 127 128 <legal 0> 129 */ 130 131 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 132 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 133 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 134 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 135 136 137 /* Description FLUSH_ADDR_31_0 138 139 Consumer: REO 140 Producer: SW 141 142 Address (lower 32 bits) of the descriptor to flush 143 <legal all> 144 */ 145 146 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 147 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 148 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 149 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 150 151 152 /* Description FLUSH_ADDR_39_32 153 154 Consumer: REO 155 Producer: SW 156 157 Address (upper 8 bits) of the descriptor to flush 158 <legal all> 159 */ 160 161 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 162 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 163 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 164 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 165 166 167 /* Description FORWARD_ALL_MPDUS_IN_QUEUE 168 169 Is only allowed to be set when the flush address corresponds 170 with a REO descriptor. 171 172 When set, REO shall first forward all the MPDUs held in 173 the indicated re-order queue, before flushing the descriptor 174 from the cache. 175 <legal all> 176 */ 177 178 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 179 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 180 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 181 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 182 183 184 /* Description RELEASE_CACHE_BLOCK_INDEX 185 186 Field not valid when Flush_entire_cache is set. 187 188 If SW has previously used a blocking resource that it now 189 wants to re-use for this command, this bit shall be set. 190 It prevents SW from having to send a separate REO_UNBLOCK_CACHE 191 command. 192 193 When set, HW will first release the blocking resource (indicated 194 in field 'Cache_block_resouce_index') before this command 195 gets executed. 196 If that resource was already unblocked, this will be considered 197 an error. This command will not be executed, and an error 198 shall be returned. 199 <legal all> 200 */ 201 202 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 203 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 204 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 205 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 206 207 208 /* Description CACHE_BLOCK_RESOURCE_INDEX 209 210 Field not valid when Flush_entire_cache is set. 211 212 Indicates which of the four blocking resources in REO will 213 be assigned for managing the blocking of this (descriptor) 214 address 215 <legal all> 216 */ 217 218 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 219 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 220 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 221 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 222 223 224 /* Description FLUSH_WITHOUT_INVALIDATE 225 226 Field not valid when Flush_entire_cache is set. 227 228 When set, REO shall flush the cache line contents from the 229 cache, but there is NO need to invalidate the cache line 230 entry... The contents in the cache can be maintained. This 231 feature can be used by SW (and DV) to get a current snapshot 232 of the contents in the cache 233 234 <legal all> 235 */ 236 237 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 238 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 239 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 240 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 241 242 243 /* Description BLOCK_CACHE_USAGE_AFTER_FLUSH 244 245 Field not valid when Flush_entire_cache is set. 246 247 When set, REO shall block any cache accesses to this address 248 till explicitly unblocked. 249 250 Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue' 251 to ensure all packets are flushed out in order to make sure 252 this queue desc is not in one of the aging link lists. 253 In case SW does not want to flush the MPDUs in the queue, 254 see the recipe description below this TLV definition. 255 256 The 'blocking' index to be used for this is indicated in 257 field 'cache_block_resource_index'. If SW had previously 258 used this blocking resource and was not freed up yet, SW 259 shall first unblock that index (by setting bit Release_cache_block_index) 260 or use an unblock command. 261 262 If the resource indicated here was already blocked (and 263 did not get unblocked in this command), it is considered 264 an error scenario... 265 No flush shall happen. The status for this command shall 266 indicate error. 267 268 <legal all> 269 */ 270 271 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 272 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 273 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 274 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 275 276 277 /* Description FLUSH_ENTIRE_CACHE 278 279 When set, the entire cache shall be flushed. The entire 280 cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND' 281 is received with bit unblock type set to unblock_cache. 282 All other fields in this command are to be ignored. 283 284 Note that flushing the entire cache has no changes to the 285 current settings of the blocking resource settings 286 287 <legal all> 288 */ 289 290 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 291 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 292 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 293 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 294 295 296 /* Description FLUSH_QUEUE_1K_DESC 297 298 When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor 299 after flushing the 'RX_REO_QUEUE' descriptor. 300 301 This bit shall only be set when the BA_window_size > 255 302 in 'RX_REO_QUEUE.' 303 <legal all> 304 */ 305 306 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 307 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 308 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 309 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 310 311 312 /* Description RESERVED_2B 313 314 <legal 0> 315 */ 316 317 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 318 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 319 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 320 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 321 322 323 /* Description RESERVED_3A 324 325 <legal 0> 326 */ 327 328 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 329 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 330 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 331 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 332 333 334 /* Description RESERVED_4A 335 336 <legal 0> 337 */ 338 339 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 340 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 341 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 342 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 343 344 345 /* Description RESERVED_5A 346 347 <legal 0> 348 */ 349 350 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 351 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 352 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 353 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 354 355 356 /* Description RESERVED_6A 357 358 <legal 0> 359 */ 360 361 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 362 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 363 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 364 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 365 366 367 /* Description RESERVED_7A 368 369 <legal 0> 370 */ 371 372 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 373 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 374 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 375 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 376 377 378 /* Description RESERVED_8A 379 380 <legal 0> 381 */ 382 383 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 384 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 385 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 386 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 387 388 389 /* Description TLV64_PADDING 390 391 Automatic DWORD padding inserted while converting TLV32 392 to TLV64 for 64 bit ARCH 393 <legal 0> 394 */ 395 396 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 397 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 398 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 399 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 400 401 402 403 #endif // REO_FLUSH_CACHE 404