1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 27 #define _REO_FLUSH_CACHE_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 35 36 37 struct reo_flush_cache_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, // [0:0] 41 block_error_details : 2, // [2:1] 42 reserved_2a : 5, // [7:3] 43 cache_controller_flush_status_hit : 1, // [8:8] 44 cache_controller_flush_status_desc_type : 3, // [11:9] 45 cache_controller_flush_status_client_id : 4, // [15:12] 46 cache_controller_flush_status_error : 2, // [17:16] 47 cache_controller_flush_count : 8, // [25:18] 48 flush_queue_1k_desc : 1, // [26:26] 49 reserved_2b : 5; // [31:27] 50 uint32_t reserved_3a : 32; // [31:0] 51 uint32_t reserved_4a : 32; // [31:0] 52 uint32_t reserved_5a : 32; // [31:0] 53 uint32_t reserved_6a : 32; // [31:0] 54 uint32_t reserved_7a : 32; // [31:0] 55 uint32_t reserved_8a : 32; // [31:0] 56 uint32_t reserved_9a : 32; // [31:0] 57 uint32_t reserved_10a : 32; // [31:0] 58 uint32_t reserved_11a : 32; // [31:0] 59 uint32_t reserved_12a : 32; // [31:0] 60 uint32_t reserved_13a : 32; // [31:0] 61 uint32_t reserved_14a : 32; // [31:0] 62 uint32_t reserved_15a : 32; // [31:0] 63 uint32_t reserved_16a : 32; // [31:0] 64 uint32_t reserved_17a : 32; // [31:0] 65 uint32_t reserved_18a : 32; // [31:0] 66 uint32_t reserved_19a : 32; // [31:0] 67 uint32_t reserved_20a : 32; // [31:0] 68 uint32_t reserved_21a : 32; // [31:0] 69 uint32_t reserved_22a : 32; // [31:0] 70 uint32_t reserved_23a : 32; // [31:0] 71 uint32_t reserved_24a : 32; // [31:0] 72 uint32_t reserved_25a : 28, // [27:0] 73 looping_count : 4; // [31:28] 74 #else 75 struct uniform_reo_status_header status_header; 76 uint32_t reserved_2b : 5, // [31:27] 77 flush_queue_1k_desc : 1, // [26:26] 78 cache_controller_flush_count : 8, // [25:18] 79 cache_controller_flush_status_error : 2, // [17:16] 80 cache_controller_flush_status_client_id : 4, // [15:12] 81 cache_controller_flush_status_desc_type : 3, // [11:9] 82 cache_controller_flush_status_hit : 1, // [8:8] 83 reserved_2a : 5, // [7:3] 84 block_error_details : 2, // [2:1] 85 error_detected : 1; // [0:0] 86 uint32_t reserved_3a : 32; // [31:0] 87 uint32_t reserved_4a : 32; // [31:0] 88 uint32_t reserved_5a : 32; // [31:0] 89 uint32_t reserved_6a : 32; // [31:0] 90 uint32_t reserved_7a : 32; // [31:0] 91 uint32_t reserved_8a : 32; // [31:0] 92 uint32_t reserved_9a : 32; // [31:0] 93 uint32_t reserved_10a : 32; // [31:0] 94 uint32_t reserved_11a : 32; // [31:0] 95 uint32_t reserved_12a : 32; // [31:0] 96 uint32_t reserved_13a : 32; // [31:0] 97 uint32_t reserved_14a : 32; // [31:0] 98 uint32_t reserved_15a : 32; // [31:0] 99 uint32_t reserved_16a : 32; // [31:0] 100 uint32_t reserved_17a : 32; // [31:0] 101 uint32_t reserved_18a : 32; // [31:0] 102 uint32_t reserved_19a : 32; // [31:0] 103 uint32_t reserved_20a : 32; // [31:0] 104 uint32_t reserved_21a : 32; // [31:0] 105 uint32_t reserved_22a : 32; // [31:0] 106 uint32_t reserved_23a : 32; // [31:0] 107 uint32_t reserved_24a : 32; // [31:0] 108 uint32_t looping_count : 4, // [31:28] 109 reserved_25a : 28; // [27:0] 110 #endif 111 }; 112 113 114 /* Description STATUS_HEADER 115 116 Consumer: SW 117 Producer: REO 118 119 Details that can link this status with the original command. 120 It also contains info on how long REO took to execute this 121 command. 122 */ 123 124 125 /* Description REO_STATUS_NUMBER 126 127 Consumer: SW , DEBUG 128 Producer: REO 129 130 The value in this field is equal to value of the 'REO_CMD_Number' 131 field the REO command 132 133 This field helps to correlate the statuses with the REO 134 commands. 135 136 <legal all> 137 */ 138 139 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 140 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 141 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 142 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 143 144 145 /* Description CMD_EXECUTION_TIME 146 147 Consumer: DEBUG 148 Producer: REO 149 150 The amount of time REO took to excecute the command. Note 151 that this time does not include the duration of the command 152 waiting in the command ring, before the execution started. 153 154 155 In us. 156 157 <legal all> 158 */ 159 160 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 161 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 162 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 163 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 164 165 166 /* Description REO_CMD_EXECUTION_STATUS 167 168 Consumer: DEBUG 169 Producer: REO 170 171 Execution status of the command. 172 173 <enum 0 reo_successful_execution> Command has successfully 174 be executed 175 <enum 1 reo_blocked_execution> Command could not be executed 176 as the queue or cache was blocked 177 <enum 2 reo_failed_execution> Command has encountered problems 178 when executing, like the queue descriptor not being valid. 179 None of the status fields in the entire STATUS TLV are valid. 180 181 <enum 3 reo_resource_blocked> Command is NOT executed because 182 one or more descriptors were blocked. This is SW programming 183 mistake. 184 None of the status fields in the entire STATUS TLV are valid. 185 186 187 <legal 0-3> 188 */ 189 190 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 191 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 192 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 193 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 194 195 196 /* Description RESERVED_0A 197 198 <legal 0> 199 */ 200 201 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 202 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 203 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 204 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 205 206 207 /* Description TIMESTAMP 208 209 Timestamp at the moment that this status report is written. 210 211 212 <legal all> 213 */ 214 215 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 216 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 217 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 218 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 219 220 221 /* Description ERROR_DETECTED 222 223 Status for blocking resource handling 224 225 0: No error has been detected while executing this command 226 227 1: an error in the blocking resource management was detected 228 229 See field 'Block_error_details' 230 */ 231 232 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 233 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 234 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 235 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 236 237 238 /* Description BLOCK_ERROR_DETAILS 239 240 Field only valid when 'Error_detected' is set. 241 0: no blocking related error found 242 1: blocking resource was already in use 243 2: resource that was asked to be unblocked, was not blocked 244 245 <legal 0-2> 246 */ 247 248 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 249 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 250 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 251 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 252 253 254 /* Description RESERVED_2A 255 256 <legal 0> 257 */ 258 259 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 260 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 261 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 262 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 263 264 265 /* Description CACHE_CONTROLLER_FLUSH_STATUS_HIT 266 267 The status that the cache controller returned for executing 268 the flush command 269 270 descriptor hit 271 1 = hit 272 0 = miss 273 <legal all> 274 */ 275 276 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 277 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 278 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 279 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 280 281 282 /* Description CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE 283 284 The status that the cache controller returned for executing 285 the flush command 286 Descriptor type 287 FLOW_QUEUE_DESCRIPTOR 3'd0 288 MPDU_LINK_DESCRIPTOR 3'd4 289 <legal all> 290 */ 291 292 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 293 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 294 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 295 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 296 297 298 /* Description CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID 299 300 The status that the cache controller returned for executing 301 the flush command 302 303 client ID 304 Module who made flush the request 305 306 In REO, this is always set to 0 307 <legal 0> 308 */ 309 310 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 311 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 312 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 313 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 314 315 316 /* Description CACHE_CONTROLLER_FLUSH_STATUS_ERROR 317 318 The status that the cache controller returned for executing 319 the flush command 320 321 Error condition 322 2'b00: No error found 323 2'b01: HW IF still busy 324 2'b10: Line is currently locked. Used for the one line flush 325 command. 326 2'b11: At least one line is currently still locked. Used 327 for the cache flush command. 328 329 <legal all> 330 */ 331 332 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 333 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 334 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 335 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 336 337 338 /* Description CACHE_CONTROLLER_FLUSH_COUNT 339 340 The number of lines that were actually flushed out. 341 <legal all> 342 */ 343 344 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 345 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 346 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 347 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 348 349 350 /* Description FLUSH_QUEUE_1K_DESC 351 352 When set, REO has flushed the 'RX_REO_QUEUE_1K' descriptor 353 after flushing the 'RX_REO_QUEUE' descriptor. 354 <legal all> 355 */ 356 357 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 358 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 359 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 360 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 361 362 363 /* Description RESERVED_2B 364 365 <legal 0> 366 */ 367 368 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 369 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 370 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 371 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 372 373 374 /* Description RESERVED_3A 375 376 <legal 0> 377 */ 378 379 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 380 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 381 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 382 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 383 384 385 /* Description RESERVED_4A 386 387 <legal 0> 388 */ 389 390 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 391 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 392 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 393 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 394 395 396 /* Description RESERVED_5A 397 398 <legal 0> 399 */ 400 401 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 402 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 403 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 404 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 405 406 407 /* Description RESERVED_6A 408 409 <legal 0> 410 */ 411 412 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 413 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 414 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 415 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 416 417 418 /* Description RESERVED_7A 419 420 <legal 0> 421 */ 422 423 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 424 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 425 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 426 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 427 428 429 /* Description RESERVED_8A 430 431 <legal 0> 432 */ 433 434 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 435 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 436 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 437 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 438 439 440 /* Description RESERVED_9A 441 442 <legal 0> 443 */ 444 445 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 446 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 447 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 448 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 449 450 451 /* Description RESERVED_10A 452 453 <legal 0> 454 */ 455 456 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 457 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 458 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 459 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 460 461 462 /* Description RESERVED_11A 463 464 <legal 0> 465 */ 466 467 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 468 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 469 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 470 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 471 472 473 /* Description RESERVED_12A 474 475 <legal 0> 476 */ 477 478 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 479 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 480 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 481 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 482 483 484 /* Description RESERVED_13A 485 486 <legal 0> 487 */ 488 489 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 490 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 491 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 492 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 493 494 495 /* Description RESERVED_14A 496 497 <legal 0> 498 */ 499 500 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 501 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 502 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 503 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 504 505 506 /* Description RESERVED_15A 507 508 <legal 0> 509 */ 510 511 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 512 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 513 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 514 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 515 516 517 /* Description RESERVED_16A 518 519 <legal 0> 520 */ 521 522 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 523 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 524 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 525 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 526 527 528 /* Description RESERVED_17A 529 530 <legal 0> 531 */ 532 533 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 534 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 535 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 536 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 537 538 539 /* Description RESERVED_18A 540 541 <legal 0> 542 */ 543 544 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 545 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 546 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 547 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 548 549 550 /* Description RESERVED_19A 551 552 <legal 0> 553 */ 554 555 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 556 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 557 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 558 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 559 560 561 /* Description RESERVED_20A 562 563 <legal 0> 564 */ 565 566 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 567 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 568 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 569 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 570 571 572 /* Description RESERVED_21A 573 574 <legal 0> 575 */ 576 577 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 578 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 579 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 580 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 581 582 583 /* Description RESERVED_22A 584 585 <legal 0> 586 */ 587 588 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 589 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 590 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 591 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 592 593 594 /* Description RESERVED_23A 595 596 <legal 0> 597 */ 598 599 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 600 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 601 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 602 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 603 604 605 /* Description RESERVED_24A 606 607 <legal 0> 608 */ 609 610 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 611 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 612 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 613 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 614 615 616 /* Description RESERVED_25A 617 618 <legal 0> 619 */ 620 621 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 622 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 623 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 624 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 625 626 627 /* Description LOOPING_COUNT 628 629 A count value that indicates the number of times the producer 630 of entries into this Ring has looped around the ring. 631 At initialization time, this value is set to 0. On the first 632 loop, this value is set to 1. After the max value is reached 633 allowed by the number of bits for this field, the count 634 value continues with 0 again. 635 636 In case SW is the consumer of the ring entries, it can use 637 this field to figure out up to where the producer of entries 638 has created new entries. This eliminates the need to check 639 where the "head pointer' of the ring is located once the 640 SW starts processing an interrupt indicating that new entries 641 have been put into this ring... 642 643 Also note that SW if it wants only needs to look at the 644 LSB bit of this count value. 645 <legal all> 646 */ 647 648 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 649 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 650 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 651 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 652 653 654 655 #endif // REO_FLUSH_CACHE_STATUS 656