xref: /wlan-driver/fw-api/hw/qca5332/reo_flush_queue.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name 
20*5113495bSYour Name 
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name 
24*5113495bSYour Name 
25*5113495bSYour Name 
26*5113495bSYour Name #ifndef _REO_FLUSH_QUEUE_H_
27*5113495bSYour Name #define _REO_FLUSH_QUEUE_H_
28*5113495bSYour Name #if !defined(__ASSEMBLER__)
29*5113495bSYour Name #endif
30*5113495bSYour Name 
31*5113495bSYour Name #include "uniform_reo_cmd_header.h"
32*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
33*5113495bSYour Name 
34*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
35*5113495bSYour Name 
36*5113495bSYour Name 
37*5113495bSYour Name struct reo_flush_queue {
38*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
40*5113495bSYour Name              uint32_t flush_desc_addr_31_0                                    : 32; // [31:0]
41*5113495bSYour Name              uint32_t flush_desc_addr_39_32                                   :  8, // [7:0]
42*5113495bSYour Name                       block_desc_addr_usage_after_flush                       :  1, // [8:8]
43*5113495bSYour Name                       block_resource_index                                    :  2, // [10:9]
44*5113495bSYour Name                       reserved_2a                                             : 21; // [31:11]
45*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
46*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
47*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
48*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
49*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
50*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
51*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
52*5113495bSYour Name #else
53*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
54*5113495bSYour Name              uint32_t flush_desc_addr_31_0                                    : 32; // [31:0]
55*5113495bSYour Name              uint32_t reserved_2a                                             : 21, // [31:11]
56*5113495bSYour Name                       block_resource_index                                    :  2, // [10:9]
57*5113495bSYour Name                       block_desc_addr_usage_after_flush                       :  1, // [8:8]
58*5113495bSYour Name                       flush_desc_addr_39_32                                   :  8; // [7:0]
59*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
60*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
61*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
62*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
63*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
64*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
65*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
66*5113495bSYour Name #endif
67*5113495bSYour Name };
68*5113495bSYour Name 
69*5113495bSYour Name 
70*5113495bSYour Name /* Description		CMD_HEADER
71*5113495bSYour Name 
72*5113495bSYour Name 			Consumer: REO
73*5113495bSYour Name 			Producer: SW
74*5113495bSYour Name 
75*5113495bSYour Name 			Details for command execution tracking purposes.
76*5113495bSYour Name */
77*5113495bSYour Name 
78*5113495bSYour Name 
79*5113495bSYour Name /* Description		REO_CMD_NUMBER
80*5113495bSYour Name 
81*5113495bSYour Name 			Consumer: REO/SW/DEBUG
82*5113495bSYour Name 			Producer: SW
83*5113495bSYour Name 
84*5113495bSYour Name 			This number can be used by SW to track, identify and link
85*5113495bSYour Name 			 the created commands with the command statusses
86*5113495bSYour Name 
87*5113495bSYour Name 
88*5113495bSYour Name 			<legal all>
89*5113495bSYour Name */
90*5113495bSYour Name 
91*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
92*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
93*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
94*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
95*5113495bSYour Name 
96*5113495bSYour Name 
97*5113495bSYour Name /* Description		REO_STATUS_REQUIRED
98*5113495bSYour Name 
99*5113495bSYour Name 			Consumer: REO
100*5113495bSYour Name 			Producer: SW
101*5113495bSYour Name 
102*5113495bSYour Name 			<enum 0 NoStatus> REO does not need to generate a status
103*5113495bSYour Name 			 TLV for the execution of this command
104*5113495bSYour Name 			<enum 1 StatusRequired> REO shall generate a status TLV
105*5113495bSYour Name 			for the execution of this command
106*5113495bSYour Name 
107*5113495bSYour Name 			<legal all>
108*5113495bSYour Name */
109*5113495bSYour Name 
110*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
111*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
112*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
113*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
114*5113495bSYour Name 
115*5113495bSYour Name 
116*5113495bSYour Name /* Description		RESERVED_0A
117*5113495bSYour Name 
118*5113495bSYour Name 			<legal 0>
119*5113495bSYour Name */
120*5113495bSYour Name 
121*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
122*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
123*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
124*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
125*5113495bSYour Name 
126*5113495bSYour Name 
127*5113495bSYour Name /* Description		FLUSH_DESC_ADDR_31_0
128*5113495bSYour Name 
129*5113495bSYour Name 			Consumer: REO
130*5113495bSYour Name 			Producer: SW
131*5113495bSYour Name 
132*5113495bSYour Name 			Address (lower 32 bits) of the descriptor to flush
133*5113495bSYour Name 			<legal all>
134*5113495bSYour Name */
135*5113495bSYour Name 
136*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x0000000000000000
137*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    32
138*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    63
139*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff00000000
140*5113495bSYour Name 
141*5113495bSYour Name 
142*5113495bSYour Name /* Description		FLUSH_DESC_ADDR_39_32
143*5113495bSYour Name 
144*5113495bSYour Name 			Consumer: REO
145*5113495bSYour Name 			Producer: SW
146*5113495bSYour Name 
147*5113495bSYour Name 			Address (upper 8 bits) of the descriptor to flush
148*5113495bSYour Name 			<legal all>
149*5113495bSYour Name */
150*5113495bSYour Name 
151*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x0000000000000008
152*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
153*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
154*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x00000000000000ff
155*5113495bSYour Name 
156*5113495bSYour Name 
157*5113495bSYour Name /* Description		BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
158*5113495bSYour Name 
159*5113495bSYour Name 			When set, REO shall not re-fetch this address till SW explicitly
160*5113495bSYour Name 			 unblocked this address
161*5113495bSYour Name 
162*5113495bSYour Name 			If the blocking resource was already used, this command
163*5113495bSYour Name 			shall fail and an error is reported
164*5113495bSYour Name 
165*5113495bSYour Name 			<legal all>
166*5113495bSYour Name */
167*5113495bSYour Name 
168*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x0000000000000008
169*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
170*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
171*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x0000000000000100
172*5113495bSYour Name 
173*5113495bSYour Name 
174*5113495bSYour Name /* Description		BLOCK_RESOURCE_INDEX
175*5113495bSYour Name 
176*5113495bSYour Name 			Field only valid when 'Block_desc_addr_usage_after_flush
177*5113495bSYour Name 			 ' is set.
178*5113495bSYour Name 
179*5113495bSYour Name 			Indicates which of the four blocking resources in REO will
180*5113495bSYour Name 			 be assigned for managing the blocking of this address.
181*5113495bSYour Name 			<legal all>
182*5113495bSYour Name */
183*5113495bSYour Name 
184*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x0000000000000008
185*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
186*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
187*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x0000000000000600
188*5113495bSYour Name 
189*5113495bSYour Name 
190*5113495bSYour Name /* Description		RESERVED_2A
191*5113495bSYour Name 
192*5113495bSYour Name 			<legal 0>
193*5113495bSYour Name */
194*5113495bSYour Name 
195*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x0000000000000008
196*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
197*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
198*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0x00000000fffff800
199*5113495bSYour Name 
200*5113495bSYour Name 
201*5113495bSYour Name /* Description		RESERVED_3A
202*5113495bSYour Name 
203*5113495bSYour Name 			<legal 0>
204*5113495bSYour Name */
205*5113495bSYour Name 
206*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000000000008
207*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             32
208*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             63
209*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff00000000
210*5113495bSYour Name 
211*5113495bSYour Name 
212*5113495bSYour Name /* Description		RESERVED_4A
213*5113495bSYour Name 
214*5113495bSYour Name 			<legal 0>
215*5113495bSYour Name */
216*5113495bSYour Name 
217*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x0000000000000010
218*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
219*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
220*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0x00000000ffffffff
221*5113495bSYour Name 
222*5113495bSYour Name 
223*5113495bSYour Name /* Description		RESERVED_5A
224*5113495bSYour Name 
225*5113495bSYour Name 			<legal 0>
226*5113495bSYour Name */
227*5113495bSYour Name 
228*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x0000000000000010
229*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             32
230*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             63
231*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff00000000
232*5113495bSYour Name 
233*5113495bSYour Name 
234*5113495bSYour Name /* Description		RESERVED_6A
235*5113495bSYour Name 
236*5113495bSYour Name 			<legal 0>
237*5113495bSYour Name */
238*5113495bSYour Name 
239*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x0000000000000018
240*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
241*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
242*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0x00000000ffffffff
243*5113495bSYour Name 
244*5113495bSYour Name 
245*5113495bSYour Name /* Description		RESERVED_7A
246*5113495bSYour Name 
247*5113495bSYour Name 			<legal 0>
248*5113495bSYour Name */
249*5113495bSYour Name 
250*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000000000000018
251*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             32
252*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             63
253*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff00000000
254*5113495bSYour Name 
255*5113495bSYour Name 
256*5113495bSYour Name /* Description		RESERVED_8A
257*5113495bSYour Name 
258*5113495bSYour Name 			<legal 0>
259*5113495bSYour Name */
260*5113495bSYour Name 
261*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x0000000000000020
262*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
263*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
264*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0x00000000ffffffff
265*5113495bSYour Name 
266*5113495bSYour Name 
267*5113495bSYour Name /* Description		TLV64_PADDING
268*5113495bSYour Name 
269*5113495bSYour Name 			Automatic DWORD padding inserted while converting TLV32
270*5113495bSYour Name 			to TLV64 for 64 bit ARCH
271*5113495bSYour Name 			<legal 0>
272*5113495bSYour Name */
273*5113495bSYour Name 
274*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET                                        0x0000000000000020
275*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB                                           32
276*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB                                           63
277*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK                                          0xffffffff00000000
278*5113495bSYour Name 
279*5113495bSYour Name 
280*5113495bSYour Name 
281*5113495bSYour Name #endif   // REO_FLUSH_QUEUE
282