1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_QUEUE_H_ 27 #define _REO_FLUSH_QUEUE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 33 34 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 35 36 37 struct reo_flush_queue { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t flush_desc_addr_31_0 : 32; // [31:0] 41 uint32_t flush_desc_addr_39_32 : 8, // [7:0] 42 block_desc_addr_usage_after_flush : 1, // [8:8] 43 block_resource_index : 2, // [10:9] 44 reserved_2a : 21; // [31:11] 45 uint32_t reserved_3a : 32; // [31:0] 46 uint32_t reserved_4a : 32; // [31:0] 47 uint32_t reserved_5a : 32; // [31:0] 48 uint32_t reserved_6a : 32; // [31:0] 49 uint32_t reserved_7a : 32; // [31:0] 50 uint32_t reserved_8a : 32; // [31:0] 51 uint32_t tlv64_padding : 32; // [31:0] 52 #else 53 struct uniform_reo_cmd_header cmd_header; 54 uint32_t flush_desc_addr_31_0 : 32; // [31:0] 55 uint32_t reserved_2a : 21, // [31:11] 56 block_resource_index : 2, // [10:9] 57 block_desc_addr_usage_after_flush : 1, // [8:8] 58 flush_desc_addr_39_32 : 8; // [7:0] 59 uint32_t reserved_3a : 32; // [31:0] 60 uint32_t reserved_4a : 32; // [31:0] 61 uint32_t reserved_5a : 32; // [31:0] 62 uint32_t reserved_6a : 32; // [31:0] 63 uint32_t reserved_7a : 32; // [31:0] 64 uint32_t reserved_8a : 32; // [31:0] 65 uint32_t tlv64_padding : 32; // [31:0] 66 #endif 67 }; 68 69 70 /* Description CMD_HEADER 71 72 Consumer: REO 73 Producer: SW 74 75 Details for command execution tracking purposes. 76 */ 77 78 79 /* Description REO_CMD_NUMBER 80 81 Consumer: REO/SW/DEBUG 82 Producer: SW 83 84 This number can be used by SW to track, identify and link 85 the created commands with the command statusses 86 87 88 <legal all> 89 */ 90 91 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 92 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 93 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 94 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 95 96 97 /* Description REO_STATUS_REQUIRED 98 99 Consumer: REO 100 Producer: SW 101 102 <enum 0 NoStatus> REO does not need to generate a status 103 TLV for the execution of this command 104 <enum 1 StatusRequired> REO shall generate a status TLV 105 for the execution of this command 106 107 <legal all> 108 */ 109 110 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 111 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 112 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 113 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 114 115 116 /* Description RESERVED_0A 117 118 <legal 0> 119 */ 120 121 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 122 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 123 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 124 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 125 126 127 /* Description FLUSH_DESC_ADDR_31_0 128 129 Consumer: REO 130 Producer: SW 131 132 Address (lower 32 bits) of the descriptor to flush 133 <legal all> 134 */ 135 136 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 137 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 138 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 139 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 140 141 142 /* Description FLUSH_DESC_ADDR_39_32 143 144 Consumer: REO 145 Producer: SW 146 147 Address (upper 8 bits) of the descriptor to flush 148 <legal all> 149 */ 150 151 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 152 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 153 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 154 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 155 156 157 /* Description BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH 158 159 When set, REO shall not re-fetch this address till SW explicitly 160 unblocked this address 161 162 If the blocking resource was already used, this command 163 shall fail and an error is reported 164 165 <legal all> 166 */ 167 168 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 169 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 170 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 171 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 172 173 174 /* Description BLOCK_RESOURCE_INDEX 175 176 Field only valid when 'Block_desc_addr_usage_after_flush 177 ' is set. 178 179 Indicates which of the four blocking resources in REO will 180 be assigned for managing the blocking of this address. 181 <legal all> 182 */ 183 184 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 185 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 186 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 187 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 188 189 190 /* Description RESERVED_2A 191 192 <legal 0> 193 */ 194 195 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 196 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 197 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 198 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 199 200 201 /* Description RESERVED_3A 202 203 <legal 0> 204 */ 205 206 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 207 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 208 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 209 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 210 211 212 /* Description RESERVED_4A 213 214 <legal 0> 215 */ 216 217 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 218 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 219 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 220 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 221 222 223 /* Description RESERVED_5A 224 225 <legal 0> 226 */ 227 228 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 229 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 230 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 231 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 232 233 234 /* Description RESERVED_6A 235 236 <legal 0> 237 */ 238 239 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 240 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 241 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 242 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 243 244 245 /* Description RESERVED_7A 246 247 <legal 0> 248 */ 249 250 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 251 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 252 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 253 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 254 255 256 /* Description RESERVED_8A 257 258 <legal 0> 259 */ 260 261 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 262 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 263 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 264 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 265 266 267 /* Description TLV64_PADDING 268 269 Automatic DWORD padding inserted while converting TLV32 270 to TLV64 for 64 bit ARCH 271 <legal 0> 272 */ 273 274 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 275 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 276 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 277 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 278 279 280 281 #endif // REO_FLUSH_QUEUE 282