1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_QUEUE_STATUS_H_ 27 #define _REO_FLUSH_QUEUE_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 35 36 37 struct reo_flush_queue_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, // [0:0] 41 reserved_2a : 31; // [31:1] 42 uint32_t reserved_3a : 32; // [31:0] 43 uint32_t reserved_4a : 32; // [31:0] 44 uint32_t reserved_5a : 32; // [31:0] 45 uint32_t reserved_6a : 32; // [31:0] 46 uint32_t reserved_7a : 32; // [31:0] 47 uint32_t reserved_8a : 32; // [31:0] 48 uint32_t reserved_9a : 32; // [31:0] 49 uint32_t reserved_10a : 32; // [31:0] 50 uint32_t reserved_11a : 32; // [31:0] 51 uint32_t reserved_12a : 32; // [31:0] 52 uint32_t reserved_13a : 32; // [31:0] 53 uint32_t reserved_14a : 32; // [31:0] 54 uint32_t reserved_15a : 32; // [31:0] 55 uint32_t reserved_16a : 32; // [31:0] 56 uint32_t reserved_17a : 32; // [31:0] 57 uint32_t reserved_18a : 32; // [31:0] 58 uint32_t reserved_19a : 32; // [31:0] 59 uint32_t reserved_20a : 32; // [31:0] 60 uint32_t reserved_21a : 32; // [31:0] 61 uint32_t reserved_22a : 32; // [31:0] 62 uint32_t reserved_23a : 32; // [31:0] 63 uint32_t reserved_24a : 32; // [31:0] 64 uint32_t reserved_25a : 28, // [27:0] 65 looping_count : 4; // [31:28] 66 #else 67 struct uniform_reo_status_header status_header; 68 uint32_t reserved_2a : 31, // [31:1] 69 error_detected : 1; // [0:0] 70 uint32_t reserved_3a : 32; // [31:0] 71 uint32_t reserved_4a : 32; // [31:0] 72 uint32_t reserved_5a : 32; // [31:0] 73 uint32_t reserved_6a : 32; // [31:0] 74 uint32_t reserved_7a : 32; // [31:0] 75 uint32_t reserved_8a : 32; // [31:0] 76 uint32_t reserved_9a : 32; // [31:0] 77 uint32_t reserved_10a : 32; // [31:0] 78 uint32_t reserved_11a : 32; // [31:0] 79 uint32_t reserved_12a : 32; // [31:0] 80 uint32_t reserved_13a : 32; // [31:0] 81 uint32_t reserved_14a : 32; // [31:0] 82 uint32_t reserved_15a : 32; // [31:0] 83 uint32_t reserved_16a : 32; // [31:0] 84 uint32_t reserved_17a : 32; // [31:0] 85 uint32_t reserved_18a : 32; // [31:0] 86 uint32_t reserved_19a : 32; // [31:0] 87 uint32_t reserved_20a : 32; // [31:0] 88 uint32_t reserved_21a : 32; // [31:0] 89 uint32_t reserved_22a : 32; // [31:0] 90 uint32_t reserved_23a : 32; // [31:0] 91 uint32_t reserved_24a : 32; // [31:0] 92 uint32_t looping_count : 4, // [31:28] 93 reserved_25a : 28; // [27:0] 94 #endif 95 }; 96 97 98 /* Description STATUS_HEADER 99 100 Consumer: SW 101 Producer: REO 102 103 Details that can link this status with the original command. 104 It also contains info on how long REO took to execute this 105 command. 106 */ 107 108 109 /* Description REO_STATUS_NUMBER 110 111 Consumer: SW , DEBUG 112 Producer: REO 113 114 The value in this field is equal to value of the 'REO_CMD_Number' 115 field the REO command 116 117 This field helps to correlate the statuses with the REO 118 commands. 119 120 <legal all> 121 */ 122 123 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 124 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 125 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 126 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 127 128 129 /* Description CMD_EXECUTION_TIME 130 131 Consumer: DEBUG 132 Producer: REO 133 134 The amount of time REO took to excecute the command. Note 135 that this time does not include the duration of the command 136 waiting in the command ring, before the execution started. 137 138 139 In us. 140 141 <legal all> 142 */ 143 144 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 145 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 146 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 147 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 148 149 150 /* Description REO_CMD_EXECUTION_STATUS 151 152 Consumer: DEBUG 153 Producer: REO 154 155 Execution status of the command. 156 157 <enum 0 reo_successful_execution> Command has successfully 158 be executed 159 <enum 1 reo_blocked_execution> Command could not be executed 160 as the queue or cache was blocked 161 <enum 2 reo_failed_execution> Command has encountered problems 162 when executing, like the queue descriptor not being valid. 163 None of the status fields in the entire STATUS TLV are valid. 164 165 <enum 3 reo_resource_blocked> Command is NOT executed because 166 one or more descriptors were blocked. This is SW programming 167 mistake. 168 None of the status fields in the entire STATUS TLV are valid. 169 170 171 <legal 0-3> 172 */ 173 174 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 175 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 176 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 177 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 178 179 180 /* Description RESERVED_0A 181 182 <legal 0> 183 */ 184 185 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 186 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 187 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 188 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 189 190 191 /* Description TIMESTAMP 192 193 Timestamp at the moment that this status report is written. 194 195 196 <legal all> 197 */ 198 199 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 200 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 201 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 202 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 203 204 205 /* Description ERROR_DETECTED 206 207 Status of the blocking resource 208 0: No error has been detected while executing this command 209 210 1: Error detected: The resource to be used for blocking 211 was already in use. 212 */ 213 214 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 215 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 216 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 217 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 218 219 220 /* Description RESERVED_2A 221 222 <legal 0> 223 */ 224 225 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 226 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 227 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 228 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe 229 230 231 /* Description RESERVED_3A 232 233 <legal 0> 234 */ 235 236 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 237 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 238 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 239 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 240 241 242 /* Description RESERVED_4A 243 244 <legal 0> 245 */ 246 247 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 248 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 249 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 250 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 251 252 253 /* Description RESERVED_5A 254 255 <legal 0> 256 */ 257 258 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 259 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 260 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 261 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 262 263 264 /* Description RESERVED_6A 265 266 <legal 0> 267 */ 268 269 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 270 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 271 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 272 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 273 274 275 /* Description RESERVED_7A 276 277 <legal 0> 278 */ 279 280 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 281 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 282 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 283 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 284 285 286 /* Description RESERVED_8A 287 288 <legal 0> 289 */ 290 291 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 292 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 293 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 294 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 295 296 297 /* Description RESERVED_9A 298 299 <legal 0> 300 */ 301 302 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 303 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 304 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 305 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 306 307 308 /* Description RESERVED_10A 309 310 <legal 0> 311 */ 312 313 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 314 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 315 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 316 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 317 318 319 /* Description RESERVED_11A 320 321 <legal 0> 322 */ 323 324 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 325 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 326 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 327 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 328 329 330 /* Description RESERVED_12A 331 332 <legal 0> 333 */ 334 335 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 336 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 337 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 338 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 339 340 341 /* Description RESERVED_13A 342 343 <legal 0> 344 */ 345 346 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 347 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 348 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 349 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 350 351 352 /* Description RESERVED_14A 353 354 <legal 0> 355 */ 356 357 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 358 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 359 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 360 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 361 362 363 /* Description RESERVED_15A 364 365 <legal 0> 366 */ 367 368 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 369 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 370 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 371 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 372 373 374 /* Description RESERVED_16A 375 376 <legal 0> 377 */ 378 379 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 380 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 381 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 382 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 383 384 385 /* Description RESERVED_17A 386 387 <legal 0> 388 */ 389 390 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 391 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 392 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 393 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 394 395 396 /* Description RESERVED_18A 397 398 <legal 0> 399 */ 400 401 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 402 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 403 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 404 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 405 406 407 /* Description RESERVED_19A 408 409 <legal 0> 410 */ 411 412 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 413 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 414 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 415 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 416 417 418 /* Description RESERVED_20A 419 420 <legal 0> 421 */ 422 423 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 424 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 425 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 426 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 427 428 429 /* Description RESERVED_21A 430 431 <legal 0> 432 */ 433 434 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 435 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 436 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 437 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 438 439 440 /* Description RESERVED_22A 441 442 <legal 0> 443 */ 444 445 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 446 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 447 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 448 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 449 450 451 /* Description RESERVED_23A 452 453 <legal 0> 454 */ 455 456 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 457 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 458 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 459 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 460 461 462 /* Description RESERVED_24A 463 464 <legal 0> 465 */ 466 467 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 468 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 469 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 470 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 471 472 473 /* Description RESERVED_25A 474 475 <legal 0> 476 */ 477 478 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 479 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 480 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 481 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 482 483 484 /* Description LOOPING_COUNT 485 486 A count value that indicates the number of times the producer 487 of entries into this Ring has looped around the ring. 488 At initialization time, this value is set to 0. On the first 489 loop, this value is set to 1. After the max value is reached 490 allowed by the number of bits for this field, the count 491 value continues with 0 again. 492 493 In case SW is the consumer of the ring entries, it can use 494 this field to figure out up to where the producer of entries 495 has created new entries. This eliminates the need to check 496 where the "head pointer' of the ring is located once the 497 SW starts processing an interrupt indicating that new entries 498 have been put into this ring... 499 500 Also note that SW if it wants only needs to look at the 501 LSB bit of this count value. 502 <legal all> 503 */ 504 505 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 506 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 507 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 508 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 509 510 511 512 #endif // REO_FLUSH_QUEUE_STATUS 513