xref: /wlan-driver/fw-api/hw/qca5332/reo_flush_timeout_list.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name 
20*5113495bSYour Name 
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name 
24*5113495bSYour Name 
25*5113495bSYour Name 
26*5113495bSYour Name #ifndef _REO_FLUSH_TIMEOUT_LIST_H_
27*5113495bSYour Name #define _REO_FLUSH_TIMEOUT_LIST_H_
28*5113495bSYour Name #if !defined(__ASSEMBLER__)
29*5113495bSYour Name #endif
30*5113495bSYour Name 
31*5113495bSYour Name #include "uniform_reo_cmd_header.h"
32*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
33*5113495bSYour Name 
34*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
35*5113495bSYour Name 
36*5113495bSYour Name 
37*5113495bSYour Name struct reo_flush_timeout_list {
38*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
40*5113495bSYour Name              uint32_t ac_timout_list                                          :  2, // [1:0]
41*5113495bSYour Name                       reserved_1                                              : 30; // [31:2]
42*5113495bSYour Name              uint32_t minimum_release_desc_count                              : 16, // [15:0]
43*5113495bSYour Name                       minimum_forward_buf_count                               : 16; // [31:16]
44*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
45*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
46*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
47*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
48*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
49*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
50*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
51*5113495bSYour Name #else
52*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
53*5113495bSYour Name              uint32_t reserved_1                                              : 30, // [31:2]
54*5113495bSYour Name                       ac_timout_list                                          :  2; // [1:0]
55*5113495bSYour Name              uint32_t minimum_forward_buf_count                               : 16, // [31:16]
56*5113495bSYour Name                       minimum_release_desc_count                              : 16; // [15:0]
57*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
58*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
59*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
60*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
61*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
62*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
63*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
64*5113495bSYour Name #endif
65*5113495bSYour Name };
66*5113495bSYour Name 
67*5113495bSYour Name 
68*5113495bSYour Name /* Description		CMD_HEADER
69*5113495bSYour Name 
70*5113495bSYour Name 			Consumer: REO
71*5113495bSYour Name 			Producer: SW
72*5113495bSYour Name 
73*5113495bSYour Name 			Details for command execution tracking purposes.
74*5113495bSYour Name */
75*5113495bSYour Name 
76*5113495bSYour Name 
77*5113495bSYour Name /* Description		REO_CMD_NUMBER
78*5113495bSYour Name 
79*5113495bSYour Name 			Consumer: REO/SW/DEBUG
80*5113495bSYour Name 			Producer: SW
81*5113495bSYour Name 
82*5113495bSYour Name 			This number can be used by SW to track, identify and link
83*5113495bSYour Name 			 the created commands with the command statusses
84*5113495bSYour Name 
85*5113495bSYour Name 
86*5113495bSYour Name 			<legal all>
87*5113495bSYour Name */
88*5113495bSYour Name 
89*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET                     0x0000000000000000
90*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB                        0
91*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB                        15
92*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK                       0x000000000000ffff
93*5113495bSYour Name 
94*5113495bSYour Name 
95*5113495bSYour Name /* Description		REO_STATUS_REQUIRED
96*5113495bSYour Name 
97*5113495bSYour Name 			Consumer: REO
98*5113495bSYour Name 			Producer: SW
99*5113495bSYour Name 
100*5113495bSYour Name 			<enum 0 NoStatus> REO does not need to generate a status
101*5113495bSYour Name 			 TLV for the execution of this command
102*5113495bSYour Name 			<enum 1 StatusRequired> REO shall generate a status TLV
103*5113495bSYour Name 			for the execution of this command
104*5113495bSYour Name 
105*5113495bSYour Name 			<legal all>
106*5113495bSYour Name */
107*5113495bSYour Name 
108*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                0x0000000000000000
109*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB                   16
110*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB                   16
111*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK                  0x0000000000010000
112*5113495bSYour Name 
113*5113495bSYour Name 
114*5113495bSYour Name /* Description		RESERVED_0A
115*5113495bSYour Name 
116*5113495bSYour Name 			<legal 0>
117*5113495bSYour Name */
118*5113495bSYour Name 
119*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET                        0x0000000000000000
120*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB                           17
121*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB                           31
122*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK                          0x00000000fffe0000
123*5113495bSYour Name 
124*5113495bSYour Name 
125*5113495bSYour Name /* Description		AC_TIMOUT_LIST
126*5113495bSYour Name 
127*5113495bSYour Name 			Consumer: REO
128*5113495bSYour Name 			Producer: SW
129*5113495bSYour Name 
130*5113495bSYour Name 			The AC_timeout list to be used for this command
131*5113495bSYour Name 			<legal all>
132*5113495bSYour Name */
133*5113495bSYour Name 
134*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET                                0x0000000000000000
135*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB                                   32
136*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB                                   33
137*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK                                  0x0000000300000000
138*5113495bSYour Name 
139*5113495bSYour Name 
140*5113495bSYour Name /* Description		RESERVED_1
141*5113495bSYour Name 
142*5113495bSYour Name 			<legal 0>
143*5113495bSYour Name */
144*5113495bSYour Name 
145*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET                                    0x0000000000000000
146*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB                                       34
147*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB                                       63
148*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK                                      0xfffffffc00000000
149*5113495bSYour Name 
150*5113495bSYour Name 
151*5113495bSYour Name /* Description		MINIMUM_RELEASE_DESC_COUNT
152*5113495bSYour Name 
153*5113495bSYour Name 			Consumer: REO
154*5113495bSYour Name 			Producer: SW
155*5113495bSYour Name 
156*5113495bSYour Name 			The minimum number of link descriptors requested to be released.
157*5113495bSYour Name 			If set to 0, only buffer release counts seems to be important...
158*5113495bSYour Name 			When set to very high value, likely the entire timeout list
159*5113495bSYour Name 			 will be exhausted before this count is reached or maybe
160*5113495bSYour Name 			 this count will not get reached. REO however will stop
161*5113495bSYour Name 			here as it can not do anything else.
162*5113495bSYour Name 
163*5113495bSYour Name 			When both this field and field Minimum_forward_buf_count
164*5113495bSYour Name 			 are > 0, REO needs to meet both requirements. When both
165*5113495bSYour Name 			 entries are 0 (which should be a programming error), REO
166*5113495bSYour Name 			 does not need to do anything.
167*5113495bSYour Name 
168*5113495bSYour Name 			Note that this includes counts of MPDU link Desc as well
169*5113495bSYour Name 			 as MSDU link Desc. Where the count of MSDU link Desc is
170*5113495bSYour Name 			 not known to REO it's approximated by deriving from MSDU
171*5113495bSYour Name 			 count
172*5113495bSYour Name 			<legal all>
173*5113495bSYour Name */
174*5113495bSYour Name 
175*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET                    0x0000000000000008
176*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB                       0
177*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB                       15
178*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK                      0x000000000000ffff
179*5113495bSYour Name 
180*5113495bSYour Name 
181*5113495bSYour Name /* Description		MINIMUM_FORWARD_BUF_COUNT
182*5113495bSYour Name 
183*5113495bSYour Name 			Consumer: REO
184*5113495bSYour Name 			Producer: SW
185*5113495bSYour Name 
186*5113495bSYour Name 			The minimum number of buffer descriptors requested to be
187*5113495bSYour Name 			 passed on to the REO destination rings.
188*5113495bSYour Name 
189*5113495bSYour Name 			If set to 0, only descriptor release counts seems to be
190*5113495bSYour Name 			important...
191*5113495bSYour Name 
192*5113495bSYour Name 			When set to very high value, likely the entire timeout list
193*5113495bSYour Name 			 will be exhausted before this count is reached or maybe
194*5113495bSYour Name 			 this count will not get reached. REO however will stop
195*5113495bSYour Name 			here as it can not do anything else.
196*5113495bSYour Name 
197*5113495bSYour Name 			Note that REO does not know the exact buffer count. This
198*5113495bSYour Name 			 can be approximated by using the MSDU_COUNT
199*5113495bSYour Name 			<legal all>
200*5113495bSYour Name */
201*5113495bSYour Name 
202*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET                     0x0000000000000008
203*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB                        16
204*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB                        31
205*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK                       0x00000000ffff0000
206*5113495bSYour Name 
207*5113495bSYour Name 
208*5113495bSYour Name /* Description		RESERVED_3A
209*5113495bSYour Name 
210*5113495bSYour Name 			<legal 0>
211*5113495bSYour Name */
212*5113495bSYour Name 
213*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET                                   0x0000000000000008
214*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB                                      32
215*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB                                      63
216*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK                                     0xffffffff00000000
217*5113495bSYour Name 
218*5113495bSYour Name 
219*5113495bSYour Name /* Description		RESERVED_4A
220*5113495bSYour Name 
221*5113495bSYour Name 			<legal 0>
222*5113495bSYour Name */
223*5113495bSYour Name 
224*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET                                   0x0000000000000010
225*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB                                      0
226*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB                                      31
227*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK                                     0x00000000ffffffff
228*5113495bSYour Name 
229*5113495bSYour Name 
230*5113495bSYour Name /* Description		RESERVED_5A
231*5113495bSYour Name 
232*5113495bSYour Name 			<legal 0>
233*5113495bSYour Name */
234*5113495bSYour Name 
235*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET                                   0x0000000000000010
236*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB                                      32
237*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB                                      63
238*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK                                     0xffffffff00000000
239*5113495bSYour Name 
240*5113495bSYour Name 
241*5113495bSYour Name /* Description		RESERVED_6A
242*5113495bSYour Name 
243*5113495bSYour Name 			<legal 0>
244*5113495bSYour Name */
245*5113495bSYour Name 
246*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET                                   0x0000000000000018
247*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB                                      0
248*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB                                      31
249*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK                                     0x00000000ffffffff
250*5113495bSYour Name 
251*5113495bSYour Name 
252*5113495bSYour Name /* Description		RESERVED_7A
253*5113495bSYour Name 
254*5113495bSYour Name 			<legal 0>
255*5113495bSYour Name */
256*5113495bSYour Name 
257*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET                                   0x0000000000000018
258*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB                                      32
259*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB                                      63
260*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK                                     0xffffffff00000000
261*5113495bSYour Name 
262*5113495bSYour Name 
263*5113495bSYour Name /* Description		RESERVED_8A
264*5113495bSYour Name 
265*5113495bSYour Name 			<legal 0>
266*5113495bSYour Name */
267*5113495bSYour Name 
268*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET                                   0x0000000000000020
269*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB                                      0
270*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB                                      31
271*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK                                     0x00000000ffffffff
272*5113495bSYour Name 
273*5113495bSYour Name 
274*5113495bSYour Name /* Description		TLV64_PADDING
275*5113495bSYour Name 
276*5113495bSYour Name 			Automatic DWORD padding inserted while converting TLV32
277*5113495bSYour Name 			to TLV64 for 64 bit ARCH
278*5113495bSYour Name 			<legal 0>
279*5113495bSYour Name */
280*5113495bSYour Name 
281*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET                                 0x0000000000000020
282*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB                                    32
283*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB                                    63
284*5113495bSYour Name #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK                                   0xffffffff00000000
285*5113495bSYour Name 
286*5113495bSYour Name 
287*5113495bSYour Name 
288*5113495bSYour Name #endif   // REO_FLUSH_TIMEOUT_LIST
289