1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_GET_QUEUE_STATS_H_ 27 #define _REO_GET_QUEUE_STATS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 33 34 #define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 35 36 37 struct reo_get_queue_stats { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 41 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 42 clear_stats : 1, // [8:8] 43 reserved_2a : 23; // [31:9] 44 uint32_t reserved_3a : 32; // [31:0] 45 uint32_t reserved_4a : 32; // [31:0] 46 uint32_t reserved_5a : 32; // [31:0] 47 uint32_t reserved_6a : 32; // [31:0] 48 uint32_t reserved_7a : 32; // [31:0] 49 uint32_t reserved_8a : 32; // [31:0] 50 uint32_t tlv64_padding : 32; // [31:0] 51 #else 52 struct uniform_reo_cmd_header cmd_header; 53 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 54 uint32_t reserved_2a : 23, // [31:9] 55 clear_stats : 1, // [8:8] 56 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 57 uint32_t reserved_3a : 32; // [31:0] 58 uint32_t reserved_4a : 32; // [31:0] 59 uint32_t reserved_5a : 32; // [31:0] 60 uint32_t reserved_6a : 32; // [31:0] 61 uint32_t reserved_7a : 32; // [31:0] 62 uint32_t reserved_8a : 32; // [31:0] 63 uint32_t tlv64_padding : 32; // [31:0] 64 #endif 65 }; 66 67 68 /* Description CMD_HEADER 69 70 Consumer: REO 71 Producer: SW 72 73 Details for command execution tracking purposes. 74 */ 75 76 77 /* Description REO_CMD_NUMBER 78 79 Consumer: REO/SW/DEBUG 80 Producer: SW 81 82 This number can be used by SW to track, identify and link 83 the created commands with the command statusses 84 85 86 <legal all> 87 */ 88 89 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 90 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 91 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 92 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 93 94 95 /* Description REO_STATUS_REQUIRED 96 97 Consumer: REO 98 Producer: SW 99 100 <enum 0 NoStatus> REO does not need to generate a status 101 TLV for the execution of this command 102 <enum 1 StatusRequired> REO shall generate a status TLV 103 for the execution of this command 104 105 <legal all> 106 */ 107 108 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 109 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 110 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 111 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 112 113 114 /* Description RESERVED_0A 115 116 <legal 0> 117 */ 118 119 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 120 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 121 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 122 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 123 124 125 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 126 127 Consumer: REO 128 Producer: SW 129 130 Address (lower 32 bits) of the REO queue descriptor 131 <legal all> 132 */ 133 134 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 135 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 136 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 137 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 138 139 140 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 141 142 Consumer: REO 143 Producer: SW 144 145 Address (upper 8 bits) of the REO queue descriptor 146 <legal all> 147 */ 148 149 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 150 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 151 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 152 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 153 154 155 /* Description CLEAR_STATS 156 157 Clear stat settings.... 158 159 <enum 0 no_clear> Do NOT clear the stats after generating 160 the status 161 <enum 1 clear_the_stats> Clear the stats after generating 162 the status. 163 164 The stats actually cleared are: 165 Timeout_count 166 Forward_due_to_bar_count 167 Duplicate_count 168 Frames_in_order_count 169 BAR_received_count 170 MPDU_Frames_processed_count 171 MSDU_Frames_processed_count 172 Total_processed_byte_count 173 Late_receive_MPDU_count 174 window_jump_2k 175 Hole_count 176 <legal 0-1> 177 */ 178 179 #define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 180 #define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 181 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 182 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 183 184 185 /* Description RESERVED_2A 186 187 <legal 0> 188 */ 189 190 #define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 191 #define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 192 #define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 193 #define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 194 195 196 /* Description RESERVED_3A 197 198 <legal 0> 199 */ 200 201 #define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 202 #define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 203 #define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 204 #define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 205 206 207 /* Description RESERVED_4A 208 209 <legal 0> 210 */ 211 212 #define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 213 #define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 214 #define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 215 #define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff 216 217 218 /* Description RESERVED_5A 219 220 <legal 0> 221 */ 222 223 #define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 224 #define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 225 #define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 226 #define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 227 228 229 /* Description RESERVED_6A 230 231 <legal 0> 232 */ 233 234 #define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 235 #define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 236 #define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 237 #define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff 238 239 240 /* Description RESERVED_7A 241 242 <legal 0> 243 */ 244 245 #define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 246 #define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 247 #define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 248 #define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 249 250 251 /* Description RESERVED_8A 252 253 <legal 0> 254 */ 255 256 #define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 257 #define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 258 #define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 259 #define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff 260 261 262 /* Description TLV64_PADDING 263 264 Automatic DWORD padding inserted while converting TLV32 265 to TLV64 for 64 bit ARCH 266 <legal 0> 267 */ 268 269 #define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 270 #define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 271 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 272 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 273 274 275 276 #endif // REO_GET_QUEUE_STATS 277