1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_UNBLOCK_CACHE_H_ 27 #define _REO_UNBLOCK_CACHE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 33 34 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 35 36 37 struct reo_unblock_cache { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t unblock_type : 1, // [0:0] 41 cache_block_resource_index : 2, // [2:1] 42 reserved_1a : 29; // [31:3] 43 uint32_t reserved_2a : 32; // [31:0] 44 uint32_t reserved_3a : 32; // [31:0] 45 uint32_t reserved_4a : 32; // [31:0] 46 uint32_t reserved_5a : 32; // [31:0] 47 uint32_t reserved_6a : 32; // [31:0] 48 uint32_t reserved_7a : 32; // [31:0] 49 uint32_t reserved_8a : 32; // [31:0] 50 uint32_t tlv64_padding : 32; // [31:0] 51 #else 52 struct uniform_reo_cmd_header cmd_header; 53 uint32_t reserved_1a : 29, // [31:3] 54 cache_block_resource_index : 2, // [2:1] 55 unblock_type : 1; // [0:0] 56 uint32_t reserved_2a : 32; // [31:0] 57 uint32_t reserved_3a : 32; // [31:0] 58 uint32_t reserved_4a : 32; // [31:0] 59 uint32_t reserved_5a : 32; // [31:0] 60 uint32_t reserved_6a : 32; // [31:0] 61 uint32_t reserved_7a : 32; // [31:0] 62 uint32_t reserved_8a : 32; // [31:0] 63 uint32_t tlv64_padding : 32; // [31:0] 64 #endif 65 }; 66 67 68 /* Description CMD_HEADER 69 70 Consumer: REO 71 Producer: SW 72 73 Details for command execution tracking purposes. 74 */ 75 76 77 /* Description REO_CMD_NUMBER 78 79 Consumer: REO/SW/DEBUG 80 Producer: SW 81 82 This number can be used by SW to track, identify and link 83 the created commands with the command statusses 84 85 86 <legal all> 87 */ 88 89 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 90 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 91 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 92 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 93 94 95 /* Description REO_STATUS_REQUIRED 96 97 Consumer: REO 98 Producer: SW 99 100 <enum 0 NoStatus> REO does not need to generate a status 101 TLV for the execution of this command 102 <enum 1 StatusRequired> REO shall generate a status TLV 103 for the execution of this command 104 105 <legal all> 106 */ 107 108 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 109 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 110 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 111 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 112 113 114 /* Description RESERVED_0A 115 116 <legal 0> 117 */ 118 119 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 120 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 121 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 122 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 123 124 125 /* Description UNBLOCK_TYPE 126 127 Unblock type 128 129 <enum 0 unblock_resource_index> Unblock a block resource, 130 whose index is given in field 'cache_block_resource_index'. 131 132 If the indicated blocking resource is not in use (=> not 133 blocking an address at the moment), the command status 134 will indicate an error. 135 136 <enum 1 unblock_cache> The entire cache usage is unblocked. 137 138 If the entire cache is not in a blocked mode at the moment 139 this command is received, the command status will indicate 140 an error. 141 Note that unlocking the "entire cache" has no changes to 142 the current settings of the blocking resource settings 143 144 <legal all> 145 */ 146 147 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 148 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 149 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 150 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 151 152 153 /* Description CACHE_BLOCK_RESOURCE_INDEX 154 155 Field not valid when field Unblock_type is set to unblock_cache. 156 157 158 Indicates which of the four blocking resources in REO should 159 be released from blocking a (descriptor) address. 160 <legal all> 161 */ 162 163 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 164 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 165 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 166 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 167 168 169 /* Description RESERVED_1A 170 171 <legal 0> 172 */ 173 174 #define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 175 #define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 176 #define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 177 #define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 178 179 180 /* Description RESERVED_2A 181 182 <legal 0> 183 */ 184 185 #define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 186 #define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 187 #define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 188 #define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff 189 190 191 /* Description RESERVED_3A 192 193 <legal 0> 194 */ 195 196 #define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 197 #define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 198 #define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 199 #define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 200 201 202 /* Description RESERVED_4A 203 204 <legal 0> 205 */ 206 207 #define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 208 #define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 209 #define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 210 #define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 211 212 213 /* Description RESERVED_5A 214 215 <legal 0> 216 */ 217 218 #define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 219 #define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 220 #define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 221 #define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 222 223 224 /* Description RESERVED_6A 225 226 <legal 0> 227 */ 228 229 #define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 230 #define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 231 #define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 232 #define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 233 234 235 /* Description RESERVED_7A 236 237 <legal 0> 238 */ 239 240 #define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 241 #define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 242 #define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 243 #define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 244 245 246 /* Description RESERVED_8A 247 248 <legal 0> 249 */ 250 251 #define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 252 #define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 253 #define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 254 #define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 255 256 257 /* Description TLV64_PADDING 258 259 Automatic DWORD padding inserted while converting TLV32 260 to TLV64 for 64 bit ARCH 261 <legal 0> 262 */ 263 264 #define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 265 #define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 266 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 267 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 268 269 270 271 #endif // REO_UNBLOCK_CACHE 272