1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 27 #define _REO_UPDATE_RX_REO_QUEUE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 33 34 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 35 36 37 struct reo_update_rx_reo_queue { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 41 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 42 update_receive_queue_number : 1, // [8:8] 43 update_vld : 1, // [9:9] 44 update_associated_link_descriptor_counter : 1, // [10:10] 45 update_disable_duplicate_detection : 1, // [11:11] 46 update_soft_reorder_enable : 1, // [12:12] 47 update_ac : 1, // [13:13] 48 update_bar : 1, // [14:14] 49 update_rty : 1, // [15:15] 50 update_chk_2k_mode : 1, // [16:16] 51 update_oor_mode : 1, // [17:17] 52 update_ba_window_size : 1, // [18:18] 53 update_pn_check_needed : 1, // [19:19] 54 update_pn_shall_be_even : 1, // [20:20] 55 update_pn_shall_be_uneven : 1, // [21:21] 56 update_pn_handling_enable : 1, // [22:22] 57 update_pn_size : 1, // [23:23] 58 update_ignore_ampdu_flag : 1, // [24:24] 59 update_svld : 1, // [25:25] 60 update_ssn : 1, // [26:26] 61 update_seq_2k_error_detected_flag : 1, // [27:27] 62 update_pn_error_detected_flag : 1, // [28:28] 63 update_pn_valid : 1, // [29:29] 64 update_pn : 1, // [30:30] 65 clear_stat_counters : 1; // [31:31] 66 uint32_t receive_queue_number : 16, // [15:0] 67 vld : 1, // [16:16] 68 associated_link_descriptor_counter : 2, // [18:17] 69 disable_duplicate_detection : 1, // [19:19] 70 soft_reorder_enable : 1, // [20:20] 71 ac : 2, // [22:21] 72 bar : 1, // [23:23] 73 rty : 1, // [24:24] 74 chk_2k_mode : 1, // [25:25] 75 oor_mode : 1, // [26:26] 76 pn_check_needed : 1, // [27:27] 77 pn_shall_be_even : 1, // [28:28] 78 pn_shall_be_uneven : 1, // [29:29] 79 pn_handling_enable : 1, // [30:30] 80 ignore_ampdu_flag : 1; // [31:31] 81 uint32_t ba_window_size : 10, // [9:0] 82 pn_size : 2, // [11:10] 83 svld : 1, // [12:12] 84 ssn : 12, // [24:13] 85 seq_2k_error_detected_flag : 1, // [25:25] 86 pn_error_detected_flag : 1, // [26:26] 87 pn_valid : 1, // [27:27] 88 flush_from_cache : 1, // [28:28] 89 reserved_4a : 3; // [31:29] 90 uint32_t pn_31_0 : 32; // [31:0] 91 uint32_t pn_63_32 : 32; // [31:0] 92 uint32_t pn_95_64 : 32; // [31:0] 93 uint32_t pn_127_96 : 32; // [31:0] 94 uint32_t tlv64_padding : 32; // [31:0] 95 #else 96 struct uniform_reo_cmd_header cmd_header; 97 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 98 uint32_t clear_stat_counters : 1, // [31:31] 99 update_pn : 1, // [30:30] 100 update_pn_valid : 1, // [29:29] 101 update_pn_error_detected_flag : 1, // [28:28] 102 update_seq_2k_error_detected_flag : 1, // [27:27] 103 update_ssn : 1, // [26:26] 104 update_svld : 1, // [25:25] 105 update_ignore_ampdu_flag : 1, // [24:24] 106 update_pn_size : 1, // [23:23] 107 update_pn_handling_enable : 1, // [22:22] 108 update_pn_shall_be_uneven : 1, // [21:21] 109 update_pn_shall_be_even : 1, // [20:20] 110 update_pn_check_needed : 1, // [19:19] 111 update_ba_window_size : 1, // [18:18] 112 update_oor_mode : 1, // [17:17] 113 update_chk_2k_mode : 1, // [16:16] 114 update_rty : 1, // [15:15] 115 update_bar : 1, // [14:14] 116 update_ac : 1, // [13:13] 117 update_soft_reorder_enable : 1, // [12:12] 118 update_disable_duplicate_detection : 1, // [11:11] 119 update_associated_link_descriptor_counter : 1, // [10:10] 120 update_vld : 1, // [9:9] 121 update_receive_queue_number : 1, // [8:8] 122 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 123 uint32_t ignore_ampdu_flag : 1, // [31:31] 124 pn_handling_enable : 1, // [30:30] 125 pn_shall_be_uneven : 1, // [29:29] 126 pn_shall_be_even : 1, // [28:28] 127 pn_check_needed : 1, // [27:27] 128 oor_mode : 1, // [26:26] 129 chk_2k_mode : 1, // [25:25] 130 rty : 1, // [24:24] 131 bar : 1, // [23:23] 132 ac : 2, // [22:21] 133 soft_reorder_enable : 1, // [20:20] 134 disable_duplicate_detection : 1, // [19:19] 135 associated_link_descriptor_counter : 2, // [18:17] 136 vld : 1, // [16:16] 137 receive_queue_number : 16; // [15:0] 138 uint32_t reserved_4a : 3, // [31:29] 139 flush_from_cache : 1, // [28:28] 140 pn_valid : 1, // [27:27] 141 pn_error_detected_flag : 1, // [26:26] 142 seq_2k_error_detected_flag : 1, // [25:25] 143 ssn : 12, // [24:13] 144 svld : 1, // [12:12] 145 pn_size : 2, // [11:10] 146 ba_window_size : 10; // [9:0] 147 uint32_t pn_31_0 : 32; // [31:0] 148 uint32_t pn_63_32 : 32; // [31:0] 149 uint32_t pn_95_64 : 32; // [31:0] 150 uint32_t pn_127_96 : 32; // [31:0] 151 uint32_t tlv64_padding : 32; // [31:0] 152 #endif 153 }; 154 155 156 /* Description CMD_HEADER 157 158 Consumer: REO 159 Producer: SW 160 161 Details for command execution tracking purposes. 162 */ 163 164 165 /* Description REO_CMD_NUMBER 166 167 Consumer: REO/SW/DEBUG 168 Producer: SW 169 170 This number can be used by SW to track, identify and link 171 the created commands with the command statusses 172 173 174 <legal all> 175 */ 176 177 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 178 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 179 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 180 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 181 182 183 /* Description REO_STATUS_REQUIRED 184 185 Consumer: REO 186 Producer: SW 187 188 <enum 0 NoStatus> REO does not need to generate a status 189 TLV for the execution of this command 190 <enum 1 StatusRequired> REO shall generate a status TLV 191 for the execution of this command 192 193 <legal all> 194 */ 195 196 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 197 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 198 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 199 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 200 201 202 /* Description RESERVED_0A 203 204 <legal 0> 205 */ 206 207 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 208 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 209 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 210 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 211 212 213 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 214 215 Consumer: REO 216 Producer: SW 217 218 Address (lower 32 bits) of the REO queue descriptor 219 <legal all> 220 */ 221 222 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 223 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 224 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 225 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 226 227 228 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 229 230 Consumer: REO 231 Producer: SW 232 233 Address (upper 8 bits) of the REO queue descriptor 234 <legal all> 235 */ 236 237 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 238 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 239 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 240 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 241 242 243 /* Description UPDATE_RECEIVE_QUEUE_NUMBER 244 245 Consumer: REO 246 Producer: SW 247 When set, receive_queue_number from this command will be 248 updated in the descriptor. 249 <legal all> 250 */ 251 252 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 253 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 254 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 255 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 256 257 258 /* Description UPDATE_VLD 259 260 Consumer: REO 261 Producer: SW 262 263 When clear, REO will NOT update the VLD bit setting. For 264 this setting, SW MUST set the Flush_from_cache bit in this 265 command. 266 267 When set, VLD from this command will be updated in the descriptor. 268 269 <legal all> 270 */ 271 272 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 273 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 274 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 275 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 276 277 278 /* Description UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 279 280 Consumer: REO 281 Producer: SW 282 When set, Associated_link_descriptor_counter from this command 283 will be updated in the descriptor. 284 <legal all> 285 */ 286 287 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 288 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 289 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 290 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 291 292 293 /* Description UPDATE_DISABLE_DUPLICATE_DETECTION 294 295 Consumer: REO 296 Producer: SW 297 When set, Disable_duplicate_detection from this command 298 will be updated in the descriptor. 299 <legal all> 300 */ 301 302 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 303 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 304 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 305 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 306 307 308 /* Description UPDATE_SOFT_REORDER_ENABLE 309 310 Consumer: REO 311 Producer: SW 312 When set, Soft_reorder_enable from this command will be 313 updated in the descriptor. 314 <legal all> 315 */ 316 317 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 318 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 319 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 320 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 321 322 323 /* Description UPDATE_AC 324 325 Consumer: REO 326 Producer: SW 327 When set, AC from this command will be updated in the descriptor. 328 329 <legal all> 330 */ 331 332 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 333 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 334 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 335 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 336 337 338 /* Description UPDATE_BAR 339 340 Consumer: REO 341 Producer: SW 342 When set, BAR from this command will be updated in the descriptor. 343 344 <legal all> 345 */ 346 347 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 348 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 349 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 350 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 351 352 353 /* Description UPDATE_RTY 354 355 Consumer: REO 356 Producer: SW 357 When set, RTY from this command will be updated in the descriptor. 358 359 <legal all> 360 */ 361 362 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 363 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 364 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 365 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 366 367 368 /* Description UPDATE_CHK_2K_MODE 369 370 Consumer: REO 371 Producer: SW 372 When set, Chk_2k_mode from this command will be updated 373 in the descriptor. 374 <legal all> 375 */ 376 377 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 378 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 379 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 380 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 381 382 383 /* Description UPDATE_OOR_MODE 384 385 Consumer: REO 386 Producer: SW 387 When set, OOR_Mode from this command will be updated in 388 the descriptor. 389 <legal all> 390 */ 391 392 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 393 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 394 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 395 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 396 397 398 /* Description UPDATE_BA_WINDOW_SIZE 399 400 Consumer: REO 401 Producer: SW 402 When set, BA_window_size from this command will be updated 403 in the descriptor. 404 <legal all> 405 */ 406 407 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 408 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 409 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 410 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 411 412 413 /* Description UPDATE_PN_CHECK_NEEDED 414 415 Consumer: REO 416 Producer: SW 417 When set, Pn_check_needed from this command will be updated 418 in the descriptor. 419 <legal all> 420 */ 421 422 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 423 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 424 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 425 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 426 427 428 /* Description UPDATE_PN_SHALL_BE_EVEN 429 430 Consumer: REO 431 Producer: SW 432 When set, Pn_shall_be_even from this command will be updated 433 in the descriptor. 434 <legal all> 435 */ 436 437 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 438 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 439 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 440 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 441 442 443 /* Description UPDATE_PN_SHALL_BE_UNEVEN 444 445 Consumer: REO 446 Producer: SW 447 When set, Pn_shall_be_uneven from this command will be updated 448 in the descriptor. 449 <legal all> 450 */ 451 452 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 453 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 454 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 455 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 456 457 458 /* Description UPDATE_PN_HANDLING_ENABLE 459 460 Consumer: REO 461 Producer: SW 462 When set, Pn_handling_enable from this command will be updated 463 in the descriptor. 464 <legal all> 465 */ 466 467 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 468 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 469 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 470 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 471 472 473 /* Description UPDATE_PN_SIZE 474 475 Consumer: REO 476 Producer: SW 477 When set, Pn_size from this command will be updated in the 478 descriptor. 479 <legal all> 480 */ 481 482 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 483 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 484 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 485 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 486 487 488 /* Description UPDATE_IGNORE_AMPDU_FLAG 489 490 Consumer: REO 491 Producer: SW 492 When set, Ignore_ampdu_flag from this command will be updated 493 in the descriptor. 494 <legal all> 495 */ 496 497 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 498 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 499 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 500 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 501 502 503 /* Description UPDATE_SVLD 504 505 Consumer: REO 506 Producer: SW 507 When set, Svld from this command will be updated in the 508 descriptor. 509 <legal all> 510 */ 511 512 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 513 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 514 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 515 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 516 517 518 /* Description UPDATE_SSN 519 520 Consumer: REO 521 Producer: SW 522 When set, SSN from this command will be updated in the descriptor. 523 524 <legal all> 525 */ 526 527 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 528 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 529 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 530 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 531 532 533 /* Description UPDATE_SEQ_2K_ERROR_DETECTED_FLAG 534 535 Consumer: REO 536 Producer: SW 537 When set, Seq_2k_error_detected_flag from this command will 538 be updated in the descriptor. 539 <legal all> 540 */ 541 542 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 543 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 544 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 545 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 546 547 548 /* Description UPDATE_PN_ERROR_DETECTED_FLAG 549 550 Consumer: REO 551 Producer: SW 552 When set, pn_error_detected_flag from this command will 553 be updated in the descriptor. 554 <legal all> 555 */ 556 557 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 558 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 559 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 560 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 561 562 563 /* Description UPDATE_PN_VALID 564 565 Consumer: REO 566 Producer: SW 567 When set, pn_valid from this command will be updated in 568 the descriptor. 569 <legal all> 570 */ 571 572 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 573 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 574 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 575 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 576 577 578 /* Description UPDATE_PN 579 580 Consumer: REO 581 Producer: SW 582 When set, all pn_... fields from this command will be updated 583 in the descriptor. 584 <legal all> 585 */ 586 587 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 588 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 589 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 590 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 591 592 593 /* Description CLEAR_STAT_COUNTERS 594 595 Consumer: REO 596 Producer: SW 597 When set, REO will clear (=> set to 0) the following stat 598 counters in the REO_QUEUE_STRUCT 599 600 Last_rx_enqueue_TimeStamp 601 Last_rx_dequeue_Timestamp 602 Rx_bitmap (not a counter, but bitmap is cleared) 603 Timeout_count 604 Forward_due_to_bar_count 605 Duplicate_count 606 Frames_in_order_count 607 BAR_received_count 608 MPDU_Frames_processed_count 609 MSDU_Frames_processed_count 610 Total_processed_byte_count 611 Late_receive_MPDU_count 612 window_jump_2k 613 Hole_count 614 615 <legal all> 616 */ 617 618 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 619 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 620 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 621 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 622 623 624 /* Description RECEIVE_QUEUE_NUMBER 625 626 Field only valid when Update_receive_queue_number is set 627 628 629 Field value to be copied over into the RX_REO_QUEUE descriptor. 630 631 <legal all> 632 */ 633 634 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 635 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 636 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 637 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 638 639 640 /* Description VLD 641 642 Field only valid when Update_VLD is set 643 644 For Update_VLD set and VLD clear, SW MUST set the Flush_from_cache 645 bit in this command. 646 647 Field value to be copied over into the RX_REO_QUEUE descriptor. 648 649 <legal all> 650 */ 651 652 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 653 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 654 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 655 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 656 657 658 /* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER 659 660 Field only valid when Update_Associated_link_descriptor_counter 661 is set 662 663 Field value to be copied over into the RX_REO_QUEUE descriptor. 664 665 <legal all> 666 */ 667 668 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 669 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 670 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 671 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 672 673 674 /* Description DISABLE_DUPLICATE_DETECTION 675 676 Field only valid when Update_Disable_duplicate_detection 677 is set 678 679 Field value to be copied over into the RX_REO_QUEUE descriptor. 680 681 <legal all> 682 */ 683 684 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 685 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 686 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 687 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 688 689 690 /* Description SOFT_REORDER_ENABLE 691 692 Field only valid when Update_Soft_reorder_enable is set 693 694 Field value to be copied over into the RX_REO_QUEUE descriptor. 695 696 <legal all> 697 */ 698 699 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 700 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 701 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 702 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 703 704 705 /* Description AC 706 707 Field only valid when Update_AC is set 708 709 Field value to be copied over into the RX_REO_QUEUE descriptor. 710 711 <legal all> 712 */ 713 714 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 715 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 716 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 717 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 718 719 720 /* Description BAR 721 722 Field only valid when Update_BAR is set 723 724 Field value to be copied over into the RX_REO_QUEUE descriptor. 725 726 <legal all> 727 */ 728 729 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 730 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 731 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 732 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 733 734 735 /* Description RTY 736 737 Field only valid when Update_RTY is set 738 739 Field value to be copied over into the RX_REO_QUEUE descriptor. 740 741 <legal all> 742 */ 743 744 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 745 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 746 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 747 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 748 749 750 /* Description CHK_2K_MODE 751 752 Field only valid when Update_Chk_2k_Mode is set 753 754 Field value to be copied over into the RX_REO_QUEUE descriptor. 755 756 <legal all> 757 */ 758 759 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 760 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 761 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 762 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 763 764 765 /* Description OOR_MODE 766 767 Field only valid when Update_OOR_Mode is set 768 769 Field value to be copied over into the RX_REO_QUEUE descriptor. 770 771 <legal all> 772 */ 773 774 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 775 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 776 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 777 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 778 779 780 /* Description PN_CHECK_NEEDED 781 782 Field only valid when Update_Pn_check_needed is set 783 784 Field value to be copied over into the RX_REO_QUEUE descriptor. 785 786 <legal all> 787 */ 788 789 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 790 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 791 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 792 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 793 794 795 /* Description PN_SHALL_BE_EVEN 796 797 Field only valid when Update_Pn_shall_be_even is set 798 799 Field value to be copied over into the RX_REO_QUEUE descriptor. 800 801 <legal all> 802 */ 803 804 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 805 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 806 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 807 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 808 809 810 /* Description PN_SHALL_BE_UNEVEN 811 812 Field only valid when Update_Pn_shall_be_uneven is set 813 814 Field value to be copied over into the RX_REO_QUEUE descriptor. 815 816 <legal all> 817 */ 818 819 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 820 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 821 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 822 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 823 824 825 /* Description PN_HANDLING_ENABLE 826 827 Field only valid when Update_Pn_handling_enable is set 828 829 Field value to be copied over into the RX_REO_QUEUE descriptor. 830 831 <legal all> 832 */ 833 834 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 835 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 836 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 837 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 838 839 840 /* Description IGNORE_AMPDU_FLAG 841 842 Field only valid when Update_Ignore_ampdu_flag is set 843 844 Field value to be copied over into the RX_REO_QUEUE descriptor. 845 846 <legal all> 847 */ 848 849 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 850 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 851 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 852 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 853 854 855 /* Description BA_WINDOW_SIZE 856 857 Field only valid when Update_BA_window_size is set 858 859 Field value to be copied over into the RX_REO_QUEUE descriptor. 860 861 <legal all> 862 */ 863 864 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 865 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 866 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 867 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff 868 869 870 /* Description PN_SIZE 871 872 Field only valid when Update_Pn_size is set 873 874 Field value to be copied over into the RX_REO_QUEUE descriptor. 875 876 877 <enum 0 pn_size_24> 878 <enum 1 pn_size_48> 879 <enum 2 pn_size_128> 880 881 <legal 0-2> 882 */ 883 884 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 885 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 886 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 887 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 888 889 890 /* Description SVLD 891 892 Field only valid when Update_Svld is set 893 894 Field value to be copied over into the RX_REO_QUEUE descriptor. 895 896 <legal all> 897 */ 898 899 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 900 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 901 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 902 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 903 904 905 /* Description SSN 906 907 Field only valid when Update_SSN is set 908 909 Field value to be copied over into the RX_REO_QUEUE descriptor. 910 911 <legal all> 912 */ 913 914 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 915 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 916 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 917 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 918 919 920 /* Description SEQ_2K_ERROR_DETECTED_FLAG 921 922 Field only valid when Update_Seq_2k_error_detected_flag 923 is set 924 925 Field value to be copied over into the RX_REO_QUEUE descriptor. 926 927 <legal all> 928 */ 929 930 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 931 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 932 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 933 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 934 935 936 /* Description PN_ERROR_DETECTED_FLAG 937 938 Field only valid when Update_pn_error_detected_flag is set 939 940 941 Field value to be copied over into the RX_REO_QUEUE descriptor. 942 943 <legal all> 944 */ 945 946 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 947 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 948 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 949 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 950 951 952 /* Description PN_VALID 953 954 Field only valid when Update_pn_valid is set 955 956 Field value to be copied over into the RX_REO_QUEUE descriptor. 957 958 <legal all> 959 */ 960 961 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 962 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 963 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 964 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 965 966 967 /* Description FLUSH_FROM_CACHE 968 969 When set, REO shall, after finishing the execution of this 970 command, flush the related descriptor from the cache. 971 <legal all> 972 */ 973 974 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 975 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 976 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 977 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 978 979 980 /* Description RESERVED_4A 981 982 <legal 0> 983 */ 984 985 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 986 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 987 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 988 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 989 990 991 /* Description PN_31_0 992 993 Field only valid when Update_Pn is set 994 995 Field value to be copied over into the RX_REO_QUEUE descriptor. 996 997 <legal all> 998 */ 999 1000 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 1001 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 1002 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 1003 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 1004 1005 1006 /* Description PN_63_32 1007 1008 Field only valid when Update_pn is set 1009 1010 Field value to be copied over into the RX_REO_QUEUE descriptor. 1011 1012 <legal all> 1013 */ 1014 1015 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 1016 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 1017 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 1018 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff 1019 1020 1021 /* Description PN_95_64 1022 1023 Field only valid when Update_pn is set 1024 1025 Field value to be copied over into the RX_REO_QUEUE descriptor. 1026 1027 <legal all> 1028 */ 1029 1030 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 1031 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 1032 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 1033 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 1034 1035 1036 /* Description PN_127_96 1037 1038 Field only valid when Update_pn is set 1039 1040 Field value to be copied over into the RX_REO_QUEUE descriptor. 1041 1042 <legal all> 1043 */ 1044 1045 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 1046 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 1047 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 1048 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff 1049 1050 1051 /* Description TLV64_PADDING 1052 1053 Automatic DWORD padding inserted while converting TLV32 1054 to TLV64 for 64 bit ARCH 1055 <legal 0> 1056 */ 1057 1058 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 1059 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 1060 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 1061 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 1062 1063 1064 1065 #endif // REO_UPDATE_RX_REO_QUEUE 1066