1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 27 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 35 36 37 struct reo_update_rx_reo_queue_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t reserved_2a : 32; // [31:0] 41 uint32_t reserved_3a : 32; // [31:0] 42 uint32_t reserved_4a : 32; // [31:0] 43 uint32_t reserved_5a : 32; // [31:0] 44 uint32_t reserved_6a : 32; // [31:0] 45 uint32_t reserved_7a : 32; // [31:0] 46 uint32_t reserved_8a : 32; // [31:0] 47 uint32_t reserved_9a : 32; // [31:0] 48 uint32_t reserved_10a : 32; // [31:0] 49 uint32_t reserved_11a : 32; // [31:0] 50 uint32_t reserved_12a : 32; // [31:0] 51 uint32_t reserved_13a : 32; // [31:0] 52 uint32_t reserved_14a : 32; // [31:0] 53 uint32_t reserved_15a : 32; // [31:0] 54 uint32_t reserved_16a : 32; // [31:0] 55 uint32_t reserved_17a : 32; // [31:0] 56 uint32_t reserved_18a : 32; // [31:0] 57 uint32_t reserved_19a : 32; // [31:0] 58 uint32_t reserved_20a : 32; // [31:0] 59 uint32_t reserved_21a : 32; // [31:0] 60 uint32_t reserved_22a : 32; // [31:0] 61 uint32_t reserved_23a : 32; // [31:0] 62 uint32_t reserved_24a : 32; // [31:0] 63 uint32_t reserved_25a : 28, // [27:0] 64 looping_count : 4; // [31:28] 65 #else 66 struct uniform_reo_status_header status_header; 67 uint32_t reserved_2a : 32; // [31:0] 68 uint32_t reserved_3a : 32; // [31:0] 69 uint32_t reserved_4a : 32; // [31:0] 70 uint32_t reserved_5a : 32; // [31:0] 71 uint32_t reserved_6a : 32; // [31:0] 72 uint32_t reserved_7a : 32; // [31:0] 73 uint32_t reserved_8a : 32; // [31:0] 74 uint32_t reserved_9a : 32; // [31:0] 75 uint32_t reserved_10a : 32; // [31:0] 76 uint32_t reserved_11a : 32; // [31:0] 77 uint32_t reserved_12a : 32; // [31:0] 78 uint32_t reserved_13a : 32; // [31:0] 79 uint32_t reserved_14a : 32; // [31:0] 80 uint32_t reserved_15a : 32; // [31:0] 81 uint32_t reserved_16a : 32; // [31:0] 82 uint32_t reserved_17a : 32; // [31:0] 83 uint32_t reserved_18a : 32; // [31:0] 84 uint32_t reserved_19a : 32; // [31:0] 85 uint32_t reserved_20a : 32; // [31:0] 86 uint32_t reserved_21a : 32; // [31:0] 87 uint32_t reserved_22a : 32; // [31:0] 88 uint32_t reserved_23a : 32; // [31:0] 89 uint32_t reserved_24a : 32; // [31:0] 90 uint32_t looping_count : 4, // [31:28] 91 reserved_25a : 28; // [27:0] 92 #endif 93 }; 94 95 96 /* Description STATUS_HEADER 97 98 Consumer: SW 99 Producer: REO 100 101 Details that can link this status with the original command. 102 It also contains info on how long REO took to execute this 103 command. 104 */ 105 106 107 /* Description REO_STATUS_NUMBER 108 109 Consumer: SW , DEBUG 110 Producer: REO 111 112 The value in this field is equal to value of the 'REO_CMD_Number' 113 field the REO command 114 115 This field helps to correlate the statuses with the REO 116 commands. 117 118 <legal all> 119 */ 120 121 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 122 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 123 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 124 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 125 126 127 /* Description CMD_EXECUTION_TIME 128 129 Consumer: DEBUG 130 Producer: REO 131 132 The amount of time REO took to excecute the command. Note 133 that this time does not include the duration of the command 134 waiting in the command ring, before the execution started. 135 136 137 In us. 138 139 <legal all> 140 */ 141 142 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 143 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 144 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 145 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 146 147 148 /* Description REO_CMD_EXECUTION_STATUS 149 150 Consumer: DEBUG 151 Producer: REO 152 153 Execution status of the command. 154 155 <enum 0 reo_successful_execution> Command has successfully 156 be executed 157 <enum 1 reo_blocked_execution> Command could not be executed 158 as the queue or cache was blocked 159 <enum 2 reo_failed_execution> Command has encountered problems 160 when executing, like the queue descriptor not being valid. 161 None of the status fields in the entire STATUS TLV are valid. 162 163 <enum 3 reo_resource_blocked> Command is NOT executed because 164 one or more descriptors were blocked. This is SW programming 165 mistake. 166 None of the status fields in the entire STATUS TLV are valid. 167 168 169 <legal 0-3> 170 */ 171 172 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 173 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 174 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 175 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 176 177 178 /* Description RESERVED_0A 179 180 <legal 0> 181 */ 182 183 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 184 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 185 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 186 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 187 188 189 /* Description TIMESTAMP 190 191 Timestamp at the moment that this status report is written. 192 193 194 <legal all> 195 */ 196 197 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 198 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 199 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 200 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 201 202 203 /* Description RESERVED_2A 204 205 <legal 0> 206 */ 207 208 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 209 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 210 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 211 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff 212 213 214 /* Description RESERVED_3A 215 216 <legal 0> 217 */ 218 219 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 220 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 221 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 222 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 223 224 225 /* Description RESERVED_4A 226 227 <legal 0> 228 */ 229 230 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 231 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 232 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 233 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 234 235 236 /* Description RESERVED_5A 237 238 <legal 0> 239 */ 240 241 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 242 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 243 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 244 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 245 246 247 /* Description RESERVED_6A 248 249 <legal 0> 250 */ 251 252 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 253 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 254 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 255 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 256 257 258 /* Description RESERVED_7A 259 260 <legal 0> 261 */ 262 263 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 264 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 265 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 266 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 267 268 269 /* Description RESERVED_8A 270 271 <legal 0> 272 */ 273 274 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 275 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 276 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 277 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 278 279 280 /* Description RESERVED_9A 281 282 <legal 0> 283 */ 284 285 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 286 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 287 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 288 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 289 290 291 /* Description RESERVED_10A 292 293 <legal 0> 294 */ 295 296 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 297 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 298 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 299 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 300 301 302 /* Description RESERVED_11A 303 304 <legal 0> 305 */ 306 307 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 308 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 309 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 310 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 311 312 313 /* Description RESERVED_12A 314 315 <legal 0> 316 */ 317 318 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 319 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 322 323 324 /* Description RESERVED_13A 325 326 <legal 0> 327 */ 328 329 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 330 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 331 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 332 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 333 334 335 /* Description RESERVED_14A 336 337 <legal 0> 338 */ 339 340 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 341 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 342 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 343 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 344 345 346 /* Description RESERVED_15A 347 348 <legal 0> 349 */ 350 351 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 352 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 353 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 354 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 355 356 357 /* Description RESERVED_16A 358 359 <legal 0> 360 */ 361 362 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 363 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 364 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 365 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 366 367 368 /* Description RESERVED_17A 369 370 <legal 0> 371 */ 372 373 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 374 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 375 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 376 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 377 378 379 /* Description RESERVED_18A 380 381 <legal 0> 382 */ 383 384 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 385 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 386 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 387 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 388 389 390 /* Description RESERVED_19A 391 392 <legal 0> 393 */ 394 395 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 396 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 397 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 398 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 399 400 401 /* Description RESERVED_20A 402 403 <legal 0> 404 */ 405 406 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 407 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 408 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 409 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 410 411 412 /* Description RESERVED_21A 413 414 <legal 0> 415 */ 416 417 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 418 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 419 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 420 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 421 422 423 /* Description RESERVED_22A 424 425 <legal 0> 426 */ 427 428 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 429 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 430 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 431 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 432 433 434 /* Description RESERVED_23A 435 436 <legal 0> 437 */ 438 439 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 440 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 441 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 442 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 443 444 445 /* Description RESERVED_24A 446 447 <legal 0> 448 */ 449 450 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 451 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 452 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 453 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 454 455 456 /* Description RESERVED_25A 457 458 <legal 0> 459 */ 460 461 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 462 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 463 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 464 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 465 466 467 /* Description LOOPING_COUNT 468 469 A count value that indicates the number of times the producer 470 of entries into this Ring has looped around the ring. 471 At initialization time, this value is set to 0. On the first 472 loop, this value is set to 1. After the max value is reached 473 allowed by the number of bits for this field, the count 474 value continues with 0 again. 475 476 In case SW is the consumer of the ring entries, it can use 477 this field to figure out up to where the producer of entries 478 has created new entries. This eliminates the need to check 479 where the "head pointer' of the ring is located once the 480 SW starts processing an interrupt indicating that new entries 481 have been put into this ring... 482 483 Also note that SW if it wants only needs to look at the 484 LSB bit of this count value. 485 <legal all> 486 */ 487 488 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 489 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 490 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 491 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 492 493 494 495 #endif // REO_UPDATE_RX_REO_QUEUE_STATUS 496