1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RESPONSE_END_STATUS_H_ 27 #define _RESPONSE_END_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phytx_abort_request_info.h" 32 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 33 34 #define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 35 36 37 struct response_end_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t coex_bt_tx_while_wlan_tx : 1, // [0:0] 40 coex_wan_tx_while_wlan_tx : 1, // [1:1] 41 coex_wlan_tx_while_wlan_tx : 1, // [2:2] 42 global_data_underflow_warning : 1, // [3:3] 43 response_transmit_status : 4, // [7:4] 44 phytx_pkt_end_info_valid : 1, // [8:8] 45 phytx_abort_request_info_valid : 1, // [9:9] 46 generated_response : 3, // [12:10] 47 mba_user_count : 7, // [19:13] 48 mba_fake_bitmap_count : 7, // [26:20] 49 coex_based_tx_bw : 3, // [29:27] 50 trig_response_related : 1, // [30:30] 51 dpdtrain_done : 1; // [31:31] 52 struct phytx_abort_request_info phytx_abort_request_info_details; 53 uint16_t cbf_segment_request_mask : 8, // [23:16] 54 cbf_segment_sent_mask : 8; // [31:24] 55 uint32_t underflow_mpdu_count : 9, // [8:0] 56 data_underflow_warning : 2, // [10:9] 57 phy_tx_gain_setting : 8, // [18:11] 58 timing_status : 2, // [20:19] 59 only_null_delim_sent : 1, // [21:21] 60 brp_info_valid : 1, // [22:22] 61 reserved_2a : 9; // [31:23] 62 uint32_t mu_response_bitmap_31_0 : 32; // [31:0] 63 uint32_t mu_response_bitmap_36_32 : 5, // [4:0] 64 reserved_4a : 11, // [15:5] 65 transmit_delay : 16; // [31:16] 66 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 67 start_of_frame_timestamp_31_16 : 16; // [31:16] 68 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 69 end_of_frame_timestamp_31_16 : 16; // [31:16] 70 uint32_t tx_group_delay : 12, // [11:0] 71 reserved_7a : 4, // [15:12] 72 tpc_dbg_info_cmn_15_0 : 16; // [31:16] 73 uint32_t tpc_dbg_info_31_16 : 16, // [15:0] 74 tpc_dbg_info_47_32 : 16; // [31:16] 75 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] 76 tpc_dbg_info_chn1_31_16 : 16; // [31:16] 77 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] 78 tpc_dbg_info_chn1_63_48 : 16; // [31:16] 79 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] 80 tpc_dbg_info_chn2_15_0 : 16; // [31:16] 81 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] 82 tpc_dbg_info_chn2_47_32 : 16; // [31:16] 83 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] 84 tpc_dbg_info_chn2_79_64 : 16; // [31:16] 85 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 86 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 87 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 88 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 89 uint32_t addr1_31_0 : 32; // [31:0] 90 uint32_t addr1_47_32 : 16, // [15:0] 91 addr2_15_0 : 16; // [31:16] 92 uint32_t addr2_47_16 : 32; // [31:0] 93 uint32_t addr3_31_0 : 32; // [31:0] 94 uint32_t addr3_47_32 : 16, // [15:0] 95 ranging : 1, // [16:16] 96 secure : 1, // [17:17] 97 ranging_ftm_frame_sent : 1, // [18:18] 98 reserved_20a : 13; // [31:19] 99 uint32_t tlv64_padding : 32; // [31:0] 100 #else 101 uint32_t dpdtrain_done : 1, // [31:31] 102 trig_response_related : 1, // [30:30] 103 coex_based_tx_bw : 3, // [29:27] 104 mba_fake_bitmap_count : 7, // [26:20] 105 mba_user_count : 7, // [19:13] 106 generated_response : 3, // [12:10] 107 phytx_abort_request_info_valid : 1, // [9:9] 108 phytx_pkt_end_info_valid : 1, // [8:8] 109 response_transmit_status : 4, // [7:4] 110 global_data_underflow_warning : 1, // [3:3] 111 coex_wlan_tx_while_wlan_tx : 1, // [2:2] 112 coex_wan_tx_while_wlan_tx : 1, // [1:1] 113 coex_bt_tx_while_wlan_tx : 1; // [0:0] 114 uint32_t cbf_segment_sent_mask : 8, // [31:24] 115 cbf_segment_request_mask : 8; // [23:16] 116 struct phytx_abort_request_info phytx_abort_request_info_details; 117 uint32_t reserved_2a : 9, // [31:23] 118 brp_info_valid : 1, // [22:22] 119 only_null_delim_sent : 1, // [21:21] 120 timing_status : 2, // [20:19] 121 phy_tx_gain_setting : 8, // [18:11] 122 data_underflow_warning : 2, // [10:9] 123 underflow_mpdu_count : 9; // [8:0] 124 uint32_t mu_response_bitmap_31_0 : 32; // [31:0] 125 uint32_t transmit_delay : 16, // [31:16] 126 reserved_4a : 11, // [15:5] 127 mu_response_bitmap_36_32 : 5; // [4:0] 128 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 129 start_of_frame_timestamp_15_0 : 16; // [15:0] 130 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 131 end_of_frame_timestamp_15_0 : 16; // [15:0] 132 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] 133 reserved_7a : 4, // [15:12] 134 tx_group_delay : 12; // [11:0] 135 uint32_t tpc_dbg_info_47_32 : 16, // [31:16] 136 tpc_dbg_info_31_16 : 16; // [15:0] 137 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] 138 tpc_dbg_info_chn1_15_0 : 16; // [15:0] 139 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] 140 tpc_dbg_info_chn1_47_32 : 16; // [15:0] 141 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] 142 tpc_dbg_info_chn1_79_64 : 16; // [15:0] 143 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] 144 tpc_dbg_info_chn2_31_16 : 16; // [15:0] 145 uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] 146 tpc_dbg_info_chn2_63_48 : 16; // [15:0] 147 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 148 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 149 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 150 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 151 uint32_t addr1_31_0 : 32; // [31:0] 152 uint32_t addr2_15_0 : 16, // [31:16] 153 addr1_47_32 : 16; // [15:0] 154 uint32_t addr2_47_16 : 32; // [31:0] 155 uint32_t addr3_31_0 : 32; // [31:0] 156 uint32_t reserved_20a : 13, // [31:19] 157 ranging_ftm_frame_sent : 1, // [18:18] 158 secure : 1, // [17:17] 159 ranging : 1, // [16:16] 160 addr3_47_32 : 16; // [15:0] 161 uint32_t tlv64_padding : 32; // [31:0] 162 #endif 163 }; 164 165 166 /* Description COEX_BT_TX_WHILE_WLAN_TX 167 168 When set, a BT tx coex event started while wlan was in the 169 middle of response transmission. 170 171 Field set when coex_status_broadcast TLV received with bt 172 tx activity set and WLAN tx ongoing. 173 <legal all> 174 */ 175 176 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 177 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 178 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 179 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 180 181 182 /* Description COEX_WAN_TX_WHILE_WLAN_TX 183 184 When set, a WAN tx coex event started while wlan was in 185 the middle of response transmission. 186 187 Field set when coex_status_broadcast TLV received with WAN 188 tx activity set and WLAN tx ongoing 189 <legal all> 190 */ 191 192 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 193 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 194 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 195 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 196 197 198 /* Description COEX_WLAN_TX_WHILE_WLAN_TX 199 200 When set, a WLAN tx coex event started while wlan was in 201 the middle of response transmission. 202 203 Field set when coex_status_broadcast TLV received with WLAN 204 tx activity set and WLAN tx ongoing 205 <legal all> 206 */ 207 208 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 209 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 210 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 211 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 212 213 214 /* Description GLOBAL_DATA_UNDERFLOW_WARNING 215 216 Consumer: SCH/SW 217 Producer: TXPCU 218 219 When set, during response transmission a data underflow 220 occurred for one or more users.<legal all> 221 */ 222 223 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 224 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 225 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 226 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 227 228 229 /* Description RESPONSE_TRANSMIT_STATUS 230 231 <enum 0 response_ok> Successful transmission of the selfgen 232 response frame 233 <enum 1 response_coex_soft_abort> Set if transmission is 234 terminated because of the coex soft abort. 235 <enum 2 response_phy_err> Set if transmission is terminated 236 because PHY generated an abort request 237 <enum 3 response_flush_received> Set if transmission is 238 terminated because RXPCU received a flush request 239 <enum 4 response_other_err> Set if transmission is terminated 240 because of other errors within the RXPCU 241 <legal 0-4> 242 */ 243 244 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 245 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 246 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 247 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 248 249 250 /* Description PHYTX_PKT_END_INFO_VALID 251 252 All the fields originating from PHYTX_PKT_END TLV contain 253 valid info 254 255 Note that when "trig_response_related" is set, this bit 256 will often not be set as the trigger response contents might 257 have come from a scheduling command which is not reported 258 as part of the 'response' transmission. 259 */ 260 261 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 262 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 263 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 264 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 265 266 267 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 268 269 Field Phytx_abort_request_info_details contains valid info 270 271 */ 272 273 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 274 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 275 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 276 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 277 278 279 /* Description GENERATED_RESPONSE 280 281 The generated response frame 282 283 <enum 0 selfgen_ACK> TXPCU generated an ACK response. Note 284 that this can be part of a trigger response. In that case 285 bit trig_response_related will be set as well. 286 287 <enum 1 selfgen_CTS> TXPCU generated an CTS response. Note 288 that this can be part of a trigger response. In that case 289 bit trig_response_related will be set as well. 290 291 <enum 2 selfgen_BA> TXPCU generated a BA response. Note 292 that this can be part of a trigger response. In that case 293 bit trig_response_related will be set as well. 294 295 <enum 3 selfgen_MBA> TXPCU generated an M BA response. Note 296 that this can be part of a trigger response. In that case 297 bit trig_response_related will be set as well. 298 299 <enum 4 selfgen_CBF> TXPCU generated a CBF response. Note 300 that this can be part of a trigger response. In that case 301 bit trig_response_related will be set as well. 302 303 <enum 5 selfgen_other_trig_response> 304 TXPCU generated a trigger related response of a type not 305 specified above. Note that in this case bit trig_response_related 306 will be set as well. 307 This e-num will also be used when TXPCU has been programmed 308 to overwrite it's own self gen response generation, and 309 wait for the response to come from SCH.. 310 Also applicable for basic trigger response. 311 312 <enum 6 selfgen_NDP_LMR> TXPCU generated a self-gen NDP 313 followed by a self-gen LMR for the ranging NDPA followed 314 by NDP received by RXPCU. 315 316 <legal 0-6> 317 */ 318 319 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 320 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 321 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 322 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 323 324 325 /* Description MBA_USER_COUNT 326 327 Field only valid in case of selfgen_MBA 328 329 The number of users included in the generated MBA 330 331 Note that this value will be the same as in TLV/field: RESPONSE_START_STATUS.response_STA_count 332 333 334 <legal all> 335 */ 336 337 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 338 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 339 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 340 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 341 342 343 /* Description MBA_FAKE_BITMAP_COUNT 344 345 Field only valid in case of MU OFDMA selfgen_MBA 346 347 The number of users for which RXPCU did not have a bitmap, 348 and thus provided a 'fake bitmap' 349 <legal all> 350 */ 351 352 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 353 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 354 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 355 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 356 357 358 /* Description COEX_BASED_TX_BW 359 360 This is the transmit bandwidth value 361 that is granted by Coex for the response frame 362 363 <enum 0 20_mhz>20 Mhz BW 364 <enum 1 40_mhz>40 Mhz BW 365 <enum 2 80_mhz>80 Mhz BW 366 <enum 3 160_mhz>160 Mhz BW 367 <enum 4 320_mhz>320 Mhz BW 368 <enum 5 240_mhz>240 Mhz BW 369 */ 370 371 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 372 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 373 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 374 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 375 376 377 /* Description TRIG_RESPONSE_RELATED 378 379 When set, this TLV is generated by TXPCU in the context 380 of a response transmission to a received trigger frame. 381 382 <legal all> 383 */ 384 385 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 386 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 387 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 388 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 389 390 391 /* Description DPDTRAIN_DONE 392 393 Field only valid when PHYTX_PKT_END_info_valid is set 394 395 For DPD Training packets, this bit is set to indicate that 396 DPD Training was successfully run to completion. Also 397 reused by Implicit BF Calibration Packets. This bit is intended 398 for debug purposes. 399 <legal all> 400 */ 401 402 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 403 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 404 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 405 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 406 407 408 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 409 410 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 411 set 412 413 The reason why PHYTX is requested an abort 414 */ 415 416 417 /* Description PHYTX_ABORT_REASON 418 419 Reason for early termination of TX packet by the PHY 420 421 <enum_type PHYTX_ABORT_ENUM> 422 */ 423 424 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 425 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 426 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 427 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 428 429 430 /* Description USER_NUMBER 431 432 For some errors, the user for which this error was detected 433 can be indicated in this field. 434 <legal 0-36> 435 */ 436 437 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 438 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 439 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 440 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 441 442 443 /* Description RESERVED 444 445 <legal 0> 446 */ 447 448 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 449 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 450 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 451 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 452 453 454 /* Description CBF_SEGMENT_REQUEST_MASK 455 456 Field only valid when brp_info_valid is set. 457 458 Field equal to the 'Feedback Segment Retransmission Bitmap' 459 from the Beamform Report Poll frame OR Beamform Report Poll 460 Trigger frame 461 462 Bit 0 represents segment 0 463 Bit 1 represents segment 1 464 Etc. 465 466 1'b1: Segment is requested 467 1'b0: Segment is NOT requested 468 469 <legal all> 470 */ 471 472 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 473 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 474 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 475 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 476 477 478 /* Description CBF_SEGMENT_SENT_MASK 479 480 Field only valid when brp_info_valid is set. 481 482 Bit 0 represents segment 0 483 Bit 1 represents segment 1 484 Etc. 485 486 1'b1: Segment is sent 487 1'b0: Segment is not sent 488 489 <legal all> 490 */ 491 492 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 493 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 494 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 495 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 496 497 498 /* Description UNDERFLOW_MPDU_COUNT 499 500 The MPDU count transmitted when the first underrun condition 501 was detected 502 <legal 0-256> 503 */ 504 505 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 506 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 507 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 508 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 509 510 511 /* Description DATA_UNDERFLOW_WARNING 512 513 Mac data underflow warning 514 515 <enum 0 no_data_underrun> No data underflow 516 <enum 1 data_underrun_between_mpdu> PCU experienced data 517 underflow in between MPDUs 518 <enum 2 data_underrun_within_mpdu> PCU experienced data 519 underflow within an MPDU 520 <legal 0-2> 521 */ 522 523 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 524 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 525 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 526 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 527 528 529 /* Description PHY_TX_GAIN_SETTING 530 531 PHYTX_PKT_END info 532 533 Field only valid when PHYTX_PKT_END_info_valid is set 534 535 The gain setting that the PHY used for this last PPDU transmission 536 537 */ 538 539 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 540 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 541 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 542 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 543 544 545 /* Description TIMING_STATUS 546 547 PHYTX_PKT_END info 548 549 Field only valid when PHYTX_PKT_END_info_valid is set 550 551 <enum 0 No_tx_timing_request> The MAC did not request for 552 the transmission to start at a particular time 553 <enum 1 successful_tx_timing > MAC did request for transmission 554 to start at a particular time and PHY was able to do so. 555 556 <enum 2 tx_timing_not_honoured> PHY was not able to honour 557 the requested transmit time by the MAC. The transmission 558 started later, and field transmit_delay indicates how much 559 later. 560 <legal 0-2> 561 */ 562 563 #define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 564 #define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 565 #define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 566 #define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 567 568 569 /* Description ONLY_NULL_DELIM_SENT 570 571 Field only valid when "trig_response_related" is set. 572 573 When set, TXPCU only sent NULL delimiters to the PHY for 574 the entire duration of the trigger response time. 575 576 Note that SCH does not evaluate this field. It is only for 577 SW to look at. 578 579 Setting this bit can only happen when a trigger is received, 580 and either the trigger allocated an incorrectly small duration, 581 or SW had not programmed a response scheduler command in 582 time to respond, which may not comply with the 11ax IEEE 583 spec. 584 585 <legal all> 586 */ 587 588 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 589 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 590 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 591 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 592 593 594 /* Description BRP_INFO_VALID 595 596 When set, TXPCU sent CBF segments. 597 598 Fields cbf_segment_request_mask and cbf_segment_sent_mask 599 contain valid info. 600 601 <legal all> 602 */ 603 604 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 605 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 606 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 607 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 608 609 610 /* Description RESERVED_2A 611 612 <legal 0> 613 */ 614 615 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 616 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 617 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 618 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 619 620 621 /* Description MU_RESPONSE_BITMAP_31_0 622 623 Bit 0 represents user 0 624 Bit 1 represents user 1 625 ... 626 When set, at least 1 MPDU from this user has been properly 627 received => FCS OK 628 629 TODO: remove these 630 Field can not be filled in with the self generated response 631 632 */ 633 634 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 635 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 636 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 637 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 638 639 640 /* Description MU_RESPONSE_BITMAP_36_32 641 642 Bit 0 represents user 32 643 Bit 1 represents user 33 644 ... 645 When set, at least 1 MPDU from this user has been properly 646 received => FCS OK 647 TODO: remove these 648 Field can not be filled in with the self generated response 649 650 Note: Received_response already goes to SW, so probably 651 no need to copy this bitmap info to TX_FES_STATUS TLV. 652 */ 653 654 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 655 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 656 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 657 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f 658 659 660 /* Description RESERVED_4A 661 662 <legal 0> 663 */ 664 665 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 666 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 667 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 668 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 669 670 671 /* Description TRANSMIT_DELAY 672 673 PHYTX_PKT_END info 674 675 Field only valid when PHYTX_PKT_END_info_valid is set 676 677 The number of 480 MHz clock cycles that the transmission 678 started after the actual requested transmit start time. 679 680 Value saturates at 0xFFFF 681 <legal all> 682 */ 683 684 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 685 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 686 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 687 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 688 689 690 /* Description START_OF_FRAME_TIMESTAMP_15_0 691 692 PHYTX_PKT_END info 693 694 Field only valid when PHYTX_PKT_END_info_valid is set 695 696 bits 15:0 of a 64 bit time stamp 697 Start of frame in the medium @960 MHz 698 <legal all> 699 */ 700 701 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 702 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 703 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 704 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 705 706 707 /* Description START_OF_FRAME_TIMESTAMP_31_16 708 709 PHYTX_PKT_END info 710 711 Field only valid when PHYTX_PKT_END_info_valid is set 712 713 bits 31:16 of a 64 bit time stamp 714 Start of frame in the medium @960 MHz 715 <legal all> 716 */ 717 718 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 719 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 720 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 721 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 722 723 724 /* Description END_OF_FRAME_TIMESTAMP_15_0 725 726 PHYTX_PKT_END info 727 728 Field only valid when PHYTX_PKT_END_info_valid is set 729 730 bits 15:0 of a 64 bit time stamp 731 End of frame in the medium @960 MHz 732 <legal all> 733 */ 734 735 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 736 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 737 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 738 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 739 740 741 /* Description END_OF_FRAME_TIMESTAMP_31_16 742 743 PHYTX_PKT_END info 744 745 Field only valid when PHYTX_PKT_END_info_valid is set 746 747 bits 31:16 of a 64 bit time stamp 748 End of frame in the medium @960 MHz 749 <legal all> 750 */ 751 752 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 753 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 754 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 755 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 756 757 758 /* Description TX_GROUP_DELAY 759 760 PHYTX_PKT_END info 761 762 Field only valid when PHYTX_PKT_END_info_valid is set 763 764 Group delay on TxTD+PHYRF path for this PPDU (packet BW 765 dependent), useful for RTT 766 767 Unit is 960MHz cycles. 768 <legal all> 769 */ 770 771 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 772 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 773 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 774 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 775 776 777 /* Description RESERVED_7A 778 779 <legal 0> 780 */ 781 782 #define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 783 #define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 784 #define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 785 #define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 786 787 788 /* Description TPC_DBG_INFO_CMN_15_0 789 790 PHYTX_PKT_END info 791 792 Field only valid when PHYTX_PKT_END_info_valid is set 793 794 Some TPC debug info that PHY can pass back to MAC FW 795 <legal all> 796 */ 797 798 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 799 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 800 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 801 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 802 803 804 /* Description TPC_DBG_INFO_31_16 805 806 PHYTX_PKT_END info 807 808 Field only valid when PHYTX_PKT_END_info_valid is set 809 810 Some TPC debug info that PHY can pass back to MAC FW 811 <legal all> 812 */ 813 814 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 815 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 816 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 817 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff 818 819 820 /* Description TPC_DBG_INFO_47_32 821 822 PHYTX_PKT_END info 823 824 Field only valid when PHYTX_PKT_END_info_valid is set 825 826 Some TPC debug infothat PHY can pass back to MAC FW 827 <legal all> 828 */ 829 830 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 831 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 832 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 833 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 834 835 836 /* Description TPC_DBG_INFO_CHN1_15_0 837 838 PHYTX_PKT_END info 839 840 Field only valid when PHYTX_PKT_END_info_valid is set 841 842 Some per-chain TPC debug info for the first selected chain 843 that PHY can pass back to MAC FW 844 <legal all> 845 */ 846 847 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 848 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 849 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 850 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 851 852 853 /* Description TPC_DBG_INFO_CHN1_31_16 854 855 PHYTX_PKT_END info 856 857 Field only valid when PHYTX_PKT_END_info_valid is set 858 859 Some per-chain TPC debug info for the first selected chain 860 that PHY can pass back to MAC FW 861 <legal all> 862 */ 863 864 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 865 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 866 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 867 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 868 869 870 /* Description TPC_DBG_INFO_CHN1_47_32 871 872 PHYTX_PKT_END info 873 874 Field only valid when PHYTX_PKT_END_info_valid is set 875 876 Some per-chain TPC debug info for the first selected chain 877 that PHY can pass back to MAC FW 878 <legal all> 879 */ 880 881 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 882 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 883 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 884 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 885 886 887 /* Description TPC_DBG_INFO_CHN1_63_48 888 889 PHYTX_PKT_END info 890 891 Field only valid when PHYTX_PKT_END_info_valid is set 892 893 Some per-chain TPC debug info for the first selected chain 894 that PHY can pass back to MAC FW 895 <legal all> 896 */ 897 898 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 899 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 900 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 901 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 902 903 904 /* Description TPC_DBG_INFO_CHN1_79_64 905 906 PHYTX_PKT_END info 907 908 Field only valid when PHYTX_PKT_END_info_valid is set 909 910 Some per-chain TPC debug info for the first selected chain 911 that PHY can pass back to MAC FW 912 <legal all> 913 */ 914 915 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 916 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 917 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 918 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 919 920 921 /* Description TPC_DBG_INFO_CHN2_15_0 922 923 PHYTX_PKT_END info 924 925 Field only valid when PHYTX_PKT_END_info_valid is set 926 927 Some per-chain TPC debug info for the second selected chain 928 that PHY can pass back to MAC FW 929 <legal all> 930 */ 931 932 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 933 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 934 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 935 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 936 937 938 /* Description TPC_DBG_INFO_CHN2_31_16 939 940 PHYTX_PKT_END info 941 942 Field only valid when PHYTX_PKT_END_info_valid is set 943 944 Some per-chain TPC debug info for the second selected chain 945 that PHY can pass back to MAC FW 946 <legal all> 947 */ 948 949 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 950 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 951 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 952 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 953 954 955 /* Description TPC_DBG_INFO_CHN2_47_32 956 957 PHYTX_PKT_END info 958 959 Field only valid when PHYTX_PKT_END_info_valid is set 960 961 Some per-chain TPC debug info for the second selected chain 962 that PHY can pass back to MAC FW 963 <legal all> 964 */ 965 966 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 967 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 968 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 969 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 970 971 972 /* Description TPC_DBG_INFO_CHN2_63_48 973 974 PHYTX_PKT_END info 975 976 Field only valid when PHYTX_PKT_END_info_valid is set 977 978 Some per-chain TPC debug info for the second selected chain 979 that PHY can pass back to MAC FW 980 <legal all> 981 */ 982 983 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 984 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 985 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 986 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 987 988 989 /* Description TPC_DBG_INFO_CHN2_79_64 990 991 PHYTX_PKT_END info 992 993 Field only valid when PHYTX_PKT_END_info_valid is set 994 995 Some per-chain TPC debug info for the second selected chain 996 that PHY can pass back to MAC FW 997 <legal all> 998 */ 999 1000 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 1001 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 1002 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 1003 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 1004 1005 1006 /* Description PHYTX_TX_END_SW_INFO_15_0 1007 1008 PHYTX_PKT_END info 1009 1010 Field only valid when PHYTX_PKT_END_info_valid is set 1011 1012 Some PHY status data that PHY microcode can pass back to 1013 MAC FW, for any future requests, e.g. any DMA download 1014 time 1015 <legal all> 1016 */ 1017 1018 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 1019 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 1020 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 1021 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 1022 1023 1024 /* Description PHYTX_TX_END_SW_INFO_31_16 1025 1026 PHYTX_PKT_END info 1027 1028 Field only valid when PHYTX_PKT_END_info_valid is set 1029 1030 Some PHY status data that PHY microcode can pass back to 1031 MAC FW, for any future requests, e.g. any DMA download 1032 time 1033 <legal all> 1034 */ 1035 1036 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 1037 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 1038 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 1039 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 1040 1041 1042 /* Description PHYTX_TX_END_SW_INFO_47_32 1043 1044 PHYTX_PKT_END info 1045 1046 Field only valid when PHYTX_PKT_END_info_valid is set 1047 1048 Some PHY status data that PHY microcode can pass back to 1049 MAC FW, for any future requests, e.g. any DMA download 1050 time 1051 <legal all> 1052 */ 1053 1054 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 1055 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 1056 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 1057 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 1058 1059 1060 /* Description PHYTX_TX_END_SW_INFO_63_48 1061 1062 PHYTX_PKT_END info 1063 1064 Field only valid when PHYTX_PKT_END_info_valid is set 1065 1066 Some PHY status data that PHY microcode can pass back to 1067 MAC FW, for any future requests, e.g. any DMA download 1068 time 1069 <legal all> 1070 */ 1071 1072 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 1073 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 1074 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 1075 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 1076 1077 1078 /* Description ADDR1_31_0 1079 1080 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1081 1082 */ 1083 1084 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 1085 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 1086 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 1087 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff 1088 1089 1090 /* Description ADDR1_47_32 1091 1092 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1093 1094 */ 1095 1096 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 1097 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 1098 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 1099 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 1100 1101 1102 /* Description ADDR2_15_0 1103 1104 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1105 1106 */ 1107 1108 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 1109 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 1110 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 1111 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 1112 1113 1114 /* Description ADDR2_47_16 1115 1116 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1117 1118 */ 1119 1120 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 1121 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 1122 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 1123 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff 1124 1125 1126 /* Description ADDR3_31_0 1127 1128 To be copied over from TX_CBF_INFO 1129 */ 1130 1131 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 1132 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 1133 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 1134 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 1135 1136 1137 /* Description ADDR3_47_32 1138 1139 To be copied over from TX_CBF_INFO 1140 */ 1141 1142 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 1143 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 1144 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 1145 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff 1146 1147 1148 /* Description RANGING 1149 1150 To be copied over from TX_CBF_INFO: Set to 1 if the status 1151 is generated due to an active ranging session (.11az) 1152 */ 1153 1154 #define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 1155 #define RESPONSE_END_STATUS_RANGING_LSB 16 1156 #define RESPONSE_END_STATUS_RANGING_MSB 16 1157 #define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 1158 1159 1160 /* Description SECURE 1161 1162 To be copied over from TX_CBF_INFO: Only valid if Ranging 1163 is set to 1, this indicates if the current ranging session 1164 is secure. 1165 */ 1166 1167 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 1168 #define RESPONSE_END_STATUS_SECURE_LSB 17 1169 #define RESPONSE_END_STATUS_SECURE_MSB 17 1170 #define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 1171 1172 1173 /* Description RANGING_FTM_FRAME_SENT 1174 1175 Only valid if Ranging is set to 1 1176 1177 TXPCU sets this bit if an FTM frame aggregated with an LMR 1178 was sent. 1179 */ 1180 1181 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 1182 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 1183 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 1184 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 1185 1186 1187 /* Description RESERVED_20A 1188 1189 <legal 0> 1190 */ 1191 1192 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 1193 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 1194 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 1195 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 1196 1197 1198 /* Description TLV64_PADDING 1199 1200 Automatic DWORD padding inserted while converting TLV32 1201 to TLV64 for 64 bit ARCH 1202 <legal 0> 1203 */ 1204 1205 #define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 1206 #define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 1207 #define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 1208 #define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 1209 1210 1211 1212 #endif // RESPONSE_END_STATUS 1213