1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_ATTENTION_H_ 27 #define _RX_ATTENTION_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_ATTENTION 4 32 33 #define NUM_OF_QWORDS_RX_ATTENTION 2 34 35 36 struct rx_attention { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 39 sw_frame_group_id : 7, // [8:2] 40 reserved_0 : 7, // [15:9] 41 phy_ppdu_id : 16; // [31:16] 42 uint32_t first_mpdu : 1, // [0:0] 43 reserved_1a : 1, // [1:1] 44 mcast_bcast : 1, // [2:2] 45 ast_index_not_found : 1, // [3:3] 46 ast_index_timeout : 1, // [4:4] 47 power_mgmt : 1, // [5:5] 48 non_qos : 1, // [6:6] 49 null_data : 1, // [7:7] 50 mgmt_type : 1, // [8:8] 51 ctrl_type : 1, // [9:9] 52 more_data : 1, // [10:10] 53 eosp : 1, // [11:11] 54 a_msdu_error : 1, // [12:12] 55 fragment_flag : 1, // [13:13] 56 order : 1, // [14:14] 57 cce_match : 1, // [15:15] 58 overflow_err : 1, // [16:16] 59 msdu_length_err : 1, // [17:17] 60 tcp_udp_chksum_fail : 1, // [18:18] 61 ip_chksum_fail : 1, // [19:19] 62 sa_idx_invalid : 1, // [20:20] 63 da_idx_invalid : 1, // [21:21] 64 reserved_1b : 1, // [22:22] 65 rx_in_tx_decrypt_byp : 1, // [23:23] 66 encrypt_required : 1, // [24:24] 67 directed : 1, // [25:25] 68 buffer_fragment : 1, // [26:26] 69 mpdu_length_err : 1, // [27:27] 70 tkip_mic_err : 1, // [28:28] 71 decrypt_err : 1, // [29:29] 72 unencrypted_frame_err : 1, // [30:30] 73 fcs_err : 1; // [31:31] 74 uint32_t flow_idx_timeout : 1, // [0:0] 75 flow_idx_invalid : 1, // [1:1] 76 wifi_parser_error : 1, // [2:2] 77 amsdu_parser_error : 1, // [3:3] 78 sa_idx_timeout : 1, // [4:4] 79 da_idx_timeout : 1, // [5:5] 80 msdu_limit_error : 1, // [6:6] 81 da_is_valid : 1, // [7:7] 82 da_is_mcbc : 1, // [8:8] 83 sa_is_valid : 1, // [9:9] 84 decrypt_status_code : 3, // [12:10] 85 rx_bitmap_not_updated : 1, // [13:13] 86 reserved_2 : 17, // [30:14] 87 msdu_done : 1; // [31:31] 88 uint32_t tlv64_padding : 32; // [31:0] 89 #else 90 uint32_t phy_ppdu_id : 16, // [31:16] 91 reserved_0 : 7, // [15:9] 92 sw_frame_group_id : 7, // [8:2] 93 rxpcu_mpdu_filter_in_category : 2; // [1:0] 94 uint32_t fcs_err : 1, // [31:31] 95 unencrypted_frame_err : 1, // [30:30] 96 decrypt_err : 1, // [29:29] 97 tkip_mic_err : 1, // [28:28] 98 mpdu_length_err : 1, // [27:27] 99 buffer_fragment : 1, // [26:26] 100 directed : 1, // [25:25] 101 encrypt_required : 1, // [24:24] 102 rx_in_tx_decrypt_byp : 1, // [23:23] 103 reserved_1b : 1, // [22:22] 104 da_idx_invalid : 1, // [21:21] 105 sa_idx_invalid : 1, // [20:20] 106 ip_chksum_fail : 1, // [19:19] 107 tcp_udp_chksum_fail : 1, // [18:18] 108 msdu_length_err : 1, // [17:17] 109 overflow_err : 1, // [16:16] 110 cce_match : 1, // [15:15] 111 order : 1, // [14:14] 112 fragment_flag : 1, // [13:13] 113 a_msdu_error : 1, // [12:12] 114 eosp : 1, // [11:11] 115 more_data : 1, // [10:10] 116 ctrl_type : 1, // [9:9] 117 mgmt_type : 1, // [8:8] 118 null_data : 1, // [7:7] 119 non_qos : 1, // [6:6] 120 power_mgmt : 1, // [5:5] 121 ast_index_timeout : 1, // [4:4] 122 ast_index_not_found : 1, // [3:3] 123 mcast_bcast : 1, // [2:2] 124 reserved_1a : 1, // [1:1] 125 first_mpdu : 1; // [0:0] 126 uint32_t msdu_done : 1, // [31:31] 127 reserved_2 : 17, // [30:14] 128 rx_bitmap_not_updated : 1, // [13:13] 129 decrypt_status_code : 3, // [12:10] 130 sa_is_valid : 1, // [9:9] 131 da_is_mcbc : 1, // [8:8] 132 da_is_valid : 1, // [7:7] 133 msdu_limit_error : 1, // [6:6] 134 da_idx_timeout : 1, // [5:5] 135 sa_idx_timeout : 1, // [4:4] 136 amsdu_parser_error : 1, // [3:3] 137 wifi_parser_error : 1, // [2:2] 138 flow_idx_invalid : 1, // [1:1] 139 flow_idx_timeout : 1; // [0:0] 140 uint32_t tlv64_padding : 32; // [31:0] 141 #endif 142 }; 143 144 145 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 146 147 Field indicates what the reason was that this MPDU frame 148 was allowed to come into the receive path by RXPCU 149 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 150 filter programming of rxpcu 151 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 152 regular frame filter and would have been dropped, were 153 it not for the frame fitting into the 'monitor_client' category. 154 155 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 156 regular frame filter and also did not pass the rxpcu_monitor_client 157 filter. It would have been dropped accept that it did pass 158 the 'monitor_other' category. 159 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 160 the normal frame filter programming of RXPCU but additionally 161 fit into the 'monitor_override_client' category. 162 <legal 0-3> 163 */ 164 165 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 166 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 167 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 168 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 169 170 171 /* Description SW_FRAME_GROUP_ID 172 173 SW processes frames based on certain classifications. This 174 field indicates to what sw classification this MPDU is 175 mapped. 176 The classification is given in priority order 177 178 <enum 0 sw_frame_group_NDP_frame> 179 180 <enum 1 sw_frame_group_Multicast_data> 181 <enum 2 sw_frame_group_Unicast_data> 182 <enum 3 sw_frame_group_Null_data > This includes mpdus of 183 type Data Null. 184 Hamilton v1 included QoS Data Null as well here. 185 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 186 Null frames except in UL MU or TB PPDUs. 187 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 188 QoS Null frames in UL MU or TB PPDUs. 189 190 <enum 4 sw_frame_group_mgmt_0000 > 191 <enum 5 sw_frame_group_mgmt_0001 > 192 <enum 6 sw_frame_group_mgmt_0010 > 193 <enum 7 sw_frame_group_mgmt_0011 > 194 <enum 8 sw_frame_group_mgmt_0100 > 195 <enum 9 sw_frame_group_mgmt_0101 > 196 <enum 10 sw_frame_group_mgmt_0110 > 197 <enum 11 sw_frame_group_mgmt_0111 > 198 <enum 12 sw_frame_group_mgmt_1000 > 199 <enum 13 sw_frame_group_mgmt_1001 > 200 <enum 14 sw_frame_group_mgmt_1010 > 201 <enum 15 sw_frame_group_mgmt_1011 > 202 <enum 16 sw_frame_group_mgmt_1100 > 203 <enum 17 sw_frame_group_mgmt_1101 > 204 <enum 18 sw_frame_group_mgmt_1110 > 205 <enum 19 sw_frame_group_mgmt_1111 > 206 207 <enum 20 sw_frame_group_ctrl_0000 > 208 <enum 21 sw_frame_group_ctrl_0001 > 209 <enum 22 sw_frame_group_ctrl_0010 > 210 <enum 23 sw_frame_group_ctrl_0011 > 211 <enum 24 sw_frame_group_ctrl_0100 > 212 <enum 25 sw_frame_group_ctrl_0101 > 213 <enum 26 sw_frame_group_ctrl_0110 > 214 <enum 27 sw_frame_group_ctrl_0111 > 215 <enum 28 sw_frame_group_ctrl_1000 > 216 <enum 29 sw_frame_group_ctrl_1001 > 217 <enum 30 sw_frame_group_ctrl_1010 > 218 <enum 31 sw_frame_group_ctrl_1011 > 219 <enum 32 sw_frame_group_ctrl_1100 > 220 <enum 33 sw_frame_group_ctrl_1101 > 221 <enum 34 sw_frame_group_ctrl_1110 > 222 <enum 35 sw_frame_group_ctrl_1111 > 223 224 <enum 36 sw_frame_group_unsupported> This covers type 3 225 and protocol version != 0 226 227 <enum 37 sw_frame_group_phy_error> PHY reported an error 228 229 230 <legal 0-39> 231 */ 232 233 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 234 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 235 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 236 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 237 238 239 /* Description RESERVED_0 240 241 <legal 0> 242 */ 243 244 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 245 #define RX_ATTENTION_RESERVED_0_LSB 9 246 #define RX_ATTENTION_RESERVED_0_MSB 15 247 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 248 249 250 /* Description PHY_PPDU_ID 251 252 A ppdu counter value that PHY increments for every PPDU 253 received. The counter value wraps around 254 <legal all> 255 */ 256 257 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 258 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 259 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 260 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 261 262 263 /* Description FIRST_MPDU 264 265 Indicates the first MSDU of the PPDU. If both first_mpdu 266 and last_mpdu are set in the MSDU then this is a not an 267 A-MPDU frame but a stand alone MPDU. Interior MPDU in 268 an A-MPDU shall have both first_mpdu and last_mpdu bits 269 set to 0. The PPDU start status will only be valid when 270 this bit is set. 271 */ 272 273 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 274 #define RX_ATTENTION_FIRST_MPDU_LSB 32 275 #define RX_ATTENTION_FIRST_MPDU_MSB 32 276 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 277 278 279 /* Description RESERVED_1A 280 281 <legal 0> 282 */ 283 284 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 285 #define RX_ATTENTION_RESERVED_1A_LSB 33 286 #define RX_ATTENTION_RESERVED_1A_MSB 33 287 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 288 289 290 /* Description MCAST_BCAST 291 292 Multicast / broadcast indicator. Only set when the MAC 293 address 1 bit 0 is set indicating mcast/bcast and the BSSID 294 matches one of the 4 BSSID registers. Only set when first_msdu 295 is set. 296 */ 297 298 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 299 #define RX_ATTENTION_MCAST_BCAST_LSB 34 300 #define RX_ATTENTION_MCAST_BCAST_MSB 34 301 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 302 303 304 /* Description AST_INDEX_NOT_FOUND 305 306 Only valid when first_msdu is set. 307 308 Indicates no AST matching entries within the the max search 309 count. 310 */ 311 312 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 313 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 314 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 315 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 316 317 318 /* Description AST_INDEX_TIMEOUT 319 320 Only valid when first_msdu is set. 321 322 Indicates an unsuccessful search in the address seach table 323 due to timeout. 324 */ 325 326 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 327 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 328 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 329 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 330 331 332 /* Description POWER_MGMT 333 334 Power management bit set in the 802.11 header. Only set 335 when first_msdu is set. 336 */ 337 338 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 339 #define RX_ATTENTION_POWER_MGMT_LSB 37 340 #define RX_ATTENTION_POWER_MGMT_MSB 37 341 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 342 343 344 /* Description NON_QOS 345 346 Set if packet is not a non-QoS data frame. Only set when 347 first_msdu is set. 348 */ 349 350 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 351 #define RX_ATTENTION_NON_QOS_LSB 38 352 #define RX_ATTENTION_NON_QOS_MSB 38 353 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 354 355 356 /* Description NULL_DATA 357 358 Set if frame type indicates either null data or QoS null 359 data format. Only set when first_msdu is set. 360 */ 361 362 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 363 #define RX_ATTENTION_NULL_DATA_LSB 39 364 #define RX_ATTENTION_NULL_DATA_MSB 39 365 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 366 367 368 /* Description MGMT_TYPE 369 370 Set if packet is a management packet. Only set when first_msdu 371 is set. 372 */ 373 374 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 375 #define RX_ATTENTION_MGMT_TYPE_LSB 40 376 #define RX_ATTENTION_MGMT_TYPE_MSB 40 377 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 378 379 380 /* Description CTRL_TYPE 381 382 Set if packet is a control packet. Only set when first_msdu 383 is set. 384 */ 385 386 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 387 #define RX_ATTENTION_CTRL_TYPE_LSB 41 388 #define RX_ATTENTION_CTRL_TYPE_MSB 41 389 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 390 391 392 /* Description MORE_DATA 393 394 Set if more bit in frame control is set. Only set when 395 first_msdu is set. 396 */ 397 398 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 399 #define RX_ATTENTION_MORE_DATA_LSB 42 400 #define RX_ATTENTION_MORE_DATA_MSB 42 401 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 402 403 404 /* Description EOSP 405 406 Set if the EOSP (end of service period) bit in the QoS control 407 field is set. Only set when first_msdu is set. 408 */ 409 410 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 411 #define RX_ATTENTION_EOSP_LSB 43 412 #define RX_ATTENTION_EOSP_MSB 43 413 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 414 415 416 /* Description A_MSDU_ERROR 417 418 Set if number of MSDUs in A-MSDU is above a threshold or 419 if the size of the MSDU is invalid. This receive buffer 420 will contain all of the remainder of the MSDUs in this 421 MPDU without decapsulation. 422 */ 423 424 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 425 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 426 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 427 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 428 429 430 /* Description FRAGMENT_FLAG 431 432 Indicates that this is an 802.11 fragment frame. This is 433 set when either the more_frag bit is set in the frame control 434 or the fragment number is not zero. Only set when first_msdu 435 is set. 436 */ 437 438 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 439 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 440 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 441 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 442 443 444 /* Description ORDER 445 446 Set if the order bit in the frame control is set. Only 447 set when first_msdu is set. 448 */ 449 450 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 451 #define RX_ATTENTION_ORDER_LSB 46 452 #define RX_ATTENTION_ORDER_MSB 46 453 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 454 455 456 /* Description CCE_MATCH 457 458 Indicates that this status has a corresponding MSDU that 459 requires FW processing. The OLE will have classification 460 ring mask registers which will indicate the ring(s) for 461 packets and descriptors which need FW attention. 462 */ 463 464 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 465 #define RX_ATTENTION_CCE_MATCH_LSB 47 466 #define RX_ATTENTION_CCE_MATCH_MSB 47 467 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 468 469 470 /* Description OVERFLOW_ERR 471 472 RXPCU Receive FIFO ran out of space to receive the full 473 MPDU. Therefor this MPDU is terminated early and is thus 474 corrupted. 475 476 This MPDU will not be ACKed. 477 RXPCU might still be able to correctly receive the following 478 MPDUs in the PPDU if enough fifo space became available 479 in time 480 */ 481 482 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 483 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 484 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 485 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 486 487 488 /* Description MSDU_LENGTH_ERR 489 490 Indicates that the MSDU length from the 802.3 encapsulated 491 length field extends beyond the MPDU boundary or if the 492 length is less than 14 bytes. 493 Merged with original "other_msdu_err": Indicates that the 494 MSDU threshold was exceeded and thus all the rest of the 495 MSDUs will not be scattered and will not be decasulated 496 but will be DMA'ed in RAW format as a single MSDU buffer 497 498 */ 499 500 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 501 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 502 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 503 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 504 505 506 /* Description TCP_UDP_CHKSUM_FAIL 507 508 Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') 509 did not match the checksum in the TCP/UDP header. 510 */ 511 512 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 513 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 514 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 515 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 516 517 518 /* Description IP_CHKSUM_FAIL 519 520 Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') 521 did not match the checksum in the IP header. 522 */ 523 524 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 525 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 526 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 527 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 528 529 530 /* Description SA_IDX_INVALID 531 532 Indicates no matching entry was found in the address search 533 table for the source MAC address. 534 */ 535 536 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 537 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 538 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 539 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 540 541 542 /* Description DA_IDX_INVALID 543 544 Indicates no matching entry was found in the address search 545 table for the destination MAC address. 546 */ 547 548 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 549 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 550 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 551 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 552 553 554 /* Description RESERVED_1B 555 556 <legal 0> 557 */ 558 559 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 560 #define RX_ATTENTION_RESERVED_1B_LSB 54 561 #define RX_ATTENTION_RESERVED_1B_MSB 54 562 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 563 564 565 /* Description RX_IN_TX_DECRYPT_BYP 566 567 Indicates that RX packet is not decrypted as Crypto is busy 568 with TX packet processing. 569 */ 570 571 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 572 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 573 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 574 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 575 576 577 /* Description ENCRYPT_REQUIRED 578 579 Indicates that this data type frame is not encrypted even 580 if the policy for this MPDU requires encryption as indicated 581 in the peer entry key type. 582 */ 583 584 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 585 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 586 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 587 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 588 589 590 /* Description DIRECTED 591 592 MPDU is a directed packet which means that the RA matched 593 our STA addresses. In proxySTA it means that the TA matched 594 an entry in our address search table with the corresponding 595 "no_ack" bit is the address search entry cleared. 596 */ 597 598 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 599 #define RX_ATTENTION_DIRECTED_LSB 57 600 #define RX_ATTENTION_DIRECTED_MSB 57 601 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 602 603 604 /* Description BUFFER_FRAGMENT 605 606 Indicates that at least one of the rx buffers has been fragmented. 607 If set the FW should look at the rx_frag_info descriptor 608 described below. 609 */ 610 611 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 612 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 613 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 614 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 615 616 617 /* Description MPDU_LENGTH_ERR 618 619 Indicates that the MPDU was pre-maturely terminated resulting 620 in a truncated MPDU. Don't trust the MPDU length field. 621 622 */ 623 624 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 625 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 626 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 627 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 628 629 630 /* Description TKIP_MIC_ERR 631 632 Indicates that the MPDU Michael integrity check failed 633 */ 634 635 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 636 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 637 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 638 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 639 640 641 /* Description DECRYPT_ERR 642 643 Indicates that the MPDU decrypt integrity check failed or 644 CRYPTO received an encrypted frame, but did not get a valid 645 corresponding key id in the peer entry. 646 */ 647 648 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 649 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 650 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 651 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 652 653 654 /* Description UNENCRYPTED_FRAME_ERR 655 656 Copied here by RX OLE from the RX_MPDU_END TLV 657 */ 658 659 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 660 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 661 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 662 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 663 664 665 /* Description FCS_ERR 666 667 Indicates that the MPDU FCS check failed 668 */ 669 670 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 671 #define RX_ATTENTION_FCS_ERR_LSB 63 672 #define RX_ATTENTION_FCS_ERR_MSB 63 673 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 674 675 676 /* Description FLOW_IDX_TIMEOUT 677 678 Indicates an unsuccessful flow search due to the expiring 679 of the search timer. 680 <legal all> 681 */ 682 683 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 684 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 685 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 686 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 687 688 689 /* Description FLOW_IDX_INVALID 690 691 flow id is not valid 692 <legal all> 693 */ 694 695 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 696 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 697 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 698 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 699 700 701 /* Description WIFI_PARSER_ERROR 702 703 Indicates that the WiFi frame has one of the following errors 704 705 o has less than minimum allowed bytes as per standard 706 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 707 <legal all> 708 */ 709 710 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 711 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 712 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 713 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 714 715 716 /* Description AMSDU_PARSER_ERROR 717 718 A-MSDU could not be properly de-agregated. 719 <legal all> 720 */ 721 722 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 723 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 724 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 725 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 726 727 728 /* Description SA_IDX_TIMEOUT 729 730 Indicates an unsuccessful MAC source address search due 731 to the expiring of the search timer. 732 */ 733 734 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 735 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 736 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 737 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 738 739 740 /* Description DA_IDX_TIMEOUT 741 742 Indicates an unsuccessful MAC destination address search 743 due to the expiring of the search timer. 744 */ 745 746 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 747 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 748 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 749 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 750 751 752 /* Description MSDU_LIMIT_ERROR 753 754 Indicates that the MSDU threshold was exceeded and thus 755 all the rest of the MSDUs will not be scattered and will 756 not be decasulated but will be DMA'ed in RAW format as 757 a single MSDU buffer 758 */ 759 760 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 761 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 762 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 763 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 764 765 766 /* Description DA_IS_VALID 767 768 Indicates that OLE found a valid DA entry 769 */ 770 771 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 772 #define RX_ATTENTION_DA_IS_VALID_LSB 7 773 #define RX_ATTENTION_DA_IS_VALID_MSB 7 774 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 775 776 777 /* Description DA_IS_MCBC 778 779 Field Only valid if "da_is_valid" is set 780 781 Indicates the DA address was a Multicast of Broadcast address. 782 783 */ 784 785 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 786 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 787 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 788 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 789 790 791 /* Description SA_IS_VALID 792 793 Indicates that OLE found a valid SA entry 794 */ 795 796 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 797 #define RX_ATTENTION_SA_IS_VALID_LSB 9 798 #define RX_ATTENTION_SA_IS_VALID_MSB 9 799 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 800 801 802 /* Description DECRYPT_STATUS_CODE 803 804 Field provides insight into the decryption performed 805 806 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 807 properly 808 <enum 1 decrypt_unprotected_frame > Frame is unprotected 809 and hence bypassed 810 <enum 2 decrypt_data_err > Frame has protection enabled 811 and could not be properly decrypted due to MIC/ICV mismatch 812 etc. 813 <enum 3 decrypt_key_invalid > Frame has protection enabled 814 but the key that was required to decrypt this frame was 815 not valid 816 <enum 4 decrypt_peer_entry_invalid > Frame has protection 817 enabled but the key that was required to decrypt this frame 818 was not valid 819 <enum 5 decrypt_other > Reserved for other indications 820 821 <legal 0 - 5> 822 */ 823 824 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 825 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 826 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 827 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 828 829 830 /* Description RX_BITMAP_NOT_UPDATED 831 832 Frame is received, but RXPCU could not update the receive 833 bitmap due to (temporary) fifo contraints. 834 <legal all> 835 */ 836 837 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 838 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 839 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 840 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 841 842 843 /* Description RESERVED_2 844 845 <legal 0> 846 */ 847 848 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 849 #define RX_ATTENTION_RESERVED_2_LSB 14 850 #define RX_ATTENTION_RESERVED_2_MSB 30 851 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 852 853 854 /* Description MSDU_DONE 855 856 If set indicates that the RX packet data, RX header data, 857 RX PPDU start descriptor, RX MPDU start/end descriptor, 858 RX MSDU start/end descriptors and RX Attention descriptor 859 are all valid. This bit must be in the last octet of the 860 descriptor. 861 */ 862 863 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 864 #define RX_ATTENTION_MSDU_DONE_LSB 31 865 #define RX_ATTENTION_MSDU_DONE_MSB 31 866 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 867 868 869 /* Description TLV64_PADDING 870 871 Automatic DWORD padding inserted while converting TLV32 872 to TLV64 for 64 bit ARCH 873 <legal 0> 874 */ 875 876 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 877 #define RX_ATTENTION_TLV64_PADDING_LSB 32 878 #define RX_ATTENTION_TLV64_PADDING_MSB 63 879 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 880 881 882 883 #endif // RX_ATTENTION 884