1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_FLOW_SEARCH_ENTRY_H_ 27 #define _RX_FLOW_SEARCH_ENTRY_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 32 33 34 struct rx_flow_search_entry { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t src_ip_127_96 : 32; // [31:0] 37 uint32_t src_ip_95_64 : 32; // [31:0] 38 uint32_t src_ip_63_32 : 32; // [31:0] 39 uint32_t src_ip_31_0 : 32; // [31:0] 40 uint32_t dest_ip_127_96 : 32; // [31:0] 41 uint32_t dest_ip_95_64 : 32; // [31:0] 42 uint32_t dest_ip_63_32 : 32; // [31:0] 43 uint32_t dest_ip_31_0 : 32; // [31:0] 44 uint32_t src_port : 16, // [15:0] 45 dest_port : 16; // [31:16] 46 uint32_t l4_protocol : 8, // [7:0] 47 valid : 1, // [8:8] 48 reserved_9 : 4, // [12:9] 49 service_code : 9, // [21:13] 50 priority_valid : 1, // [22:22] 51 use_ppe : 1, // [23:23] 52 reo_destination_indication : 5, // [28:24] 53 msdu_drop : 1, // [29:29] 54 reo_destination_handler : 2; // [31:30] 55 uint32_t metadata : 32; // [31:0] 56 uint32_t aggregation_count : 7, // [6:0] 57 lro_eligible : 1, // [7:7] 58 msdu_count : 24; // [31:8] 59 uint32_t msdu_byte_count : 32; // [31:0] 60 uint32_t timestamp : 32; // [31:0] 61 uint32_t cumulative_ip_length_pmac1 : 16, // [15:0] 62 cumulative_ip_length : 16; // [31:16] 63 uint32_t tcp_sequence_number : 32; // [31:0] 64 #else 65 uint32_t src_ip_127_96 : 32; // [31:0] 66 uint32_t src_ip_95_64 : 32; // [31:0] 67 uint32_t src_ip_63_32 : 32; // [31:0] 68 uint32_t src_ip_31_0 : 32; // [31:0] 69 uint32_t dest_ip_127_96 : 32; // [31:0] 70 uint32_t dest_ip_95_64 : 32; // [31:0] 71 uint32_t dest_ip_63_32 : 32; // [31:0] 72 uint32_t dest_ip_31_0 : 32; // [31:0] 73 uint32_t dest_port : 16, // [31:16] 74 src_port : 16; // [15:0] 75 uint32_t reo_destination_handler : 2, // [31:30] 76 msdu_drop : 1, // [29:29] 77 reo_destination_indication : 5, // [28:24] 78 use_ppe : 1, // [23:23] 79 priority_valid : 1, // [22:22] 80 service_code : 9, // [21:13] 81 reserved_9 : 4, // [12:9] 82 valid : 1, // [8:8] 83 l4_protocol : 8; // [7:0] 84 uint32_t metadata : 32; // [31:0] 85 uint32_t msdu_count : 24, // [31:8] 86 lro_eligible : 1, // [7:7] 87 aggregation_count : 7; // [6:0] 88 uint32_t msdu_byte_count : 32; // [31:0] 89 uint32_t timestamp : 32; // [31:0] 90 uint32_t cumulative_ip_length : 16, // [31:16] 91 cumulative_ip_length_pmac1 : 16; // [15:0] 92 uint32_t tcp_sequence_number : 32; // [31:0] 93 #endif 94 }; 95 96 97 /* Description SRC_IP_127_96 98 99 Uppermost 32 bits of source IPv6 address or prefix as per 100 Common Parser register field IP_DA_SA_PREFIX (with the 101 first byte in the MSB and the last byte in the LSB, i.e. 102 requiring a byte-swap for little-endian SW w.r.t. the byte 103 order in an IPv6 packet) 104 <legal all> 105 */ 106 107 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 108 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 109 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 110 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff 111 112 113 /* Description SRC_IP_95_64 114 115 Next 32 bits of source IPv6 address or prefix (requiring 116 a byte-swap for little-endian SW) <legal all> 117 */ 118 119 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 120 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 121 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 122 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff 123 124 125 /* Description SRC_IP_63_32 126 127 Next 32 bits of source IPv6 address or lowest 32 bits of 128 prefix (requiring a byte-swap for little-endian SW) 129 <legal all> 130 */ 131 132 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 133 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 134 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 135 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff 136 137 138 /* Description SRC_IP_31_0 139 140 Lowest 32 bits of source IPv6 address, or source IPv4 address 141 (requiring a byte-swap for little-endian SW w.r.t. the 142 byte order in an IPv6 or IPv4 packet) 143 <legal all> 144 */ 145 146 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c 147 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 148 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 149 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff 150 151 152 /* Description DEST_IP_127_96 153 154 Uppermost 32 bits of destination IPv6 address or prefix 155 as per Common Parser register field IP_DA_SA_PREFIX (with 156 the first byte in the MSB and the last byte in the LSB, 157 i.e. requiring a byte-swap for little-endian SW w.r.t. the 158 byte order as in an IPv6 packet) 159 <legal all> 160 */ 161 162 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 163 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 164 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 165 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff 166 167 168 /* Description DEST_IP_95_64 169 170 Next 32 bits of destination IPv6 address or prefix (requiring 171 a byte-swap for little-endian SW) 172 <legal all> 173 */ 174 175 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 176 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 177 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 178 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff 179 180 181 /* Description DEST_IP_63_32 182 183 Next 32 bits of destination IPv6 address or lowest 32 bits 184 of prefix (requiring a byte-swap for little-endian SW) 185 <legal all> 186 */ 187 188 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 189 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 190 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 191 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff 192 193 194 /* Description DEST_IP_31_0 195 196 Lowest 32 bits of destination IPv6 address, or destination 197 IPv4 address (requiring a byte-swap for little-endian SW 198 w.r.t. the byte order in an IPv6 or IPv4 packet) 199 <legal all> 200 */ 201 202 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c 203 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 204 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 205 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff 206 207 208 /* Description SRC_PORT 209 210 LSB of SPI in case of ESP/AH 211 else source port in case of TCP/UDP without IPsec, 212 else zeros in case of ICMP (with the first/third byte in 213 the MSB and the second/fourth byte in the LSB, i.e. requiring 214 a byte-swap for little-endian SW w.r.t. the byte order 215 as in an IPv6 or IPv4 packet) <legal all> 216 */ 217 218 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 219 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 220 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 221 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff 222 223 224 /* Description DEST_PORT 225 226 MSB of SPI in case of ESP/AH 227 else destination port in case of TCP/UDP without IPsec, 228 else zeros in case of ICMP (with the first byte in the MSB 229 and the second byte in the LSB, i.e. requiring a byte-swap 230 for little-endian SW w.r.t. the byte order as in an IPv6 231 or IPv4 packet) 232 <legal all> 233 */ 234 235 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 236 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 237 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 238 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 239 240 241 /* Description L4_PROTOCOL 242 243 IPsec or L4 protocol 244 245 <enum 1 ICMPV4> 246 <enum 6 TCP> 247 <enum 17 UDP> 248 <enum 50 ESP> 249 <enum 51 AH> 250 <enum 58 ICMPV6> 251 <legal 1, 6, 17, 50, 51, 58> 252 */ 253 254 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 255 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 256 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 257 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff 258 259 260 /* Description VALID 261 262 Indicates validity of entry 263 <legal all> 264 */ 265 266 #define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 267 #define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 268 #define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 269 #define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 270 271 272 /* Description RESERVED_9 273 274 <legal 0> 275 */ 276 277 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 278 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 279 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 280 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 281 282 283 /* Description SERVICE_CODE 284 285 Opaque service code between PPE and Wi-Fi 286 287 This field gets passed on by REO to PPE in the EDMA descriptor 288 ('REO_TO_PPE_RING'). 289 290 <legal all> 291 */ 292 293 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 294 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 295 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 296 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 297 298 299 /* Description PRIORITY_VALID 300 301 This field gets passed on by REO to PPE in the EDMA descriptor 302 ('REO_TO_PPE_RING'). 303 304 <legal all> 305 */ 306 307 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 308 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 309 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 310 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 311 312 313 /* Description USE_PPE 314 315 Indicates to RXDMA to ignore the REO_destination_indication 316 and use a programmed value corresponding to the REO2PPE 317 ring 318 319 This override to REO2PPE for packets requiring multiple 320 buffers shall be disabled based on an RXDMA configuration, 321 as PPE may not support such packets. 322 323 Supported only in full AP chips like Waikiki, not in client/soft 324 AP chips like Hamilton 325 <legal all> 326 */ 327 328 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 329 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 330 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 331 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 332 333 334 /* Description REO_DESTINATION_INDICATION 335 336 The ID of the REO exit ring where the MSDU frame shall push 337 after (MPDU level) reordering has finished. 338 339 <enum 0 reo_destination_sw0> Reo will push the frame into 340 the REO2SW0 ring 341 <enum 1 reo_destination_sw1> Reo will push the frame into 342 the REO2SW1 ring 343 <enum 2 reo_destination_sw2> Reo will push the frame into 344 the REO2SW2 ring 345 <enum 3 reo_destination_sw3> Reo will push the frame into 346 the REO2SW3 ring 347 <enum 4 reo_destination_sw4> Reo will push the frame into 348 the REO2SW4 ring 349 <enum 5 reo_destination_release> Reo will push the frame 350 into the REO_release ring 351 <enum 6 reo_destination_fw> Reo will push the frame into 352 the REO2FW ring 353 <enum 7 reo_destination_sw5> Reo will push the frame into 354 the REO2SW5 ring (REO remaps this in chips without REO2SW5 355 ring, e.g. Pine) 356 <enum 8 reo_destination_sw6> Reo will push the frame into 357 the REO2SW6 ring (REO remaps this in chips without REO2SW6 358 ring, e.g. Pine) 359 <enum 9 reo_destination_sw7> Reo will push the frame into 360 the REO2SW7 ring (REO remaps this in chips without REO2SW7 361 ring) 362 <enum 10 reo_destination_sw8> Reo will push the frame into 363 the REO2SW8 ring (REO remaps this in chips without REO2SW8 364 ring) 365 <enum 11 reo_destination_11> REO remaps this 366 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 367 REO remaps this 368 <enum 14 reo_destination_14> REO remaps this 369 <enum 15 reo_destination_15> REO remaps this 370 <enum 16 reo_destination_16> REO remaps this 371 <enum 17 reo_destination_17> REO remaps this 372 <enum 18 reo_destination_18> REO remaps this 373 <enum 19 reo_destination_19> REO remaps this 374 <enum 20 reo_destination_20> REO remaps this 375 <enum 21 reo_destination_21> REO remaps this 376 <enum 22 reo_destination_22> REO remaps this 377 <enum 23 reo_destination_23> REO remaps this 378 <enum 24 reo_destination_24> REO remaps this 379 <enum 25 reo_destination_25> REO remaps this 380 <enum 26 reo_destination_26> REO remaps this 381 <enum 27 reo_destination_27> REO remaps this 382 <enum 28 reo_destination_28> REO remaps this 383 <enum 29 reo_destination_29> REO remaps this 384 <enum 30 reo_destination_30> REO remaps this 385 <enum 31 reo_destination_31> REO remaps this 386 387 <legal all> 388 */ 389 390 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 391 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 392 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 393 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 394 395 396 /* Description MSDU_DROP 397 398 Overriding indication to REO to forward to REO release ring 399 400 <legal all> 401 */ 402 403 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 404 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 405 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 406 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 407 408 409 /* Description REO_DESTINATION_HANDLER 410 411 Indicates how to decide the REO destination indication 412 <enum 0 RXFT_USE_FT> Follow this entry 413 <enum 1 RXFT_USE_ASPT> Use address search+peer table entry 414 415 <enum 2 RXFT_USE_FT2> Follow this entry 416 <enum 3 RXFT_USE_CCE> Use CCE super-rule 417 <legal all> 418 */ 419 420 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 421 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 422 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 423 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 424 425 426 /* Description METADATA 427 428 Value to be passed to SW if this flow search entry matches 429 430 <legal all> 431 */ 432 433 #define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 434 #define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 435 #define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 436 #define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff 437 438 439 /* Description AGGREGATION_COUNT 440 441 FISA: Number'of MSDU's aggregated so far 442 443 Based on an RXOLE register, this can be changed to reflect 444 aggregation of MSDUs from PMAC0 only. 445 446 Set to zero in chips not supporting FISA, e.g. Pine 447 <legal all> 448 */ 449 450 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c 451 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 452 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 453 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f 454 455 456 /* Description LRO_ELIGIBLE 457 458 FISA: 459 To indicate whether the previous MSDU for this flow is eligible 460 for LRO/FISA 461 462 Based on an RXOLE register, this can be changed to reflect 463 the LRO/FISA eligibility for MSDUs from PMAC0 only. 464 465 Chips not supporting FISA, e.g. Waikiki: 466 This bit is also known as RDI_invalid. 467 When RXOLE is configured to enable flow search (but ignore 468 the REO_destination_indication) for the first fragment, 469 it will set this bit if a flow entry matches. 470 Subsequently when RXOLE matches this flow entry for any 471 other packet, the REO_destination_indication in this entry 472 is considered invalid and w.r.t. REO routing the flow search 473 is considered to have failed. 474 <legal all> 475 */ 476 477 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c 478 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 479 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 480 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 481 482 483 /* Description MSDU_COUNT 484 485 Number of Rx MSDUs matching this flow 486 487 Based on an RXOLE register, this can be changed to reflect 488 the number of Rx MSDUs from PMAC0 matching the flow. 489 <legal all> 490 */ 491 492 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c 493 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 494 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 495 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 496 497 498 /* Description MSDU_BYTE_COUNT 499 500 Number of bytes in Rx MSDUs matching this flow 501 502 Based on an RXOLE register, this can be changed to reflect 503 the number of Rx MSDUs from PMAC1 matching the flow. 504 505 Based on an RXOLE register, the MSB 8 bits can be changed 506 to reflect the 'aggregation_count' and 'LRO_eligible' of 507 MSDUs from PMAC1. 508 <legal all> 509 */ 510 511 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 512 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 513 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 514 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff 515 516 517 /* Description TIMESTAMP 518 519 Time of last reception (as measured at Rx OLE) matching 520 this flow 521 <legal all> 522 */ 523 524 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 525 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 526 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 527 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff 528 529 530 /* Description CUMULATIVE_IP_LENGTH_PMAC1 531 532 Based on an RXOLE register, this can be changed to reflect 533 the 'cumulative_IP_length' for MSDUs from PMAC1. 534 <legal all> 535 */ 536 537 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 538 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 539 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 540 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff 541 542 543 /* Description CUMULATIVE_IP_LENGTH 544 545 FISA: Total MSDU length that is part of this flow aggregated 546 so far 547 548 Based on an RXOLE register, this can be changed to reflect 549 aggregation of MSDUs from PMAC0 only. 550 551 Set to zero in chips not supporting FISA, e.g. Pine 552 <legal all> 553 */ 554 555 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 556 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 557 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 558 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 559 560 561 /* Description TCP_SEQUENCE_NUMBER 562 563 FISA: TCP Sequence number of the last packet in this flow 564 to detect sequence number jump 565 566 Based on an RXOLE register, this can be changed so that 567 the bottom half of this field reflects the LSBs of the TCP 568 sequence number of the last packet from PMAC0 and the top 569 half reflects the LSBs of the TCP sequence number of the 570 last packet from PMAC1. 571 572 Set to zero in chips not supporting FISA, e.g. Pine 573 <legal all> 574 */ 575 576 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c 577 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 578 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 579 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff 580 581 582 583 #endif // RX_FLOW_SEARCH_ENTRY 584