1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_FRAME_1K_BITMAP_ACK_H_ 27 #define _RX_FRAME_1K_BITMAP_ACK_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 32 33 #define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 34 35 36 struct rx_frame_1k_bitmap_ack { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t reserved_0a : 5, // [4:0] 39 ba_bitmap_size : 2, // [6:5] 40 reserved_0b : 3, // [9:7] 41 ba_tid : 4, // [13:10] 42 sta_full_aid : 13, // [26:14] 43 reserved_0c : 5; // [31:27] 44 uint32_t addr1_31_0 : 32; // [31:0] 45 uint32_t addr1_47_32 : 16, // [15:0] 46 addr2_15_0 : 16; // [31:16] 47 uint32_t addr2_47_16 : 32; // [31:0] 48 uint32_t ba_ts_ctrl : 16, // [15:0] 49 ba_ts_seq : 16; // [31:16] 50 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 51 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 52 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 53 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 54 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 55 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 56 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 57 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 58 uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] 59 uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] 60 uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] 61 uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] 62 uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] 63 uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] 64 uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] 65 uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] 66 uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] 67 uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] 68 uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] 69 uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] 70 uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] 71 uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] 72 uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] 73 uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] 74 uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] 75 uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] 76 uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] 77 uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] 78 uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] 79 uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] 80 uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] 81 uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] 82 uint32_t tlv64_padding : 32; // [31:0] 83 #else 84 uint32_t reserved_0c : 5, // [31:27] 85 sta_full_aid : 13, // [26:14] 86 ba_tid : 4, // [13:10] 87 reserved_0b : 3, // [9:7] 88 ba_bitmap_size : 2, // [6:5] 89 reserved_0a : 5; // [4:0] 90 uint32_t addr1_31_0 : 32; // [31:0] 91 uint32_t addr2_15_0 : 16, // [31:16] 92 addr1_47_32 : 16; // [15:0] 93 uint32_t addr2_47_16 : 32; // [31:0] 94 uint32_t ba_ts_seq : 16, // [31:16] 95 ba_ts_ctrl : 16; // [15:0] 96 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 97 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 98 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 99 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 100 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 101 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 102 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 103 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 104 uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] 105 uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] 106 uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] 107 uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] 108 uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] 109 uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] 110 uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] 111 uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] 112 uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] 113 uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] 114 uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] 115 uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] 116 uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] 117 uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] 118 uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] 119 uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] 120 uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] 121 uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] 122 uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] 123 uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] 124 uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] 125 uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] 126 uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] 127 uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] 128 uint32_t tlv64_padding : 32; // [31:0] 129 #endif 130 }; 131 132 133 /* Description RESERVED_0A 134 135 <legal 0> 136 */ 137 138 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 139 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 140 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 141 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f 142 143 144 /* Description BA_BITMAP_SIZE 145 146 <enum 0 BA_bitmap_512 > Bitmap size set to window of 512 147 148 <enum 1 BA_bitmap_1024 > Bitmap size set to window of 1024 149 150 151 <legal 0-1> 152 */ 153 154 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 155 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 156 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 157 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 158 159 160 /* Description RESERVED_0B 161 162 <legal 0> 163 */ 164 165 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 166 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 167 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 168 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 169 170 171 /* Description BA_TID 172 173 The tid for the BA 174 */ 175 176 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 177 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 178 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 179 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 180 181 182 /* Description STA_FULL_AID 183 184 The full AID of this station. 185 */ 186 187 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 188 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 189 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 190 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 191 192 193 /* Description RESERVED_0C 194 195 <legal 0> 196 */ 197 198 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 199 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 200 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 201 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 202 203 204 /* Description ADDR1_31_0 205 206 lower 32 bits of addr1 of the received frame 207 */ 208 209 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 210 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 211 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 212 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 213 214 215 /* Description ADDR1_47_32 216 217 upper 16 bits of addr1 of the received frame 218 */ 219 220 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 221 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 222 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 223 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 224 225 226 /* Description ADDR2_15_0 227 228 lower 16 bits of addr2 of the received frame 229 */ 230 231 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 232 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 233 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 234 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 235 236 237 /* Description ADDR2_47_16 238 239 upper 32 bits of addr2 of the received frame 240 */ 241 242 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 243 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 244 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 245 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 246 247 248 /* Description BA_TS_CTRL 249 250 Transmit BA control 251 RXPCU assumes the C-BA format, NOT M-BA format. 252 In case TXPCU is responding with M-BA, TXPCU will ignore 253 this field. TXPCU will generate it 254 */ 255 256 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 257 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 258 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 259 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 260 261 262 /* Description BA_TS_SEQ 263 264 Transmit BA sequence number. 265 */ 266 267 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 268 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 269 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 270 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 271 272 273 /* Description BA_TS_BITMAP_31_0 274 275 Transmit BA bitmap[31:0] 276 */ 277 278 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 279 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 280 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 281 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 282 283 284 /* Description BA_TS_BITMAP_63_32 285 286 Transmit BA bitmap[63:32] 287 */ 288 289 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 290 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 291 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 292 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 293 294 295 /* Description BA_TS_BITMAP_95_64 296 297 Transmit BA bitmap[95:64] 298 */ 299 300 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 301 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 302 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 303 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 304 305 306 /* Description BA_TS_BITMAP_127_96 307 308 Transmit BA bitmap[127:96] 309 */ 310 311 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 312 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 313 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 314 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 315 316 317 /* Description BA_TS_BITMAP_159_128 318 319 Transmit BA bitmap[159:128] 320 */ 321 322 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 323 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 324 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 325 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 326 327 328 /* Description BA_TS_BITMAP_191_160 329 330 Transmit BA bitmap[191:160] 331 */ 332 333 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 334 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 335 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 336 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 337 338 339 /* Description BA_TS_BITMAP_223_192 340 341 Transmit BA bitmap[223:192] 342 */ 343 344 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 345 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 346 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 347 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 348 349 350 /* Description BA_TS_BITMAP_255_224 351 352 Transmit BA bitmap[255:224] 353 */ 354 355 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 356 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 357 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 358 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 359 360 361 /* Description BA_TS_BITMAP_287_256 362 363 Transmit BA bitmap[287:256] 364 */ 365 366 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 367 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 368 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 369 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 370 371 372 /* Description BA_TS_BITMAP_319_288 373 374 Transmit BA bitmap[319:288] 375 */ 376 377 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 378 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 379 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 380 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff 381 382 383 /* Description BA_TS_BITMAP_351_320 384 385 Transmit BA bitmap[351:320] 386 */ 387 388 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 389 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 390 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 391 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 392 393 394 /* Description BA_TS_BITMAP_383_352 395 396 Transmit BA bitmap[383:352] 397 */ 398 399 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 400 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 401 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 402 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff 403 404 405 /* Description BA_TS_BITMAP_415_384 406 407 Transmit BA bitmap[415:384] 408 */ 409 410 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 411 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 412 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 413 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 414 415 416 /* Description BA_TS_BITMAP_447_416 417 418 Transmit BA bitmap[447:416] 419 */ 420 421 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 422 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 423 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 424 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff 425 426 427 /* Description BA_TS_BITMAP_479_448 428 429 Transmit BA bitmap[479:448] 430 */ 431 432 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 433 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 434 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 435 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 436 437 438 /* Description BA_TS_BITMAP_511_480 439 440 Transmit BA bitmap[511:480] 441 */ 442 443 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 444 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 445 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 446 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff 447 448 449 /* Description BA_TS_BITMAP_543_512 450 451 Transmit BA bitmap[543:512] 452 */ 453 454 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 455 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 456 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 457 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 458 459 460 /* Description BA_TS_BITMAP_575_544 461 462 Transmit BA bitmap[575:544] 463 */ 464 465 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 466 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 467 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 468 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff 469 470 471 /* Description BA_TS_BITMAP_607_576 472 473 Transmit BA bitmap[607:576] 474 */ 475 476 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 477 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 478 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 479 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 480 481 482 /* Description BA_TS_BITMAP_639_608 483 484 Transmit BA bitmap[639:608] 485 */ 486 487 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 488 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 489 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 490 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff 491 492 493 /* Description BA_TS_BITMAP_671_640 494 495 Transmit BA bitmap[671:640] 496 */ 497 498 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 499 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 500 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 501 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 502 503 504 /* Description BA_TS_BITMAP_703_672 505 506 Transmit BA bitmap[703:672] 507 */ 508 509 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 510 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 511 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 512 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff 513 514 515 /* Description BA_TS_BITMAP_735_704 516 517 Transmit BA bitmap[735:704] 518 */ 519 520 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 521 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 522 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 523 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 524 525 526 /* Description BA_TS_BITMAP_767_736 527 528 Transmit BA bitmap[767:736] 529 */ 530 531 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 532 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 533 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 534 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff 535 536 537 /* Description BA_TS_BITMAP_799_768 538 539 Transmit BA bitmap[799:768] 540 */ 541 542 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 543 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 544 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 545 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 546 547 548 /* Description BA_TS_BITMAP_831_800 549 550 Transmit BA bitmap[831:800] 551 */ 552 553 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 554 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 555 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 556 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff 557 558 559 /* Description BA_TS_BITMAP_863_832 560 561 Transmit BA bitmap[863:832] 562 */ 563 564 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 565 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 566 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 567 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 568 569 570 /* Description BA_TS_BITMAP_895_864 571 572 Transmit BA bitmap[895:864] 573 */ 574 575 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 576 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 577 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 578 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff 579 580 581 /* Description BA_TS_BITMAP_927_896 582 583 Transmit BA bitmap[927:896] 584 */ 585 586 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 587 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 588 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 589 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 590 591 592 /* Description BA_TS_BITMAP_959_928 593 594 Transmit BA bitmap[959:928] 595 */ 596 597 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 598 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 599 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 600 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff 601 602 603 /* Description BA_TS_BITMAP_991_960 604 605 Transmit BA bitmap[991:960] 606 */ 607 608 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 609 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 610 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 611 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 612 613 614 /* Description BA_TS_BITMAP_1023_992 615 616 Transmit BA bitmap[1023:992] 617 */ 618 619 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 620 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 621 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 622 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff 623 624 625 /* Description TLV64_PADDING 626 627 Automatic DWORD padding inserted while converting TLV32 628 to TLV64 for 64 bit ARCH 629 <legal 0> 630 */ 631 632 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 633 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 634 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 635 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 636 637 638 639 #endif // RX_FRAME_1K_BITMAP_ACK 640